Searched hist:5 (Results 126 - 150 of 1055) sorted by relevance

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/gem5/ext/fputils/
H A Dfp80.c10480:5d4ebc92d32e Thu Oct 16 05:49:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> ext: Update fputils to rev 6a47fd8358

This patch updates fputils to the latest revision (6a47fd8358) from
the upstream repository (github.com/andysan/fputils). Most notably,
this includes changes that export a limited set of 64-bit float
manipulation and avoids a warning about unused 64-bit floats in clang.
/gem5/ext/fputils/include/fputils/
H A Dfp80.h10480:5d4ebc92d32e Thu Oct 16 05:49:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> ext: Update fputils to rev 6a47fd8358

This patch updates fputils to the latest revision (6a47fd8358) from
the upstream repository (github.com/andysan/fputils). Most notably,
this includes changes that export a limited set of 64-bit float
manipulation and avoids a warning about unused 64-bit floats in clang.
/gem5/src/arch/arm/insts/
H A Dneon64_mem.hh10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
/gem5/src/arch/arm/isa/decoder/
H A Daarch64.isa10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
/gem5/src/arch/arm/isa/insts/
H A Daarch64.isa10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
/gem5/src/arch/mips/
H A DSConsopts5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
H A Ddt_constants.hh5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
/gem5/src/arch/sparc/
H A Dhandlers.hh9085:5f0321c03a26 Mon Jul 02 08:21:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> gcc: Fix warnings for gcc 4.7 and clang 3.1

This patch fixes two warnings, one related to a narrowing conversion
(int to MachInst), and one due to the cast operator for arguments and
a mismatch in const-ness (const void* and void*).
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/
H A Dtranslate.py5927:5e3367b103da Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Do a merge for the zero extension microop.
/gem5/src/arch/x86/regs/
H A Dmsr.hh9875:5cfad3486991 Wed Sep 18 05:28:00 EDT 2013 Andreas Sandberg <andreas@sandberg.pp.se> x86: Expose the raw hash map of MSRs

This patch allows the KVM CPU module to initialize it's MSRs by
enumerating the MSRs in the gem5 x86 implementation.
/gem5/src/arch/arm/freebsd/
H A Dfreebsd.hh11383:5ac090acd180 Thu Mar 17 13:24:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: extend mmap system call to support file backed mmaps

For O3, which has a stat that counts reg reads, there is an additional
reg read per mmap() call since there's an arg we no longer ignore.
Otherwise, stats should not be affected.
/gem5/tests/quick/se/50.vortex/
H A Dtest.py11851:824055fe6b30 Wed Nov 09 15:27:00 EST 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead

The EIOProcess class was removed recently and it was the only other class
which derived from Process. Since every Process invocation is also a
LiveProcess invocation, it makes sense to simplify the organization by
combining the fields from LiveProcess into Process.
/gem5/src/base/
H A Dtypes.cc11990:5fad911cc326 Sun Jan 29 19:00:00 EST 2017 Andreas Sandberg <andreas.sandberg@arm.com> base, sim, dev: Remove SWIG

Remove SWIG guards and SWIG-specific C++ code.

Change-Id: Icaad6720513b6f48153727ef3f70e0dba0df4bee
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2921
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
/gem5/src/arch/riscv/isa/
H A Dmain.isa11726:11950d45640b Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A
extension, which includes atomic memory instructions. These instructions
atomically read a value from memory, modify it with a value contained in a
source register, and store the original memory value in the destination
register and modified value back into memory. Because this requires two
memory accesses and GEM5 does not support two timing memory accesses in
a single instruction, each of these instructions is split into two micro-
ops: A "load" micro-op, which reads the memory, and a "store" micro-op,
which modifies and writes it back. Each atomic memory instruction also has
two bits that acquire and release a lock on its memory location.
Additionally, there are atomic load and store instructions that only either
load or store, but not both, and can acquire or release memory locks.

Note that because the current implementation of RISC-V only supports one
core and one thread, it doesn't make sense to make use of AMO instructions.
However, they do form a standard extension of the RISC-V ISA, so they are
included mostly as a placeholder for when multithreaded execution is
implemented. As a result, any tests for their correctness in a future
patch may be abbreviated.

Patch 1 introduced RISC-V and implemented the base instruction set, RV64I;
patch 2 implemented the integer multiply extension, RV64M; and patch 3
implemented the single- and double-precision floating point extensions,
RV64FD.

Patch 5 will add support for timing, minor, and detailed CPU models that
isn't present in patches 1-4.

[Added missing file amo.isa]
[Replaced information removed from initial patch that was missed during
division into multiple patches.]
[Fixed some minor formatting issues.]
[Fixed oversight where LR and SC didn't have both AQ and RL flags.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
11726:11950d45640b Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A
extension, which includes atomic memory instructions. These instructions
atomically read a value from memory, modify it with a value contained in a
source register, and store the original memory value in the destination
register and modified value back into memory. Because this requires two
memory accesses and GEM5 does not support two timing memory accesses in
a single instruction, each of these instructions is split into two micro-
ops: A "load" micro-op, which reads the memory, and a "store" micro-op,
which modifies and writes it back. Each atomic memory instruction also has
two bits that acquire and release a lock on its memory location.
Additionally, there are atomic load and store instructions that only either
load or store, but not both, and can acquire or release memory locks.

Note that because the current implementation of RISC-V only supports one
core and one thread, it doesn't make sense to make use of AMO instructions.
However, they do form a standard extension of the RISC-V ISA, so they are
included mostly as a placeholder for when multithreaded execution is
implemented. As a result, any tests for their correctness in a future
patch may be abbreviated.

Patch 1 introduced RISC-V and implemented the base instruction set, RV64I;
patch 2 implemented the integer multiply extension, RV64M; and patch 3
implemented the single- and double-precision floating point extensions,
RV64FD.

Patch 5 will add support for timing, minor, and detailed CPU models that
isn't present in patches 1-4.

[Added missing file amo.isa]
[Replaced information removed from initial patch that was missed during
division into multiple patches.]
[Fixed some minor formatting issues.]
[Fixed oversight where LR and SC didn't have both AQ and RL flags.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/
H A Dsimerr10218:5a45f124a2f7 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> tests: Reflect name change in DRAM tests

This patch reflects the recent name change in the DRAM TrafficGen
tests and also tidies up the test directory.
/gem5/src/dev/net/
H A Dpktfifo.cc11701:5e7599457b97 Wed Oct 26 22:48:00 EDT 2016 mlebeane <michael.lebeane@amd.com> dev: Add 'simLength' parameter in EthPacketData
Currently, all the network devices create a 16K buffer for the 'data' field
in EthPacketData, and use 'length' to keep track of the size of the packet
in the buffer. This patch introduces the 'simLength' parameter to
EthPacketData, which is used to hold the effective length of the packet used
for all timing calulations in the simulator. Serialization is performed using
only the useful data in the packet ('length') and not necessarily the entire
original buffer.
/gem5/src/cpu/simple/
H A Dnoncaching.cc13012:5fbc6b9c64bc Tue Mar 15 11:45:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Replace the fastmem with a new CPU model

The AtomicSimpleCPU used to be able to access memory directly to speed
up simulation if no caches are used. This is fine as long as no
switching between CPU models is required. In order to switch to a new
CPU model that requires caches, we currently need to checkpoint the
system and restore it into a new configuration. The new
'atomic_noncaching' memory mode provides a solution that avoids this
issue since caches are bypassed in this mode. This changeset removes
the old fastmem option from the AtomicSimpleCPU and introduces a new
CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.

The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU
used to use when accessing memory in when fastmem was enabled.

This changeset also introduces a new switcheroo test that tests
switching between a NonCachingSimpleCPU and a TimingSimpleCPU with
caches.

Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12419
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/dev/arm/
H A Dvio_mmio.hh12740:beed0805c651 Mon Nov 07 13:21:00 EST 2016 Andreas Sandberg <andreas.sandberg@arm.com> dev-arm: Add a MMIO transport interface for VirtIO

The MMIO interface currently only supports a subset of version 0.9.5
of the VirtIO specification. It has the following known limitations:

* The queue size hint (the QUEUE_NUM register) is ignored.

* Queue alignment is assumed to be hard-coded to
VirtQueue::ALIGN_SIZE (4096 bytes).

* Only 4096 byte pages are currently supported.

Change-Id: Ifd318f5e5bddab0b6a42d8c8af9ff2fbb477f98b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
/gem5/tests/configs/
H A Drealview-switcheroo-noncaching-timing.py13012:5fbc6b9c64bc Tue Mar 15 11:45:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Replace the fastmem with a new CPU model

The AtomicSimpleCPU used to be able to access memory directly to speed
up simulation if no caches are used. This is fine as long as no
switching between CPU models is required. In order to switch to a new
CPU model that requires caches, we currently need to checkpoint the
system and restore it into a new configuration. The new
'atomic_noncaching' memory mode provides a solution that avoids this
issue since caches are bypassed in this mode. This changeset removes
the old fastmem option from the AtomicSimpleCPU and introduces a new
CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.

The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU
used to use when accessing memory in when fastmem was enabled.

This changeset also introduces a new switcheroo test that tests
switching between a NonCachingSimpleCPU and a TimingSimpleCPU with
caches.

Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12419
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/mem/cache/prefetch/
H A Dassociative_set.hh13707:5aab50651a66 Thu Feb 21 15:56:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Add a mechanism to iterate all entries of an AssociativeSet

Added functions to obtain an iterator to access all entries of
an AssociativeSet container.

Change-Id: I1ec555bd97d97e3edaced2b8f61287e922279c26
Reviewed-on: https://gem5-review.googlesource.com/c/16582
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/systemc/ext/systemc_home/include/
H A Dsystemc13687:5d81a7792e59 Fri Feb 08 17:48:00 EST 2019 Gabe Black <gabeblack@google.com> systemc: Add a systemc_home directory which maps to the ext headers.

Some systemc code bases expect to find a SYSTEMC_HOME environment
variable which points to the installed header files provided by
systemc, all under ${SYSTEMC_HOME}/include. The systemc headers in
gem5 are not supposed to be installed anywhere, but to satisfy those
expectations this change creates a dummy systemc_home directory with
an include/ in it which has headers which just include the actual
headers in src/systemc/ext.

More gem5 aware code bases can still access the headers either by
letting gem5's scons environment -I the ext directory, or can do so
themselves if they're not being built by gem5's scons.

Change-Id: I5f2e6bfcf20dd314d525207c2e13ca53474a33f3
Reviewed-on: https://gem5-review.googlesource.com/c/16263
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
H A Dsystemc.h13687:5d81a7792e59 Fri Feb 08 17:48:00 EST 2019 Gabe Black <gabeblack@google.com> systemc: Add a systemc_home directory which maps to the ext headers.

Some systemc code bases expect to find a SYSTEMC_HOME environment
variable which points to the installed header files provided by
systemc, all under ${SYSTEMC_HOME}/include. The systemc headers in
gem5 are not supposed to be installed anywhere, but to satisfy those
expectations this change creates a dummy systemc_home directory with
an include/ in it which has headers which just include the actual
headers in src/systemc/ext.

More gem5 aware code bases can still access the headers either by
letting gem5's scons environment -I the ext directory, or can do so
themselves if they're not being built by gem5's scons.

Change-Id: I5f2e6bfcf20dd314d525207c2e13ca53474a33f3
Reviewed-on: https://gem5-review.googlesource.com/c/16263
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
H A Dtlm13687:5d81a7792e59 Fri Feb 08 17:48:00 EST 2019 Gabe Black <gabeblack@google.com> systemc: Add a systemc_home directory which maps to the ext headers.

Some systemc code bases expect to find a SYSTEMC_HOME environment
variable which points to the installed header files provided by
systemc, all under ${SYSTEMC_HOME}/include. The systemc headers in
gem5 are not supposed to be installed anywhere, but to satisfy those
expectations this change creates a dummy systemc_home directory with
an include/ in it which has headers which just include the actual
headers in src/systemc/ext.

More gem5 aware code bases can still access the headers either by
letting gem5's scons environment -I the ext directory, or can do so
themselves if they're not being built by gem5's scons.

Change-Id: I5f2e6bfcf20dd314d525207c2e13ca53474a33f3
Reviewed-on: https://gem5-review.googlesource.com/c/16263
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
H A Dtlm.h13687:5d81a7792e59 Fri Feb 08 17:48:00 EST 2019 Gabe Black <gabeblack@google.com> systemc: Add a systemc_home directory which maps to the ext headers.

Some systemc code bases expect to find a SYSTEMC_HOME environment
variable which points to the installed header files provided by
systemc, all under ${SYSTEMC_HOME}/include. The systemc headers in
gem5 are not supposed to be installed anywhere, but to satisfy those
expectations this change creates a dummy systemc_home directory with
an include/ in it which has headers which just include the actual
headers in src/systemc/ext.

More gem5 aware code bases can still access the headers either by
letting gem5's scons environment -I the ext directory, or can do so
themselves if they're not being built by gem5's scons.

Change-Id: I5f2e6bfcf20dd314d525207c2e13ca53474a33f3
Reviewed-on: https://gem5-review.googlesource.com/c/16263
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/systemc/ext/systemc_home/include/tlm_utils/
H A Dconvenience_socket_bases.h13687:5d81a7792e59 Fri Feb 08 17:48:00 EST 2019 Gabe Black <gabeblack@google.com> systemc: Add a systemc_home directory which maps to the ext headers.

Some systemc code bases expect to find a SYSTEMC_HOME environment
variable which points to the installed header files provided by
systemc, all under ${SYSTEMC_HOME}/include. The systemc headers in
gem5 are not supposed to be installed anywhere, but to satisfy those
expectations this change creates a dummy systemc_home directory with
an include/ in it which has headers which just include the actual
headers in src/systemc/ext.

More gem5 aware code bases can still access the headers either by
letting gem5's scons environment -I the ext directory, or can do so
themselves if they're not being built by gem5's scons.

Change-Id: I5f2e6bfcf20dd314d525207c2e13ca53474a33f3
Reviewed-on: https://gem5-review.googlesource.com/c/16263
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

Completed in 47 milliseconds

1234567891011>>