Searched hist:4820 (Results 1 - 5 of 5) sorted by relevance
| /gem5/src/mem/ruby/structures/ | ||
| H A D | CacheMemory.hh | 10973:4820cc8408b0 Mon Jul 20 10:15:00 EDT 2015 David Hashe <david.hashe@amd.com> ruby: speed up function used for cache walks This patch adds a few helpful functions that allow .sm files to directly invalidate all cache blocks using a trigger queue rather than rely on each individual cache block to be invalidated via requests from the mandatory queue. |
| H A D | CacheMemory.cc | 10973:4820cc8408b0 Mon Jul 20 10:15:00 EDT 2015 David Hashe <david.hashe@amd.com> ruby: speed up function used for cache walks This patch adds a few helpful functions that allow .sm files to directly invalidate all cache blocks using a trigger queue rather than rely on each individual cache block to be invalidated via requests from the mandatory queue. |
| /gem5/src/arch/x86/ | ||
| H A D | process.cc | 4820:b39cc8dfb9b7 Mon Jul 30 18:42:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Use an mmap base address that matches what an actual machine uses. |
| /gem5/src/cpu/o3/ | ||
| H A D | commit_impl.hh | 12216:70bb3ae0fbfc Tue Jul 25 05:31:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> cpu-o3: Avoid early checker verification for store conditionals The O3CPU allows stores to commit before they are completed and as soon as they enter the store queue. This is the reason why stores are verified by the the checker CPU, separately, once they complete and after they are sent to the memory. Store conditionals, on the other hand, have an additional writeback stage in the pipeline as they return their result to a register, similarly to loads. This is the reason why they do not commit before they receive a response from the memory. This allows store conditionals to be verified by the checker CPU as soon as they commit in the same way as all other non-store insturctions. At the same time, the presense of a checker CPU should not require changes to way we handle instructions. This change removes explicit calls to: * incorrectly set the extra data of the request to 0 (a subsequent call to completeAcc already does this without making any ISA assumptions about the return value of the failed store conditional) * complete failing store conditionals Change-Id: If21d70b21caa55b35e9fdcc50f254c590465d3c3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4820 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | lsq_unit_impl.hh | 12216:70bb3ae0fbfc Tue Jul 25 05:31:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> cpu-o3: Avoid early checker verification for store conditionals The O3CPU allows stores to commit before they are completed and as soon as they enter the store queue. This is the reason why stores are verified by the the checker CPU, separately, once they complete and after they are sent to the memory. Store conditionals, on the other hand, have an additional writeback stage in the pipeline as they return their result to a register, similarly to loads. This is the reason why they do not commit before they receive a response from the memory. This allows store conditionals to be verified by the checker CPU as soon as they commit in the same way as all other non-store insturctions. At the same time, the presense of a checker CPU should not require changes to way we handle instructions. This change removes explicit calls to: * incorrectly set the extra data of the request to 0 (a subsequent call to completeAcc already does this without making any ISA assumptions about the return value of the failed store conditional) * complete failing store conditionals Change-Id: If21d70b21caa55b35e9fdcc50f254c590465d3c3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4820 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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