Searched hist:2015 (Results 326 - 350 of 1505) sorted by relevance
/gem5/src/mem/ruby/system/ | ||
H A D | CacheRecorder.cc | 11108:6342ddf6d733 Wed Sep 16 00:03:00 EDT 2015 David Hashe <david.hashe@amd.com> ruby: rename System.{hh,cc} to RubySystem.{hh,cc} The eventual aim of this change is to pass RubySystem pointers through to objects generated from the SLICC protocol code. Because some of these objects need to dereference their RubySystem pointers, they need access to the System.hh header file. In src/mem/ruby/SConscript, the MakeInclude function creates single-line header files in the build directory that do nothing except include the corresponding header file from the source tree. However, SLICC also generates a list of header files from its symbol table, and writes it to mem/protocol/Types.hh in the build directory. This code assumes that the header file name is the same as the class name. The end result of this is the many of the generated slicc files try to include RubySystem.hh, when the file they really need is System.hh. The path of least resistence is just to rename System.hh to RubySystem.hh. 11061:25b53a7195f7 Sat Aug 29 11:19:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: eliminate type uint64 and int64 These types are being replaced with uint64_t and int64_t. 11049:dfb0aa3f0649 Wed Aug 19 11:02:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: reverts to changeset: bf82f1f7b040 11039:fe230bcf3f38 Fri Aug 14 20:28:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: cache recorder: move check on block size to RubySystem. 11031:3815437cb231 Fri Aug 14 20:28:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: eliminate type uint64 and int64 These types are being replaced with uint64_t and int64_t. 11025:4872dbdea907 Fri Aug 14 01:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: replace Address by Addr This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system. 10991:72781d410e48 Tue Aug 04 00:08:00 EDT 2015 Timothy Jones <timothy.jones@cl.cam.ac.uk> uby: Fix checkpointing and restore There are 2 problems with the existing checkpoint and restore code in ruby. The first is that when the event queue is altered by ruby during serialization, some events that are currently scheduled cannot be found (e.g. the event to stop simulation that always lives on the queue), causing a panic. The second is that ruby is sometimes serialized after the memory system, meaning that the dirty data in its cache is flushed back to memory too late and so isn't included in the checkpoint. These are fixed by implementing memory writeback in ruby, using the same technique of hijacking the event queue, but first descheduling all events that are currently on it. They are saved, along with their scheduled time, so that the event queue can be faithfully reconstructed after writeback has finished. Events with the AutoDelete flag set will delete themselves when they are descheduled, causing an error when attempting to schedule them again. This is fixed by simply not recording them when taking them off the queue. Writeback is still implemented using flushing, so the cache recorder object, that is created to generate the trace and manage flushing, is kept around and used during serialization to write the trace to disk. Committed by: Nilay Vaish <nilay@cs.wisc.edu> 10653:e3fc6bc7f97e Thu Jan 22 05:00:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Clean up Request initialisation This patch tidies up how we create and set the fields of a Request. In essence it tries to use the constructor where possible (as opposed to setPhys and setVirt), thus avoiding spreading the information across a number of locations. In fact, setPhys is made private as part of this patch, and a number of places where we callede setVirt instead uses the appropriate constructor. |
/gem5/src/arch/arm/kvm/ | ||
H A D | arm_cpu.cc | 11178:555325cbf464 Thu Oct 29 08:48:00 EDT 2015 Victor Garcia <victor.garcia@arm.com> kvm, arm: Fix compilation errors due to API changes The checkpoint changes, along with the SMT patches have changed a number of APIs. Adapt the ArmKvmCPU accordingly. 10857:d2d5212578db Mon Jun 01 14:43:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> kvm, arm: Move ARM-specific files to arch/arm/kvm/ This changeset moves the ARM-specific KVM CPU implementation to arch/arm/kvm/. This change is expected to keep the source tree somewhat cleaner as we start adding support for ARMv8 and KVM in-kernel interrupt controller simulation. |
/gem5/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/ | ||
H A D | stats.txt | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes 11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes 11106:878dd30741c4 Wed Sep 16 10:35:00 EDT 2015 Jason Lowe-Power <power.jg@gmail.com> stats: files for regression tests for Learning gem5 scripts Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
/gem5/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/ | ||
H A D | stats.txt | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes 11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes 11106:878dd30741c4 Wed Sep 16 10:35:00 EDT 2015 Jason Lowe-Power <power.jg@gmail.com> stats: files for regression tests for Learning gem5 scripts Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
/gem5/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/ | ||
H A D | stats.txt | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes 11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes 11106:878dd30741c4 Wed Sep 16 10:35:00 EDT 2015 Jason Lowe-Power <power.jg@gmail.com> stats: files for regression tests for Learning gem5 scripts Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
/gem5/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/ | ||
H A D | stats.txt | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes 11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes 11106:878dd30741c4 Wed Sep 16 10:35:00 EDT 2015 Jason Lowe-Power <power.jg@gmail.com> stats: files for regression tests for Learning gem5 scripts Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
/gem5/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/ | ||
H A D | stats.txt | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes 11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes 11106:878dd30741c4 Wed Sep 16 10:35:00 EDT 2015 Jason Lowe-Power <power.jg@gmail.com> stats: files for regression tests for Learning gem5 scripts Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
/gem5/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/ | ||
H A D | stats.txt | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes 10812:bacaefeb126a Thu Apr 30 15:17:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: arm: updates 10754:02621b4f013b Mon Mar 23 06:57:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Final reclassification of quick regressions A few regressions were still considered long, but finished well within the 180 seconds. They are only a handful (mostly mcf in atomic). |
/gem5/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/ | ||
H A D | stats.txt | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes 10812:bacaefeb126a Thu Apr 30 15:17:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: arm: updates 10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long. Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
/gem5/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/ | ||
H A D | stats.txt | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes 10812:bacaefeb126a Thu Apr 30 15:17:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: arm: updates 10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long. Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
/gem5/src/dev/arm/ | ||
H A D | flash_device.hh | 11174:5a9019db4a08 Fri Oct 23 09:51:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> arm: Add missing explicit overrides for ARM devices Make clang >= 3.5 happy when compiling build/ARM/gem5.opt on OSX. 11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions. 10913:38dbdeea7f1f Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor and simplify the drain API The drain() call currently passes around a DrainManager pointer, which is now completely pointless since there is only ever one global DrainManager in the system. It also contains vestiges from the time when SimObjects had to keep track of their child objects that needed draining. This changeset moves all of the DrainState handling to the Drainable base class and changes the drain() and drainResume() calls to reflect this. Particularly, the drain() call has been updated to take no parameters (the DrainManager argument isn't needed) and return a DrainState instead of an unsigned integer (there is no point returning anything other than 0 or 1 any more). Drainable objects should return either DrainState::Draining (equivalent to returning 1 in the old system) if they need more time to drain or DrainState::Drained (equivalent to returning 0 in the old system) if they are already in a consistent state. Returning DrainState::Running is considered an error. Drain done signalling is now done through the signalDrainDone() method in the Drainable class instead of using the DrainManager directly. The new call checks if the state of the object is DrainState::Draining before notifying the drain manager. This means that it is safe to call signalDrainDone() without first checking if the simulator has requested draining. The intention here is to reduce the code needed to implement draining in simple objects. 10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically: * Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section. * Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects. * Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections). * The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects. * Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code. 10801:049eb85e8ea2 Thu Apr 23 13:37:00 EDT 2015 Rene de Jong <rene.dejong@arm.com> arm, dev: Add a NAND flash timing model This adds a NAND flash timing model. This model takes the number of planes into account and is ultimately intended to be used as a high-level performance model for any device using flash. To access the memory, use either readMemory or writeMemory. To make use of the model you will need an interface model such as UFSHostDevice, which is part of a separate patch. At the moment the flash device is part of the ARM device tree since the only use if the UFSHostDevice, and that in turn relies on the ARM GIC. |
/gem5/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/ | ||
H A D | stats.txt | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes 10892:bd37e25fb3b7 Fri Jul 03 10:15:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected. 10726:8a20e2a1562d Mon Mar 02 05:04:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU. |
/gem5/tests/long/se/50.vortex/ref/arm/linux/minor-timing/ | ||
H A D | stats.txt | 11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes 11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes 11103:38f6188421e0 Tue Sep 15 09:14:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent changesets including d0934b57735a 10892:bd37e25fb3b7 Fri Jul 03 10:15:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected. 10852:5b58b4cccfd7 Tue May 26 03:21:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update MinorCPU regressions after accounting fix 10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes 10812:bacaefeb126a Thu Apr 30 15:17:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: arm: updates 10753:48a72150f82c Thu Mar 19 08:41:00 EDT 2015 Steve Reinhardt <stever@gmail.com> stats: update Minor stats due to PF bug fix A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5) inadvertently fixed a bug in the Minor CPU model which caused it to treat software prefetches as regular loads. Prior to this changeset, Minor did an ad-hoc generation of memory commands that left out the PF check; because it now uses the common code that the other CPU models use, it generates prefetches properly. These stat changes reflect the fact that the Minor model now issues SoftPFReqs. 10726:8a20e2a1562d Mon Mar 02 05:04:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU. 10636:9ac724889705 Sun Jan 04 14:02:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: changes due to recent changesets. |
/gem5/src/mem/slicc/ast/ | ||
H A D | InPortDeclAST.py | 11095:12c36d719139 Mon Sep 14 11:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: remove member buffer_expr from Var class This was added by changeset 51f40b101a56. Instead, buffer_expr would now be associated with the InPort class. 11049:dfb0aa3f0649 Wed Aug 19 11:02:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: reverts to changeset: bf82f1f7b040 11030:17240f381d6a Fri Aug 14 20:28:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: use default argument value Before this patch, while one could declare / define a function with default argument values, but the actual function call would require one to specify all the arguments. This patch changes the check for function arguments. Now a function call needs to specify arguments that are at least as much as those with default values and at most the total number of arguments taken as input by the function. 11025:4872dbdea907 Fri Aug 14 01:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: replace Address by Addr This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system. 10984:a86f453a7caa Mon Jul 20 10:15:00 EDT 2015 Brad Beckmann <Brad.Beckmann@amd.com> slicc: enable overloading in functions not in classes For many years the slicc symbol table has supported overloaded functions in external classes. This patch extends that support to functions that are not part of classes (a.k.a. no parent). For example, this support allows slicc to understand that mapAddressToRange is overloaded and the NodeID is an optional parameter. 10981:b300dcda5896 Mon Jul 20 10:15:00 EDT 2015 Brad Beckmann <Brad.Beckmann@amd.com> slicc: improved stalling support in protocols Adds features to allow protocols to reschedule controllers when conditionally stalling within inport logic or actions. Also insures that resource and protocol stalls are re-evaluated the next cycle. 10963:51f40b101a56 Mon Jul 20 10:15:00 EDT 2015 David Hashe <david.hashe@amd.com> slicc: support for multiple message types on the same buffer This patch allows SLICC protocols to use more than one message type with a message buffer. For example, you can declare two in ports as such: in_port(ResponseQueue_in, ResponseMsg, responseFromDir, rank=3) { ... } in_port(tgtResponseQueue_in, TgtResponseMsg, responseFromDir, rank=2) { ... } |
H A D | FuncDeclAST.py | 11049:dfb0aa3f0649 Wed Aug 19 11:02:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: reverts to changeset: bf82f1f7b040 11030:17240f381d6a Fri Aug 14 20:28:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: use default argument value Before this patch, while one could declare / define a function with default argument values, but the actual function call would require one to specify all the arguments. This patch changes the check for function arguments. Now a function call needs to specify arguments that are at least as much as those with default values and at most the total number of arguments taken as input by the function. 10984:a86f453a7caa Mon Jul 20 10:15:00 EDT 2015 Brad Beckmann <Brad.Beckmann@amd.com> slicc: enable overloading in functions not in classes For many years the slicc symbol table has supported overloaded functions in external classes. This patch extends that support to functions that are not part of classes (a.k.a. no parent). For example, this support allows slicc to understand that mapAddressToRange is overloaded and the NodeID is an optional parameter. |
/gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/ | ||
H A D | config.ini | 11356:a80884911971 Sun Jul 19 16:03:00 EDT 2015 Krishnendra Nathella <krinat01@arm.com> cpu: Fix LLSC atomic CPU wakeup Writes to locked memory addresses (LLSC) did not wake up the locking CPU. This can lead to deadlocks on multi-core runs. In AtomicSimpleCPU, recvAtomicSnoop was checking if the incoming packet was an invalidation (isInvalidate) and only then handled a locked snoop. But, writes are seen instead of invalidates when running without caches (fast-forward configurations). As as simple fix, now handleLockedSnoop is also called even if the incoming snoop packet are from writes. 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11245:1c5102c0a7a9 Fri Dec 04 19:11:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to reflect changes to PCI handling 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 11103:38f6188421e0 Tue Sep 15 09:14:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent changesets including d0934b57735a 10736:4433fb00fa7d Mon Mar 09 10:39:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: changes to due to recent set of patches 10636:9ac724889705 Sun Jan 04 14:02:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: changes due to recent changesets. |
/gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ | ||
H A D | config.ini | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 11103:38f6188421e0 Tue Sep 15 09:14:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent changesets including d0934b57735a 11066:969113566d50 Sun Aug 30 01:24:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent changes. 11023:97cf7ba82f0c Fri Aug 14 02:19:00 EDT 2015 Joel Hestness <jthestness@gmail.com> stats: Bump for MessageBuffer, cache latency changes 10736:4433fb00fa7d Mon Mar 09 10:39:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: changes to due to recent set of patches 10645:cd95d4d51659 Sat Jan 10 19:06:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: changes due to recent changesets. |
/gem5/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/ | ||
H A D | stats.txt | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes 11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes 10892:bd37e25fb3b7 Fri Jul 03 10:15:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected. 10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes 10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long. Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
/gem5/src/mem/ruby/common/ | ||
H A D | Histogram.hh | 11061:25b53a7195f7 Sat Aug 29 11:19:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: eliminate type uint64 and int64 These types are being replaced with uint64_t and int64_t. 11049:dfb0aa3f0649 Wed Aug 19 11:02:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: reverts to changeset: bf82f1f7b040 11031:3815437cb231 Fri Aug 14 20:28:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: eliminate type uint64 and int64 These types are being replaced with uint64_t and int64_t. |
H A D | SubBlock.hh | 11049:dfb0aa3f0649 Wed Aug 19 11:02:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: reverts to changeset: bf82f1f7b040 11040:ec668f8466eb Fri Aug 14 20:28:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: SubBlock: refactor code 11025:4872dbdea907 Fri Aug 14 01:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: replace Address by Addr This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system. |
/gem5/src/mem/ruby/structures/ | ||
H A D | TBETable.hh | 11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions. 11111:6da33e720481 Wed Sep 16 12:59:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffer, timer table: significant changes This patch changes MessageBuffer and TimerTable, two structures used for buffering messages by components in ruby. These structures would no longer maintain pointers to clock objects. Functions in these structures have been changed to take as input current time in Tick. Similarly, these structures will not operate on Cycle valued latencies for different operations. The corresponding functions would need to be provided with these latencies by components invoking the relevant functions. These latencies should also be in Ticks. I felt the need for these changes while trying to speed up ruby. The ultimate aim is to eliminate Consumer class and replace it with an EventManager object in the MessageBuffer and TimerTable classes. This object would be used for scheduling events. The event itself would contain information on the object and function to be invoked. In hindsight, it seems I should have done this while I was moving away from use of a single global clock in the memory system. That change led to introduction of clock objects that replaced the global clock object. It never crossed my mind that having clock object pointers is not a good design. And now I really don't like the fact that we have separate consumer, receiver and sender pointers in message buffers. 11025:4872dbdea907 Fri Aug 14 01:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: replace Address by Addr This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system. |
/gem5/src/mem/slicc/symbols/ | ||
H A D | Transition.py | 11209:d5a7a4da9f63 Fri Nov 13 17:30:00 EST 2015 Tony Gutierrez <anthony.gutierrez@amd.com> slicc: fixes for the Address to Addr changeset (11025) misc changes now that Address has become Addr including int to address util function 10984:a86f453a7caa Mon Jul 20 10:15:00 EDT 2015 Brad Beckmann <Brad.Beckmann@amd.com> slicc: enable overloading in functions not in classes For many years the slicc symbol table has supported overloaded functions in external classes. This patch extends that support to functions that are not part of classes (a.k.a. no parent). For example, this support allows slicc to understand that mapAddressToRange is overloaded and the NodeID is an optional parameter. 10964:2b4fe083d17b Mon Jul 20 10:15:00 EDT 2015 David Hashe <david.hashe@amd.com> slicc: support for transitions with a wildcard next state This patches adds support for transitions of the form: transition(START, EVENTS, *) { ACTIONS } This allows a machine to collapse states that differ only in the next state transition to collapse into one, and can help shorten/simplfy some protocols significantly. When * is encountered as an end state of a transition, the next state is determined by calling the machine-specific getNextState function. The next state is determined before any actions of the transition execute, and therefore the next state calculation cannot depend on any of the transition actions. |
/gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/ | ||
H A D | simout | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11245:1c5102c0a7a9 Fri Dec 04 19:11:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to reflect changes to PCI handling 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets |
/gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/ | ||
H A D | simout | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11245:1c5102c0a7a9 Fri Dec 04 19:11:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to reflect changes to PCI handling 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets |
/gem5/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/ | ||
H A D | simout | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11245:1c5102c0a7a9 Fri Dec 04 19:11:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to reflect changes to PCI handling 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets |
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