1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000062 # Number of seconds simulated 4sim_ticks 62333000 # Number of ticks simulated 5final_tick 62333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 472885 # Simulator instruction rate (inst/s) 8host_op_rate 471880 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5205204018 # Simulator tick rate (ticks/s) 10host_mem_usage 636424 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5641 # Number of instructions simulated 13sim_ops 5641 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states 17system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 293 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 430 # Number of read requests responded to by this memory 25system.mem_ctrl.bw_read::cpu.inst 300835833 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 140663854 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 441499687 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 300835833 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 300835833 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 300835833 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 140663854 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 441499687 # Total bandwidth to/from this memory (bytes/s) 33system.mem_ctrl.readReqs 430 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 430 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 27520 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 27520 # Total read bytes from the system interface side 41system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.mem_ctrl.perBankRdBursts::0 25 # Per bank write bursts 46system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts 47system.mem_ctrl.perBankRdBursts::2 0 # Per bank write bursts 48system.mem_ctrl.perBankRdBursts::3 0 # Per bank write bursts 49system.mem_ctrl.perBankRdBursts::4 6 # Per bank write bursts 50system.mem_ctrl.perBankRdBursts::5 3 # Per bank write bursts 51system.mem_ctrl.perBankRdBursts::6 11 # Per bank write bursts 52system.mem_ctrl.perBankRdBursts::7 49 # Per bank write bursts 53system.mem_ctrl.perBankRdBursts::8 53 # Per bank write bursts 54system.mem_ctrl.perBankRdBursts::9 74 # Per bank write bursts 55system.mem_ctrl.perBankRdBursts::10 34 # Per bank write bursts 56system.mem_ctrl.perBankRdBursts::11 19 # Per bank write bursts 57system.mem_ctrl.perBankRdBursts::12 50 # Per bank write bursts 58system.mem_ctrl.perBankRdBursts::13 27 # Per bank write bursts 59system.mem_ctrl.perBankRdBursts::14 72 # Per bank write bursts 60system.mem_ctrl.perBankRdBursts::15 7 # Per bank write bursts 61system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts 62system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts 63system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts 64system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts 65system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts 66system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts 67system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts 68system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts 69system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts 70system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry 79system.mem_ctrl.totGap 62196000 # Total gap between requests 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 430 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) 88system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) 89system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) 90system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) 91system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) 92system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) 93system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) 94system.mem_ctrl.rdQLenPdf::0 430 # What read queue length does an incoming req see 95system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see 96system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see 97system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 241.840708 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 173.064480 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 223.138673 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 41 36.28% 62.83% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::256-383 20 17.70% 80.53% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 8 7.08% 87.61% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.04% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 2 1.77% 93.81% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 3 2.65% 96.46% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::896-1023 1 0.88% 97.35% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation 203system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation 204system.mem_ctrl.totQLat 6850250 # Total ticks spent queuing 205system.mem_ctrl.totMemAccLat 14912750 # Total ticks spent from burst creation until serviced by the DRAM 206system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers 207system.mem_ctrl.avgQLat 15930.81 # Average queueing delay per DRAM burst 208system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.mem_ctrl.avgMemAccLat 34680.81 # Average memory access latency per DRAM burst 210system.mem_ctrl.avgRdBW 441.50 # Average DRAM read bandwidth in MiByte/s 211system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.mem_ctrl.avgRdBWSys 441.50 # Average system read bandwidth in MiByte/s 213system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.mem_ctrl.busUtil 3.45 # Data bus utilization in percentage 216system.mem_ctrl.busUtilRead 3.45 # Data bus utilization in percentage for reads 217system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 219system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.mem_ctrl.readRowHits 316 # Number of row buffer hits during reads 221system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 222system.mem_ctrl.readRowHitRate 73.49 # Row buffer hit rate for reads 223system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 224system.mem_ctrl.avgGap 144641.86 # Average gap between requests 225system.mem_ctrl.pageHitRate 73.49 # Row buffer hit rate, read and write combined 226system.mem_ctrl_0.actEnergy 192780 # Energy for activate commands per rank (pJ) 227system.mem_ctrl_0.preEnergy 98670 # Energy for precharge commands per rank (pJ) 228system.mem_ctrl_0.readEnergy 671160 # Energy for read commands per rank (pJ) 229system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) 231system.mem_ctrl_0.actBackEnergy 2176830 # Energy for active background per rank (pJ) 232system.mem_ctrl_0.preBackEnergy 210240 # Energy for precharge background per rank (pJ) 233system.mem_ctrl_0.actPowerDownEnergy 19527630 # Energy for active power-down per rank (pJ) 234system.mem_ctrl_0.prePowerDownEnergy 3815040 # Energy for precharge power-down per rank (pJ) 235system.mem_ctrl_0.selfRefreshEnergy 1573140 # Energy for self refresh per rank (pJ) 236system.mem_ctrl_0.totalEnergy 33182610 # Total energy per rank (pJ) 237system.mem_ctrl_0.averagePower 532.337778 # Core power per rank (mW) 238system.mem_ctrl_0.totalIdleTime 56494000 # Total Idle time Per DRAM Rank 239system.mem_ctrl_0.memoryStateTime::IDLE 323000 # Time in different power states 240system.mem_ctrl_0.memoryStateTime::REF 2086000 # Time in different power states 241system.mem_ctrl_0.memoryStateTime::SREF 4253250 # Time in different power states 242system.mem_ctrl_0.memoryStateTime::PRE_PDN 9935000 # Time in different power states 243system.mem_ctrl_0.memoryStateTime::ACT 2911750 # Time in different power states 244system.mem_ctrl_0.memoryStateTime::ACT_PDN 42824000 # Time in different power states 245system.mem_ctrl_1.actEnergy 621180 # Energy for activate commands per rank (pJ) 246system.mem_ctrl_1.preEnergy 330165 # Energy for precharge commands per rank (pJ) 247system.mem_ctrl_1.readEnergy 2399040 # Energy for read commands per rank (pJ) 248system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) 250system.mem_ctrl_1.actBackEnergy 5632170 # Energy for active background per rank (pJ) 251system.mem_ctrl_1.preBackEnergy 168480 # Energy for precharge background per rank (pJ) 252system.mem_ctrl_1.actPowerDownEnergy 22617030 # Energy for active power-down per rank (pJ) 253system.mem_ctrl_1.prePowerDownEnergy 64320 # Energy for precharge power-down per rank (pJ) 254system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.mem_ctrl_1.totalEnergy 36749505 # Total energy per rank (pJ) 256system.mem_ctrl_1.averagePower 587.463363 # Core power per rank (mW) 257system.mem_ctrl_1.totalIdleTime 49768000 # Total Idle time Per DRAM Rank 258system.mem_ctrl_1.memoryStateTime::IDLE 176000 # Time in different power states 259system.mem_ctrl_1.memoryStateTime::REF 1843250 # Time in different power states 260system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states 261system.mem_ctrl_1.memoryStateTime::PRE_PDN 167500 # Time in different power states 262system.mem_ctrl_1.memoryStateTime::ACT 10545750 # Time in different power states 263system.mem_ctrl_1.memoryStateTime::ACT_PDN 49600500 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states 265system.cpu.dtb.read_hits 0 # DTB read hits 266system.cpu.dtb.read_misses 0 # DTB read misses 267system.cpu.dtb.read_accesses 0 # DTB read accesses 268system.cpu.dtb.write_hits 0 # DTB write hits 269system.cpu.dtb.write_misses 0 # DTB write misses 270system.cpu.dtb.write_accesses 0 # DTB write accesses 271system.cpu.dtb.hits 0 # DTB hits 272system.cpu.dtb.misses 0 # DTB misses 273system.cpu.dtb.accesses 0 # DTB accesses 274system.cpu.itb.read_hits 0 # DTB read hits 275system.cpu.itb.read_misses 0 # DTB read misses 276system.cpu.itb.read_accesses 0 # DTB read accesses 277system.cpu.itb.write_hits 0 # DTB write hits 278system.cpu.itb.write_misses 0 # DTB write misses 279system.cpu.itb.write_accesses 0 # DTB write accesses 280system.cpu.itb.hits 0 # DTB hits 281system.cpu.itb.misses 0 # DTB misses 282system.cpu.itb.accesses 0 # DTB accesses 283system.cpu.workload.numSyscalls 7 # Number of system calls 284system.cpu.pwrStateResidencyTicks::ON 62333000 # Cumulative time (in ticks) in various power states 285system.cpu.numCycles 62333 # number of cpu cycles simulated 286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 288system.cpu.committedInsts 5641 # Number of instructions committed 289system.cpu.committedOps 5641 # Number of ops (including micro ops) committed 290system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses 291system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 292system.cpu.num_func_calls 191 # number of times a function call or return occured 293system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls 294system.cpu.num_int_insts 4957 # number of integer instructions 295system.cpu.num_fp_insts 2 # number of float instructions 296system.cpu.num_int_register_reads 7072 # number of times the integer registers were read 297system.cpu.num_int_register_writes 3291 # number of times the integer registers were written 298system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 299system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 300system.cpu.num_mem_refs 2037 # number of memory refs 301system.cpu.num_load_insts 1135 # Number of load instructions 302system.cpu.num_store_insts 902 # Number of store instructions 303system.cpu.num_idle_cycles 0 # Number of idle cycles 304system.cpu.num_busy_cycles 62333 # Number of busy cycles 305system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 306system.cpu.idle_fraction 0 # Percentage of idle cycles 307system.cpu.Branches 886 # Number of branches fetched 308system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction 309system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction 310system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction 311system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction 312system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction 313system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction 314system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction 315system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction 316system.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction 317system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction 318system.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction 319system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction 320system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction 321system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction 322system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction 323system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction 324system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction 325system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction 326system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction 327system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction 328system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction 329system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction 330system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction 331system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction 332system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction 333system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction 334system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction 335system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction 336system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction 337system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction 338system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction 339system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction 340system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction 341system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction 342system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 343system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 344system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 345system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 346system.cpu.op_class::total 5642 # Class of executed instruction 347system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states 348system.cpu.dcache.tags.replacements 0 # number of replacements 349system.cpu.dcache.tags.tagsinuse 86.045434 # Cycle average of tags in use 350system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. 351system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. 352system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. 353system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 354system.cpu.dcache.tags.occ_blocks::cpu.data 86.045434 # Average occupied blocks per requestor 355system.cpu.dcache.tags.occ_percent::cpu.data 0.084029 # Average percentage of cache occupancy 356system.cpu.dcache.tags.occ_percent::total 0.084029 # Average percentage of cache occupancy 357system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id 358system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 359system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 360system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id 361system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses 362system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses 363system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states 364system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 365system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 366system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits 367system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits 368system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits 369system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits 370system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits 371system.cpu.dcache.overall_hits::total 1899 # number of overall hits 372system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 373system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 374system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses 375system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses 376system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses 377system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses 378system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses 379system.cpu.dcache.overall_misses::total 137 # number of overall misses 380system.cpu.dcache.ReadReq_miss_latency::cpu.data 10089000 # number of ReadReq miss cycles 381system.cpu.dcache.ReadReq_miss_latency::total 10089000 # number of ReadReq miss cycles 382system.cpu.dcache.WriteReq_miss_latency::cpu.data 5605000 # number of WriteReq miss cycles 383system.cpu.dcache.WriteReq_miss_latency::total 5605000 # number of WriteReq miss cycles 384system.cpu.dcache.demand_miss_latency::cpu.data 15694000 # number of demand (read+write) miss cycles 385system.cpu.dcache.demand_miss_latency::total 15694000 # number of demand (read+write) miss cycles 386system.cpu.dcache.overall_miss_latency::cpu.data 15694000 # number of overall miss cycles 387system.cpu.dcache.overall_miss_latency::total 15694000 # number of overall miss cycles 388system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) 389system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) 390system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 391system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 392system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses 393system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses 394system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses 395system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses 396system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses 397system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses 398system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses 399system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses 400system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses 401system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses 402system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses 403system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses 404system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115965.517241 # average ReadReq miss latency 405system.cpu.dcache.ReadReq_avg_miss_latency::total 115965.517241 # average ReadReq miss latency 406system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 112100 # average WriteReq miss latency 407system.cpu.dcache.WriteReq_avg_miss_latency::total 112100 # average WriteReq miss latency 408system.cpu.dcache.demand_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency 409system.cpu.dcache.demand_avg_miss_latency::total 114554.744526 # average overall miss latency 410system.cpu.dcache.overall_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency 411system.cpu.dcache.overall_avg_miss_latency::total 114554.744526 # average overall miss latency 412system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 413system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 417system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 418system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 419system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 420system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 421system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 422system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 423system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses 424system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 425system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses 426system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9915000 # number of ReadReq MSHR miss cycles 427system.cpu.dcache.ReadReq_mshr_miss_latency::total 9915000 # number of ReadReq MSHR miss cycles 428system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5505000 # number of WriteReq MSHR miss cycles 429system.cpu.dcache.WriteReq_mshr_miss_latency::total 5505000 # number of WriteReq MSHR miss cycles 430system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15420000 # number of demand (read+write) MSHR miss cycles 431system.cpu.dcache.demand_mshr_miss_latency::total 15420000 # number of demand (read+write) MSHR miss cycles 432system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15420000 # number of overall MSHR miss cycles 433system.cpu.dcache.overall_mshr_miss_latency::total 15420000 # number of overall MSHR miss cycles 434system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses 435system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses 436system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 437system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 438system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses 439system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses 440system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses 441system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses 442system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 113965.517241 # average ReadReq mshr miss latency 443system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 113965.517241 # average ReadReq mshr miss latency 444system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 110100 # average WriteReq mshr miss latency 445system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 110100 # average WriteReq mshr miss latency 446system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency 447system.cpu.dcache.demand_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency 448system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency 449system.cpu.dcache.overall_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency 450system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states 451system.cpu.icache.tags.replacements 94 # number of replacements 452system.cpu.icache.tags.tagsinuse 109.768952 # Cycle average of tags in use 453system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks. 454system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks. 455system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks. 456system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 457system.cpu.icache.tags.occ_blocks::cpu.inst 109.768952 # Average occupied blocks per requestor 458system.cpu.icache.tags.occ_percent::cpu.inst 0.428785 # Average percentage of cache occupancy 459system.cpu.icache.tags.occ_percent::total 0.428785 # Average percentage of cache occupancy 460system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id 461system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 462system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id 463system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id 464system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses 465system.cpu.icache.tags.data_accesses 11583 # Number of data accesses 466system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states 467system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits 468system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits 469system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits 470system.cpu.icache.demand_hits::total 5346 # number of demand (read+write) hits 471system.cpu.icache.overall_hits::cpu.inst 5346 # number of overall hits 472system.cpu.icache.overall_hits::total 5346 # number of overall hits 473system.cpu.icache.ReadReq_misses::cpu.inst 297 # number of ReadReq misses 474system.cpu.icache.ReadReq_misses::total 297 # number of ReadReq misses 475system.cpu.icache.demand_misses::cpu.inst 297 # number of demand (read+write) misses 476system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses 477system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses 478system.cpu.icache.overall_misses::total 297 # number of overall misses 479system.cpu.icache.ReadReq_miss_latency::cpu.inst 32151000 # number of ReadReq miss cycles 480system.cpu.icache.ReadReq_miss_latency::total 32151000 # number of ReadReq miss cycles 481system.cpu.icache.demand_miss_latency::cpu.inst 32151000 # number of demand (read+write) miss cycles 482system.cpu.icache.demand_miss_latency::total 32151000 # number of demand (read+write) miss cycles 483system.cpu.icache.overall_miss_latency::cpu.inst 32151000 # number of overall miss cycles 484system.cpu.icache.overall_miss_latency::total 32151000 # number of overall miss cycles 485system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) 486system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) 487system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses 488system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses 489system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses 490system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses 491system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052632 # miss rate for ReadReq accesses 492system.cpu.icache.ReadReq_miss_rate::total 0.052632 # miss rate for ReadReq accesses 493system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 # miss rate for demand accesses 494system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses 495system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses 496system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses 497system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108252.525253 # average ReadReq miss latency 498system.cpu.icache.ReadReq_avg_miss_latency::total 108252.525253 # average ReadReq miss latency 499system.cpu.icache.demand_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency 500system.cpu.icache.demand_avg_miss_latency::total 108252.525253 # average overall miss latency 501system.cpu.icache.overall_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency 502system.cpu.icache.overall_avg_miss_latency::total 108252.525253 # average overall miss latency 503system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 504system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 505system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 506system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 507system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 508system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 509system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses 510system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses 511system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses 512system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses 513system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses 514system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses 515system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31557000 # number of ReadReq MSHR miss cycles 516system.cpu.icache.ReadReq_mshr_miss_latency::total 31557000 # number of ReadReq MSHR miss cycles 517system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31557000 # number of demand (read+write) MSHR miss cycles 518system.cpu.icache.demand_mshr_miss_latency::total 31557000 # number of demand (read+write) MSHR miss cycles 519system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31557000 # number of overall MSHR miss cycles 520system.cpu.icache.overall_mshr_miss_latency::total 31557000 # number of overall MSHR miss cycles 521system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses 522system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses 523system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses 524system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses 525system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses 526system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses 527system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106252.525253 # average ReadReq mshr miss latency 528system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106252.525253 # average ReadReq mshr miss latency 529system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency 530system.cpu.icache.demand_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency 531system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency 532system.cpu.icache.overall_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency 533system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. 534system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. 535system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 536system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 537system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 538system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 539system.l2bus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states 540system.l2bus.trans_dist::ReadResp 384 # Transaction distribution 541system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution 542system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution 543system.l2bus.trans_dist::ReadExResp 50 # Transaction distribution 544system.l2bus.trans_dist::ReadSharedReq 384 # Transaction distribution 545system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes) 546system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) 547system.l2bus.pkt_count::total 962 # Packet count per connected master and slave (bytes) 548system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 19008 # Cumulative packet size per connected master and slave (bytes) 549system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) 550system.l2bus.pkt_size::total 27776 # Cumulative packet size per connected master and slave (bytes) 551system.l2bus.snoops 0 # Total snoops (count) 552system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) 553system.l2bus.snoop_fanout::samples 434 # Request fanout histogram 554system.l2bus.snoop_fanout::mean 0 # Request fanout histogram 555system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram 556system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 557system.l2bus.snoop_fanout::0 434 100.00% 100.00% # Request fanout histogram 558system.l2bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 559system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 560system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 561system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 562system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram 563system.l2bus.snoop_fanout::total 434 # Request fanout histogram 564system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks) 565system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 566system.l2bus.respLayer0.occupancy 891000 # Layer occupancy (ticks) 567system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) 568system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks) 569system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) 570system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states 571system.l2cache.tags.replacements 0 # number of replacements 572system.l2cache.tags.tagsinuse 215.766788 # Cycle average of tags in use 573system.l2cache.tags.total_refs 98 # Total number of references to valid blocks. 574system.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks. 575system.l2cache.tags.avg_refs 0.227907 # Average number of references to valid blocks. 576system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 577system.l2cache.tags.occ_blocks::cpu.inst 129.675199 # Average occupied blocks per requestor 578system.l2cache.tags.occ_blocks::cpu.data 86.091590 # Average occupied blocks per requestor 579system.l2cache.tags.occ_percent::cpu.inst 0.031659 # Average percentage of cache occupancy 580system.l2cache.tags.occ_percent::cpu.data 0.021018 # Average percentage of cache occupancy 581system.l2cache.tags.occ_percent::total 0.052677 # Average percentage of cache occupancy 582system.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id 583system.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 584system.l2cache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id 585system.l2cache.tags.occ_task_id_percent::1024 0.104980 # Percentage of cache occupancy per task id 586system.l2cache.tags.tag_accesses 4654 # Number of tag accesses 587system.l2cache.tags.data_accesses 4654 # Number of data accesses 588system.l2cache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states 589system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits 590system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits 591system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits 592system.l2cache.demand_hits::total 4 # number of demand (read+write) hits 593system.l2cache.overall_hits::cpu.inst 4 # number of overall hits 594system.l2cache.overall_hits::total 4 # number of overall hits 595system.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 596system.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 597system.l2cache.ReadSharedReq_misses::cpu.inst 293 # number of ReadSharedReq misses 598system.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses 599system.l2cache.ReadSharedReq_misses::total 380 # number of ReadSharedReq misses 600system.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses 601system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 602system.l2cache.demand_misses::total 430 # number of demand (read+write) misses 603system.l2cache.overall_misses::cpu.inst 293 # number of overall misses 604system.l2cache.overall_misses::cpu.data 137 # number of overall misses 605system.l2cache.overall_misses::total 430 # number of overall misses 606system.l2cache.ReadExReq_miss_latency::cpu.data 5355000 # number of ReadExReq miss cycles 607system.l2cache.ReadExReq_miss_latency::total 5355000 # number of ReadExReq miss cycles 608system.l2cache.ReadSharedReq_miss_latency::cpu.inst 30582000 # number of ReadSharedReq miss cycles 609system.l2cache.ReadSharedReq_miss_latency::cpu.data 9654000 # number of ReadSharedReq miss cycles 610system.l2cache.ReadSharedReq_miss_latency::total 40236000 # number of ReadSharedReq miss cycles 611system.l2cache.demand_miss_latency::cpu.inst 30582000 # number of demand (read+write) miss cycles 612system.l2cache.demand_miss_latency::cpu.data 15009000 # number of demand (read+write) miss cycles 613system.l2cache.demand_miss_latency::total 45591000 # number of demand (read+write) miss cycles 614system.l2cache.overall_miss_latency::cpu.inst 30582000 # number of overall miss cycles 615system.l2cache.overall_miss_latency::cpu.data 15009000 # number of overall miss cycles 616system.l2cache.overall_miss_latency::total 45591000 # number of overall miss cycles 617system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 618system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 619system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses) 620system.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses) 621system.l2cache.ReadSharedReq_accesses::total 384 # number of ReadSharedReq accesses(hits+misses) 622system.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses 623system.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses 624system.l2cache.demand_accesses::total 434 # number of demand (read+write) accesses 625system.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses 626system.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses 627system.l2cache.overall_accesses::total 434 # number of overall (read+write) accesses 628system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 629system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 630system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.986532 # miss rate for ReadSharedReq accesses 631system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 632system.l2cache.ReadSharedReq_miss_rate::total 0.989583 # miss rate for ReadSharedReq accesses 633system.l2cache.demand_miss_rate::cpu.inst 0.986532 # miss rate for demand accesses 634system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 635system.l2cache.demand_miss_rate::total 0.990783 # miss rate for demand accesses 636system.l2cache.overall_miss_rate::cpu.inst 0.986532 # miss rate for overall accesses 637system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 638system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses 639system.l2cache.ReadExReq_avg_miss_latency::cpu.data 107100 # average ReadExReq miss latency 640system.l2cache.ReadExReq_avg_miss_latency::total 107100 # average ReadExReq miss latency 641system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104375.426621 # average ReadSharedReq miss latency 642system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110965.517241 # average ReadSharedReq miss latency 643system.l2cache.ReadSharedReq_avg_miss_latency::total 105884.210526 # average ReadSharedReq miss latency 644system.l2cache.demand_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency 645system.l2cache.demand_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency 646system.l2cache.demand_avg_miss_latency::total 106025.581395 # average overall miss latency 647system.l2cache.overall_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency 648system.l2cache.overall_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency 649system.l2cache.overall_avg_miss_latency::total 106025.581395 # average overall miss latency 650system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 651system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 653system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 654system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 655system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 657system.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 658system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 293 # number of ReadSharedReq MSHR misses 659system.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses 660system.l2cache.ReadSharedReq_mshr_misses::total 380 # number of ReadSharedReq MSHR misses 661system.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 662system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 663system.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 664system.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 665system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 666system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses 667system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4355000 # number of ReadExReq MSHR miss cycles 668system.l2cache.ReadExReq_mshr_miss_latency::total 4355000 # number of ReadExReq MSHR miss cycles 669system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 24722000 # number of ReadSharedReq MSHR miss cycles 670system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7914000 # number of ReadSharedReq MSHR miss cycles 671system.l2cache.ReadSharedReq_mshr_miss_latency::total 32636000 # number of ReadSharedReq MSHR miss cycles 672system.l2cache.demand_mshr_miss_latency::cpu.inst 24722000 # number of demand (read+write) MSHR miss cycles 673system.l2cache.demand_mshr_miss_latency::cpu.data 12269000 # number of demand (read+write) MSHR miss cycles 674system.l2cache.demand_mshr_miss_latency::total 36991000 # number of demand (read+write) MSHR miss cycles 675system.l2cache.overall_mshr_miss_latency::cpu.inst 24722000 # number of overall MSHR miss cycles 676system.l2cache.overall_mshr_miss_latency::cpu.data 12269000 # number of overall MSHR miss cycles 677system.l2cache.overall_mshr_miss_latency::total 36991000 # number of overall MSHR miss cycles 678system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 679system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 680system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses 681system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 682system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989583 # mshr miss rate for ReadSharedReq accesses 683system.l2cache.demand_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for demand accesses 684system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 685system.l2cache.demand_mshr_miss_rate::total 0.990783 # mshr miss rate for demand accesses 686system.l2cache.overall_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for overall accesses 687system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 688system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses 689system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87100 # average ReadExReq mshr miss latency 690system.l2cache.ReadExReq_avg_mshr_miss_latency::total 87100 # average ReadExReq mshr miss latency 691system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84375.426621 # average ReadSharedReq mshr miss latency 692system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90965.517241 # average ReadSharedReq mshr miss latency 693system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85884.210526 # average ReadSharedReq mshr miss latency 694system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency 695system.l2cache.demand_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency 696system.l2cache.demand_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency 697system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency 698system.l2cache.overall_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency 699system.l2cache.overall_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency 700system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter. 701system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 702system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 703system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 704system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 705system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 706system.membus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states 707system.membus.trans_dist::ReadResp 380 # Transaction distribution 708system.membus.trans_dist::ReadExReq 50 # Transaction distribution 709system.membus.trans_dist::ReadExResp 50 # Transaction distribution 710system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution 711system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 860 # Packet count per connected master and slave (bytes) 712system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) 713system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 27520 # Cumulative packet size per connected master and slave (bytes) 714system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) 715system.membus.snoops 0 # Total snoops (count) 716system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 717system.membus.snoop_fanout::samples 430 # Request fanout histogram 718system.membus.snoop_fanout::mean 0 # Request fanout histogram 719system.membus.snoop_fanout::stdev 0 # Request fanout histogram 720system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 721system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram 722system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 723system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 724system.membus.snoop_fanout::min_value 0 # Request fanout histogram 725system.membus.snoop_fanout::max_value 0 # Request fanout histogram 726system.membus.snoop_fanout::total 430 # Request fanout histogram 727system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) 728system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 729system.membus.respLayer0.occupancy 2298250 # Layer occupancy (ticks) 730system.membus.respLayer0.utilization 3.7 # Layer utilization (%) 731 732---------- End Simulation Statistics ---------- 733