xref: /gem5/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000062                       # Number of seconds simulated
sim_ticks                                    62333000                       # Number of ticks simulated
final_tick                                   62333000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 472885                       # Simulator instruction rate (inst/s)
host_op_rate                                   471880                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5205204018                       # Simulator tick rate (ticks/s)
host_mem_usage                                 636424                       # Number of bytes of host memory used
host_seconds                                     0.01                       # Real time elapsed on the host
sim_insts                                        5641                       # Number of instructions simulated
sim_ops                                          5641                       # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
system.mem_ctrl.bytes_read::cpu.inst            18752                       # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data             8768                       # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total               27520                       # Number of bytes read from this memory
system.mem_ctrl.bytes_inst_read::cpu.inst        18752                       # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_inst_read::total          18752                       # Number of instructions bytes read from this memory
system.mem_ctrl.num_reads::cpu.inst               293                       # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::cpu.data               137                       # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::total                  430                       # Number of read requests responded to by this memory
system.mem_ctrl.bw_read::cpu.inst           300835833                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::cpu.data           140663854                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::total              441499687                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::cpu.inst      300835833                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::total         300835833                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.inst          300835833                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.data          140663854                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::total             441499687                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.readReqs                          430                       # Number of read requests accepted
system.mem_ctrl.writeReqs                           0                       # Number of write requests accepted
system.mem_ctrl.readBursts                        430                       # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrl.writeBursts                         0                       # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrl.bytesReadDRAM                   27520                       # Total number of bytes read from DRAM
system.mem_ctrl.bytesReadWrQ                        0                       # Total number of bytes read from write queue
system.mem_ctrl.bytesWritten                        0                       # Total number of bytes written to DRAM
system.mem_ctrl.bytesReadSys                    27520                       # Total read bytes from the system interface side
system.mem_ctrl.bytesWrittenSys                     0                       # Total written bytes from the system interface side
system.mem_ctrl.servicedByWrQ                       0                       # Number of DRAM read bursts serviced by the write queue
system.mem_ctrl.mergedWrBursts                      0                       # Number of DRAM write bursts merged with an existing one
system.mem_ctrl.neitherReadNorWriteReqs             0                       # Number of requests that are neither read nor write
system.mem_ctrl.perBankRdBursts::0                 25                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::1                  0                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::2                  0                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::3                  0                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::4                  6                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::5                  3                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::6                 11                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::7                 49                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::8                 53                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::9                 74                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::10                34                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::11                19                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::12                50                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::13                27                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::14                72                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::15                 7                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::0                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::1                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::2                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::3                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::4                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::5                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::6                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::7                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::8                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::9                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::10                 0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::11                 0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::12                 0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::13                 0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::14                 0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
system.mem_ctrl.totGap                       62196000                       # Total gap between requests
system.mem_ctrl.readPktSize::0                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::1                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::2                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::3                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::4                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::5                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::6                    430                       # Read request sizes (log2)
system.mem_ctrl.writePktSize::0                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::1                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::2                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::3                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::4                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::5                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::6                     0                       # Write request sizes (log2)
system.mem_ctrl.rdQLenPdf::0                      430                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::1                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::2                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::3                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::4                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::5                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::6                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::7                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::8                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::9                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::10                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::11                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::12                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::13                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::14                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::15                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::16                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::17                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::18                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::19                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::20                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::21                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::22                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::23                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::24                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::25                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::26                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::27                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::28                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::29                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::30                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::31                       0                       # What read queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::0                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::1                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::2                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::3                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::4                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::5                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::6                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::7                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::8                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::9                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::10                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::11                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::12                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::13                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::14                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::15                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::16                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::17                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::18                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::19                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::20                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::21                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::22                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::23                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::24                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::25                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::26                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::27                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::28                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::29                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::30                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::31                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::32                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::33                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::34                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::35                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::36                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::37                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::38                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::39                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::40                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::41                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::42                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::43                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::44                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::45                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::46                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::47                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::48                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::49                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::50                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::51                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::52                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::53                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::54                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::55                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::56                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::57                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::58                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::59                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::60                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
system.mem_ctrl.bytesPerActivate::samples          113                       # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::mean     241.840708                       # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::gmean    173.064480                       # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::stdev    223.138673                       # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::0-127            30     26.55%     26.55% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::128-255           41     36.28%     62.83% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::256-383           20     17.70%     80.53% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::384-511            8      7.08%     87.61% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::512-639            5      4.42%     92.04% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::640-767            2      1.77%     93.81% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::768-895            3      2.65%     96.46% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::896-1023            1      0.88%     97.35% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151            3      2.65%    100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total           113                       # Bytes accessed per row activation
system.mem_ctrl.totQLat                       6850250                       # Total ticks spent queuing
system.mem_ctrl.totMemAccLat                 14912750                       # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat                     2150000                       # Total ticks spent in databus transfers
system.mem_ctrl.avgQLat                      15930.81                       # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
system.mem_ctrl.avgMemAccLat                 34680.81                       # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW                        441.50                       # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgWrBW                          0.00                       # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys                     441.50                       # Average system read bandwidth in MiByte/s
system.mem_ctrl.avgWrBWSys                       0.00                       # Average system write bandwidth in MiByte/s
system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
system.mem_ctrl.busUtil                          3.45                       # Data bus utilization in percentage
system.mem_ctrl.busUtilRead                      3.45                       # Data bus utilization in percentage for reads
system.mem_ctrl.busUtilWrite                     0.00                       # Data bus utilization in percentage for writes
system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
system.mem_ctrl.avgWrQLen                        0.00                       # Average write queue length when enqueuing
system.mem_ctrl.readRowHits                       316                       # Number of row buffer hits during reads
system.mem_ctrl.writeRowHits                        0                       # Number of row buffer hits during writes
system.mem_ctrl.readRowHitRate                  73.49                       # Row buffer hit rate for reads
system.mem_ctrl.writeRowHitRate                   nan                       # Row buffer hit rate for writes
system.mem_ctrl.avgGap                      144641.86                       # Average gap between requests
system.mem_ctrl.pageHitRate                     73.49                       # Row buffer hit rate, read and write combined
system.mem_ctrl_0.actEnergy                    192780                       # Energy for activate commands per rank (pJ)
system.mem_ctrl_0.preEnergy                     98670                       # Energy for precharge commands per rank (pJ)
system.mem_ctrl_0.readEnergy                   671160                       # Energy for read commands per rank (pJ)
system.mem_ctrl_0.writeEnergy                       0                       # Energy for write commands per rank (pJ)
system.mem_ctrl_0.refreshEnergy          4917120.000000                       # Energy for refresh commands per rank (pJ)
system.mem_ctrl_0.actBackEnergy               2176830                       # Energy for active background per rank (pJ)
system.mem_ctrl_0.preBackEnergy                210240                       # Energy for precharge background per rank (pJ)
system.mem_ctrl_0.actPowerDownEnergy         19527630                       # Energy for active power-down per rank (pJ)
system.mem_ctrl_0.prePowerDownEnergy          3815040                       # Energy for precharge power-down per rank (pJ)
system.mem_ctrl_0.selfRefreshEnergy           1573140                       # Energy for self refresh per rank (pJ)
system.mem_ctrl_0.totalEnergy                33182610                       # Total energy per rank (pJ)
system.mem_ctrl_0.averagePower             532.337778                       # Core power per rank (mW)
system.mem_ctrl_0.totalIdleTime              56494000                       # Total Idle time Per DRAM Rank
system.mem_ctrl_0.memoryStateTime::IDLE        323000                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::REF        2086000                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::SREF       4253250                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::PRE_PDN      9935000                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT        2911750                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT_PDN     42824000                       # Time in different power states
system.mem_ctrl_1.actEnergy                    621180                       # Energy for activate commands per rank (pJ)
system.mem_ctrl_1.preEnergy                    330165                       # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.readEnergy                  2399040                       # Energy for read commands per rank (pJ)
system.mem_ctrl_1.writeEnergy                       0                       # Energy for write commands per rank (pJ)
system.mem_ctrl_1.refreshEnergy          4917120.000000                       # Energy for refresh commands per rank (pJ)
system.mem_ctrl_1.actBackEnergy               5632170                       # Energy for active background per rank (pJ)
system.mem_ctrl_1.preBackEnergy                168480                       # Energy for precharge background per rank (pJ)
system.mem_ctrl_1.actPowerDownEnergy         22617030                       # Energy for active power-down per rank (pJ)
system.mem_ctrl_1.prePowerDownEnergy            64320                       # Energy for precharge power-down per rank (pJ)
system.mem_ctrl_1.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
system.mem_ctrl_1.totalEnergy                36749505                       # Total energy per rank (pJ)
system.mem_ctrl_1.averagePower             587.463363                       # Core power per rank (mW)
system.mem_ctrl_1.totalIdleTime              49768000                       # Total Idle time Per DRAM Rank
system.mem_ctrl_1.memoryStateTime::IDLE        176000                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::REF        1843250                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::SREF             0                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::PRE_PDN       167500                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT       10545750                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN     49600500                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.numSyscalls                     7                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON        62333000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                            62333                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                        5641                       # Number of instructions committed
system.cpu.committedOps                          5641                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses                  4957                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
system.cpu.num_func_calls                         191                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts          651                       # number of instructions that are conditional controls
system.cpu.num_int_insts                         4957                       # number of integer instructions
system.cpu.num_fp_insts                             2                       # number of float instructions
system.cpu.num_int_register_reads                7072                       # number of times the integer registers were read
system.cpu.num_int_register_writes               3291                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
system.cpu.num_mem_refs                          2037                       # number of memory refs
system.cpu.num_load_insts                        1135                       # Number of load instructions
system.cpu.num_store_insts                        902                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                      62333                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.Branches                               886                       # Number of branches fetched
system.cpu.op_class::No_OpClass                   641     11.36%     11.36% # Class of executed instruction
system.cpu.op_class::IntAlu                      2960     52.46%     63.82% # Class of executed instruction
system.cpu.op_class::IntMult                        2      0.04%     63.86% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     63.86% # Class of executed instruction
system.cpu.op_class::FloatAdd                       2      0.04%     63.90% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::FloatMultAcc                   0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::FloatMisc                      0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.90% # Class of executed instruction
system.cpu.op_class::MemRead                     1135     20.12%     84.01% # Class of executed instruction
system.cpu.op_class::MemWrite                     902     15.99%    100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite                  0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                       5642                       # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse            86.045434                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                1899                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               137                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             13.861314                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    86.045434                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.084029                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.084029                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          137                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.133789                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              4209                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             4209                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data         1048                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1048                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          851                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            851                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          1899                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             1899                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         1899                       # number of overall hits
system.cpu.dcache.overall_hits::total            1899                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            87                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data           50                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           50                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          137                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            137                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          137                       # number of overall misses
system.cpu.dcache.overall_misses::total           137                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     10089000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     10089000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      5605000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      5605000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     15694000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     15694000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     15694000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     15694000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1135                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1135                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2036                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2036                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2036                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2036                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076652                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.076652                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.055494                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.055494                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.067289                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.067289                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.067289                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.067289                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115965.517241                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 115965.517241                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data       112100                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total       112100                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 114554.744526                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 114554.744526                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 114554.744526                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 114554.744526                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           50                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          137                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          137                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          137                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      9915000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      9915000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5505000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      5505000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     15420000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     15420000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     15420000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     15420000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076652                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076652                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055494                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067289                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.067289                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067289                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.067289                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 113965.517241                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 113965.517241                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data       110100                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total       110100                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 112554.744526                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 112554.744526                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 112554.744526                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 112554.744526                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                94                       # number of replacements
system.cpu.icache.tags.tagsinuse           109.768952                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                5346                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               297                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs                    18                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   109.768952                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.428785                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.428785                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          203                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          141                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.792969                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses             11583                       # Number of tag accesses
system.cpu.icache.tags.data_accesses            11583                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst         5346                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            5346                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          5346                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             5346                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         5346                       # number of overall hits
system.cpu.icache.overall_hits::total            5346                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          297                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           297                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          297                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            297                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          297                       # number of overall misses
system.cpu.icache.overall_misses::total           297                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     32151000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     32151000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     32151000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     32151000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     32151000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     32151000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         5643                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         5643                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         5643                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         5643                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         5643                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         5643                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.052632                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.052632                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.052632                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.052632                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.052632                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.052632                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108252.525253                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 108252.525253                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 108252.525253                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 108252.525253                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 108252.525253                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 108252.525253                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          297                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          297                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          297                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          297                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          297                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          297                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     31557000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     31557000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     31557000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     31557000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     31557000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     31557000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.052632                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.052632                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.052632                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.052632                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.052632                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.052632                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106252.525253                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106252.525253                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106252.525253                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 106252.525253                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106252.525253                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 106252.525253                       # average overall mshr miss latency
system.l2bus.snoop_filter.tot_requests            528                       # Total number of requests made to the snoop filter.
system.l2bus.snoop_filter.hit_single_requests           94                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.l2bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.l2bus.snoop_filter.tot_snoops                0                       # Total number of snoops made to the snoop filter.
system.l2bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l2bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.l2bus.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
system.l2bus.trans_dist::ReadResp                 384                       # Transaction distribution
system.l2bus.trans_dist::CleanEvict                94                       # Transaction distribution
system.l2bus.trans_dist::ReadExReq                 50                       # Transaction distribution
system.l2bus.trans_dist::ReadExResp                50                       # Transaction distribution
system.l2bus.trans_dist::ReadSharedReq            384                       # Transaction distribution
system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side          688                       # Packet count per connected master and slave (bytes)
system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side          274                       # Packet count per connected master and slave (bytes)
system.l2bus.pkt_count::total                     962                       # Packet count per connected master and slave (bytes)
system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side        19008                       # Cumulative packet size per connected master and slave (bytes)
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side         8768                       # Cumulative packet size per connected master and slave (bytes)
system.l2bus.pkt_size::total                    27776                       # Cumulative packet size per connected master and slave (bytes)
system.l2bus.snoops                                 0                       # Total snoops (count)
system.l2bus.snoopTraffic                           0                       # Total snoop traffic (bytes)
system.l2bus.snoop_fanout::samples                434                       # Request fanout histogram
system.l2bus.snoop_fanout::mean                     0                       # Request fanout histogram
system.l2bus.snoop_fanout::stdev                    0                       # Request fanout histogram
system.l2bus.snoop_fanout::underflows               0      0.00%      0.00% # Request fanout histogram
system.l2bus.snoop_fanout::0                      434    100.00%    100.00% # Request fanout histogram
system.l2bus.snoop_fanout::1                        0      0.00%    100.00% # Request fanout histogram
system.l2bus.snoop_fanout::2                        0      0.00%    100.00% # Request fanout histogram
system.l2bus.snoop_fanout::overflows                0      0.00%    100.00% # Request fanout histogram
system.l2bus.snoop_fanout::min_value                0                       # Request fanout histogram
system.l2bus.snoop_fanout::max_value                0                       # Request fanout histogram
system.l2bus.snoop_fanout::total                  434                       # Request fanout histogram
system.l2bus.reqLayer0.occupancy               528000                       # Layer occupancy (ticks)
system.l2bus.reqLayer0.utilization                0.8                       # Layer utilization (%)
system.l2bus.respLayer0.occupancy              891000                       # Layer occupancy (ticks)
system.l2bus.respLayer0.utilization               1.4                       # Layer utilization (%)
system.l2bus.respLayer1.occupancy              411000                       # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization               0.7                       # Layer utilization (%)
system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
system.l2cache.tags.replacements                    0                       # number of replacements
system.l2cache.tags.tagsinuse              215.766788                       # Cycle average of tags in use
system.l2cache.tags.total_refs                     98                       # Total number of references to valid blocks.
system.l2cache.tags.sampled_refs                  430                       # Sample count of references to valid blocks.
system.l2cache.tags.avg_refs                 0.227907                       # Average number of references to valid blocks.
system.l2cache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.l2cache.tags.occ_blocks::cpu.inst   129.675199                       # Average occupied blocks per requestor
system.l2cache.tags.occ_blocks::cpu.data    86.091590                       # Average occupied blocks per requestor
system.l2cache.tags.occ_percent::cpu.inst     0.031659                       # Average percentage of cache occupancy
system.l2cache.tags.occ_percent::cpu.data     0.021018                       # Average percentage of cache occupancy
system.l2cache.tags.occ_percent::total       0.052677                       # Average percentage of cache occupancy
system.l2cache.tags.occ_task_id_blocks::1024          430                       # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::1          356                       # Occupied blocks per task id
system.l2cache.tags.occ_task_id_percent::1024     0.104980                       # Percentage of cache occupancy per task id
system.l2cache.tags.tag_accesses                 4654                       # Number of tag accesses
system.l2cache.tags.data_accesses                4654                       # Number of data accesses
system.l2cache.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
system.l2cache.ReadSharedReq_hits::cpu.inst            4                       # number of ReadSharedReq hits
system.l2cache.ReadSharedReq_hits::total            4                       # number of ReadSharedReq hits
system.l2cache.demand_hits::cpu.inst                4                       # number of demand (read+write) hits
system.l2cache.demand_hits::total                   4                       # number of demand (read+write) hits
system.l2cache.overall_hits::cpu.inst               4                       # number of overall hits
system.l2cache.overall_hits::total                  4                       # number of overall hits
system.l2cache.ReadExReq_misses::cpu.data           50                       # number of ReadExReq misses
system.l2cache.ReadExReq_misses::total             50                       # number of ReadExReq misses
system.l2cache.ReadSharedReq_misses::cpu.inst          293                       # number of ReadSharedReq misses
system.l2cache.ReadSharedReq_misses::cpu.data           87                       # number of ReadSharedReq misses
system.l2cache.ReadSharedReq_misses::total          380                       # number of ReadSharedReq misses
system.l2cache.demand_misses::cpu.inst            293                       # number of demand (read+write) misses
system.l2cache.demand_misses::cpu.data            137                       # number of demand (read+write) misses
system.l2cache.demand_misses::total               430                       # number of demand (read+write) misses
system.l2cache.overall_misses::cpu.inst           293                       # number of overall misses
system.l2cache.overall_misses::cpu.data           137                       # number of overall misses
system.l2cache.overall_misses::total              430                       # number of overall misses
system.l2cache.ReadExReq_miss_latency::cpu.data      5355000                       # number of ReadExReq miss cycles
system.l2cache.ReadExReq_miss_latency::total      5355000                       # number of ReadExReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.inst     30582000                       # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.data      9654000                       # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::total     40236000                       # number of ReadSharedReq miss cycles
system.l2cache.demand_miss_latency::cpu.inst     30582000                       # number of demand (read+write) miss cycles
system.l2cache.demand_miss_latency::cpu.data     15009000                       # number of demand (read+write) miss cycles
system.l2cache.demand_miss_latency::total     45591000                       # number of demand (read+write) miss cycles
system.l2cache.overall_miss_latency::cpu.inst     30582000                       # number of overall miss cycles
system.l2cache.overall_miss_latency::cpu.data     15009000                       # number of overall miss cycles
system.l2cache.overall_miss_latency::total     45591000                       # number of overall miss cycles
system.l2cache.ReadExReq_accesses::cpu.data           50                       # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadExReq_accesses::total           50                       # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadSharedReq_accesses::cpu.inst          297                       # number of ReadSharedReq accesses(hits+misses)
system.l2cache.ReadSharedReq_accesses::cpu.data           87                       # number of ReadSharedReq accesses(hits+misses)
system.l2cache.ReadSharedReq_accesses::total          384                       # number of ReadSharedReq accesses(hits+misses)
system.l2cache.demand_accesses::cpu.inst          297                       # number of demand (read+write) accesses
system.l2cache.demand_accesses::cpu.data          137                       # number of demand (read+write) accesses
system.l2cache.demand_accesses::total             434                       # number of demand (read+write) accesses
system.l2cache.overall_accesses::cpu.inst          297                       # number of overall (read+write) accesses
system.l2cache.overall_accesses::cpu.data          137                       # number of overall (read+write) accesses
system.l2cache.overall_accesses::total            434                       # number of overall (read+write) accesses
system.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.l2cache.ReadSharedReq_miss_rate::cpu.inst     0.986532                       # miss rate for ReadSharedReq accesses
system.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
system.l2cache.ReadSharedReq_miss_rate::total     0.989583                       # miss rate for ReadSharedReq accesses
system.l2cache.demand_miss_rate::cpu.inst     0.986532                       # miss rate for demand accesses
system.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.l2cache.demand_miss_rate::total       0.990783                       # miss rate for demand accesses
system.l2cache.overall_miss_rate::cpu.inst     0.986532                       # miss rate for overall accesses
system.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.l2cache.overall_miss_rate::total      0.990783                       # miss rate for overall accesses
system.l2cache.ReadExReq_avg_miss_latency::cpu.data       107100                       # average ReadExReq miss latency
system.l2cache.ReadExReq_avg_miss_latency::total       107100                       # average ReadExReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104375.426621                       # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110965.517241                       # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::total 105884.210526                       # average ReadSharedReq miss latency
system.l2cache.demand_avg_miss_latency::cpu.inst 104375.426621                       # average overall miss latency
system.l2cache.demand_avg_miss_latency::cpu.data 109554.744526                       # average overall miss latency
system.l2cache.demand_avg_miss_latency::total 106025.581395                       # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.inst 104375.426621                       # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.data 109554.744526                       # average overall miss latency
system.l2cache.overall_avg_miss_latency::total 106025.581395                       # average overall miss latency
system.l2cache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.l2cache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.l2cache.blocked::no_targets                  0                       # number of cycles access was blocked
system.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
system.l2cache.ReadExReq_mshr_misses::total           50                       # number of ReadExReq MSHR misses
system.l2cache.ReadSharedReq_mshr_misses::cpu.inst          293                       # number of ReadSharedReq MSHR misses
system.l2cache.ReadSharedReq_mshr_misses::cpu.data           87                       # number of ReadSharedReq MSHR misses
system.l2cache.ReadSharedReq_mshr_misses::total          380                       # number of ReadSharedReq MSHR misses
system.l2cache.demand_mshr_misses::cpu.inst          293                       # number of demand (read+write) MSHR misses
system.l2cache.demand_mshr_misses::cpu.data          137                       # number of demand (read+write) MSHR misses
system.l2cache.demand_mshr_misses::total          430                       # number of demand (read+write) MSHR misses
system.l2cache.overall_mshr_misses::cpu.inst          293                       # number of overall MSHR misses
system.l2cache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
system.l2cache.overall_mshr_misses::total          430                       # number of overall MSHR misses
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4355000                       # number of ReadExReq MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_latency::total      4355000                       # number of ReadExReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     24722000                       # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7914000                       # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::total     32636000                       # number of ReadSharedReq MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.inst     24722000                       # number of demand (read+write) MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.data     12269000                       # number of demand (read+write) MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::total     36991000                       # number of demand (read+write) MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.inst     24722000                       # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.data     12269000                       # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::total     36991000                       # number of overall MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst     0.986532                       # mshr miss rate for ReadSharedReq accesses
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
system.l2cache.ReadSharedReq_mshr_miss_rate::total     0.989583                       # mshr miss rate for ReadSharedReq accesses
system.l2cache.demand_mshr_miss_rate::cpu.inst     0.986532                       # mshr miss rate for demand accesses
system.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.l2cache.demand_mshr_miss_rate::total     0.990783                       # mshr miss rate for demand accesses
system.l2cache.overall_mshr_miss_rate::cpu.inst     0.986532                       # mshr miss rate for overall accesses
system.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.l2cache.overall_mshr_miss_rate::total     0.990783                       # mshr miss rate for overall accesses
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        87100                       # average ReadExReq mshr miss latency
system.l2cache.ReadExReq_avg_mshr_miss_latency::total        87100                       # average ReadExReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84375.426621                       # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90965.517241                       # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85884.210526                       # average ReadSharedReq mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84375.426621                       # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 89554.744526                       # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::total 86025.581395                       # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84375.426621                       # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 89554.744526                       # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::total 86025.581395                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests           430                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED     62333000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                380                       # Transaction distribution
system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           380                       # Transaction distribution
system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port          860                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    860                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port        27520                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   27520                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               430                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     430    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 430                       # Request fanout histogram
system.membus.reqLayer0.occupancy              430000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer0.occupancy            2298250                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              3.7                       # Layer utilization (%)

---------- End Simulation Statistics   ----------