Searched hist:2011 (Results 26 - 50 of 897) sorted by relevance

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/gem5/util/statetrace/arch/sparc/
H A Dtracechild.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
/gem5/util/statetrace/arch/amd64/
H A Dtracechild.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
/gem5/src/cpu/testers/memtest/
H A DSConscript8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags
/gem5/src/unittest/
H A Dcprintftime.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/system/alpha/h/
H A Dtlaser.h8029:442f90a944eb Wed Feb 16 01:34:00 EST 2011 Nathan Binkert <nate@binkert.org> copyright: update copyright on alpha system files
/gem5/src/arch/alpha/
H A Dregredir.cc8780:89e0822462a1 Tue Nov 01 07:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of uses of FULL_SYSTEM in Alpha.
/gem5/src/arch/power/
H A Dvtophys.cc8759:e9455f81588f Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Power: Add a stub implementation for vtophys in SE and FS.
H A Dfaults.hh8591:8f23aeaf6a91 Tue Sep 27 03:24:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Faults: Replace calls to genMachineCheckFault with M5PanicFault.
8569:498d3aacd292 Mon Sep 19 09:17:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Faults: Get rid of the unused isAlignmentFault and isMachineCheckFault.

These functions aren't called anywhere and are probably only theoretically
useful.
7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
H A Dvtophys.hh8759:e9455f81588f Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Power: Add a stub implementation for vtophys in SE and FS.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
/gem5/system/arm/simple_bootloader/
H A Dsimple.S8280:5dddde1126c2 Wed May 04 21:38:00 EDT 2011 Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com> ARM: Boot loader changes that make it more flexible about load and I/O addrs
7843:fb777f10f3df Tue Jan 18 17:29:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add code for a simple bootloader for MP boot.
/gem5/src/dev/x86/
H A Dsouth_bridge.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/ext/libelf/
H A D_libelf.h8349:931ef19535e0 Mon Jun 13 02:51:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> LibElf: Build the error management code in libelf.

This change makes some minor changes to get the error management code in
libelf to build on Linux and to build it into the library.
H A Delf_errmsg.c8349:931ef19535e0 Mon Jun 13 02:51:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> LibElf: Build the error management code in libelf.

This change makes some minor changes to get the error management code in
libelf to build on Linux and to build it into the library.
/gem5/src/arch/x86/regs/
H A DSConscript8582:dd79a696b91c Fri Sep 23 05:42:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Move the MSR lookup table out of the TLB and into its own file.

Translating MSR addresses into MSR register indices took a lot of space in the
TLB source and made looking around in that file awkward. This change moves
the lookup into its own file to get it out of the way. It also changes it from
a switch statement to a hash map which should hopefully be a little more
efficient.
H A Dmsr.cc8582:dd79a696b91c Fri Sep 23 05:42:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Move the MSR lookup table out of the TLB and into its own file.

Translating MSR addresses into MSR register indices took a lot of space in the
TLB source and made looking around in that file awkward. This change moves
the lookup into its own file to get it out of the way. It also changes it from
a switch statement to a hash map which should hopefully be a little more
efficient.
/gem5/src/cpu/o3/
H A Dthread_context.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/arm/isa/insts/
H A Dmult.isa8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
8304:16911ff780d3 Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Construct the predicate test register for more instruction programatically.

If one of the condition codes isn't being used in the execution we should only
read it if the instruction might be dependent on it. With the preeceding changes
there are several more cases where we should dynamically pick instead of assuming
as we did before.
8303:5a95f1d2494e Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
8302:9f23d01421de Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Remove the saturating (Q) condition code from the renamed register.

Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
8301:858384f3af1c Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Break up condition codes into normal flags, saturation, and simd.

This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.
8206:c3090dc00ddf Mon Apr 04 12:42:00 EDT 2011 William Wang <William.Wang@arm.com> ARM: Cleanup and small fixes to some NEON ops to match the spec.

Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
/gem5/src/base/stats/
H A Dinfo.hh8514:57c96df312a1 Fri Aug 19 16:08:00 EDT 2011 Thomas Grass <Thomas.Grass@ARM.com> Stats: Add a sparse histogram stat object.
8296:be7f03723412 Thu May 12 14:19:00 EDT 2011 Nathan Binkert <nate@binkert.org> stats: move code that loops over all stats into python
8243:63e849f0f341 Wed Apr 20 14:14:00 EDT 2011 Brad Danofsky <bradley.danofsky@amd.com> stats: add user settable separator string for arrayed stats

Default is '::', so no visible change unless it is overridden
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7831:c1e158414648 Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> stats: Add a histogram statistic type
7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
/gem5/src/base/vnc/
H A DSConscript8739:925f15f96322 Fri Sep 30 03:28:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the devices in SE mode.
8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags
7949:e59dac494020 Fri Feb 11 19:29:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> VNC: Add VNC server to M5
/gem5/src/dev/alpha/
H A DAlphaBackdoor.py8789:a8b63a0ee14c Sun Nov 13 05:05:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in dev.
8742:9df38d259935 Tue Oct 04 05:26:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Put platform pointers in fewer objects.

Not all objects need a platform pointer, and having one creates a dependence
on their being a platform object. This change removes the platform pointer to
from the base device object and moves it into subclasses that actually need
it.
8739:925f15f96322 Fri Sep 30 03:28:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the devices in SE mode.
/gem5/src/dev/arm/
H A Da9scu.hh8282:0cc4594abf28 Wed May 04 21:38:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add snoop control unit device.
/gem5/src/arch/sparc/
H A Dnativetrace.hh7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
/gem5/src/arch/x86/
H A Dnativetrace.hh7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
/gem5/src/mem/ruby/network/fault_model/
H A DSConscript8612:df3b7a1e883f Fri Nov 04 18:40:00 EDT 2011 Tushar Krishna <tushar@csail.mit.edu> GARNET: adding a fault model for resilient on-chip network research.

This patch adds a fault model, which provides the probability of a number of
architectural faults in the interconnection network (e.g., data corruption,
misrouting). These probabilities can be used to realistically inject faults
in GARNET and faithfully evaluate the effectiveness of novel resilient NoC
architectures.
/gem5/src/mem/ruby/network/simple/
H A DSimpleLink.cc8258:7c377f5162f8 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: basic link bw for garnet and simple networks

This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology. To do so, the patch generalizes the specification
of bw for basic links. This value is then translated to the specific value
used by the simple and Garnet networks. Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.

Completed in 69 milliseconds

1234567891011>>