17843SAli.Saidi@ARM.com/* 27843SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37843SAli.Saidi@ARM.com * All rights reserved 47843SAli.Saidi@ARM.com * 57843SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67843SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77843SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87843SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97843SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107843SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117843SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127843SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137843SAli.Saidi@ARM.com * 147843SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157843SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167843SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177843SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187843SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197843SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207843SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217843SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227843SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237843SAli.Saidi@ARM.com * this software without specific prior written permission. 247843SAli.Saidi@ARM.com * 257843SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267843SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277843SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287843SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297843SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307843SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317843SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327843SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337843SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347843SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357843SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367843SAli.Saidi@ARM.com * 377843SAli.Saidi@ARM.com * Authors: Ali Saidi 387843SAli.Saidi@ARM.com */ 397843SAli.Saidi@ARM.com 407843SAli.Saidi@ARM.com/************************************************************************* 417843SAli.Saidi@ARM.com * Super simple bootloader 427843SAli.Saidi@ARM.com * Preserve loaded values that we need to pass to the kernel (r0, r1, r2) 437843SAli.Saidi@ARM.com * Additionally M5 puts the kernel start address in r3 447843SAli.Saidi@ARM.com * 457843SAli.Saidi@ARM.com * Upon executing this code: 467843SAli.Saidi@ARM.com * r0 = 0, r1 = machine number, r2 = atags ptr 478280SPrakash.Ramrakhyani@arm.com * r3 = kernel start address, r4 = GIC address, r5 = flag register address 487843SAli.Saidi@ARM.com * 497843SAli.Saidi@ARM.com * CPU 0 should branch to the kernel start address and it's done with 507843SAli.Saidi@ARM.com * the boot loader. Other CPUs need to start in a wfi loop. When CPU0 sends 517843SAli.Saidi@ARM.com * an IPI the slave CPUs reads a register which CPU0 has programmed with the 527843SAli.Saidi@ARM.com * boot address for the secondary cpu 537843SAli.Saidi@ARM.com **************************************************************************/ 547843SAli.Saidi@ARM.com.text 557843SAli.Saidi@ARM.com.globl _start 567843SAli.Saidi@ARM.com.extern main 577843SAli.Saidi@ARM.com_start: 587843SAli.Saidi@ARM.com_entry: 598280SPrakash.Ramrakhyani@arm.com b bootldr // All the interrupt vectors jump to the boot loader 608280SPrakash.Ramrakhyani@arm.com b bootldr 618280SPrakash.Ramrakhyani@arm.com b bootldr 628280SPrakash.Ramrakhyani@arm.com b bootldr 638280SPrakash.Ramrakhyani@arm.com b bootldr 648280SPrakash.Ramrakhyani@arm.com b bootldr 658280SPrakash.Ramrakhyani@arm.com b bootldr 668280SPrakash.Ramrakhyani@arm.com b bootldr 678280SPrakash.Ramrakhyani@arm.com b bootldr 688280SPrakash.Ramrakhyani@arm.com 698280SPrakash.Ramrakhyani@arm.combootldr: 708280SPrakash.Ramrakhyani@arm.com mrc p15, 0, r8, c0, c0, 5 // get the MPIDR register 719190SMatt.Evans@arm.com bics r8, r8, #0xff000000 // isolate the lower 24 bits (affinity levels) 727843SAli.Saidi@ARM.com bxeq r3 // if it's 0 (CPU 0), branch to kernel 738280SPrakash.Ramrakhyani@arm.com mov r8, #1 748280SPrakash.Ramrakhyani@arm.com str r8, [r4, #0] // Enable CPU interface on GIC 758280SPrakash.Ramrakhyani@arm.com wfi // wait for an interrupt 767843SAli.Saidi@ARM.compen: 778280SPrakash.Ramrakhyani@arm.com ldr r8, [r5] // load the value 788280SPrakash.Ramrakhyani@arm.com movs r8, r8 // set the flags on this value 797843SAli.Saidi@ARM.com beq pen // if it's zero try again 808280SPrakash.Ramrakhyani@arm.com bx r8 // Jump to where we've been told 817843SAli.Saidi@ARM.com bkpt // We should never get here 82