1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40/*************************************************************************
41 * Super simple bootloader
42 * Preserve loaded values that we need to pass to the kernel (r0, r1, r2)
43 * Additionally M5 puts the kernel start address in r3
44 *
45 * Upon executing this code:
46 * r0 = 0, r1 = machine number, r2 = atags ptr
47 * r3 = kernel start address, r4 = GIC address, r5 = flag register address
48 *
49 * CPU 0 should branch to the kernel start address and it's done with
50 * the boot loader. Other CPUs need to start in a wfi loop. When CPU0 sends
51 * an IPI the slave CPUs reads a register which CPU0 has programmed with the
52 * boot address for the secondary cpu
53 **************************************************************************/
54.text
55.globl  _start
56.extern	main
57_start:
58_entry:
59    b bootldr // All the interrupt vectors jump to the boot loader
60    b bootldr
61    b bootldr
62    b bootldr
63    b bootldr
64    b bootldr
65    b bootldr
66    b bootldr
67    b bootldr
68
69bootldr:
70    mrc p15, 0, r8, c0, c0, 5 // get the MPIDR register
71    bics r8, r8, #0xff000000  // isolate the lower 24 bits (affinity levels)
72    bxeq r3                   // if it's 0 (CPU 0), branch to kernel
73    mov  r8, #1
74    str  r8, [r4, #0]         //  Enable CPU interface on GIC
75    wfi                       //  wait for an interrupt
76pen:
77    ldr r8, [r5]              // load the value
78    movs r8, r8               // set the flags on this value
79    beq pen                   // if it's zero try again
80    bx r8                     // Jump to where we've been told
81    bkpt                      // We should never get here
82