Searched hist:2007 (Results 351 - 375 of 895) sorted by relevance
/gem5/src/arch/x86/ | ||
H A D | emulenv.hh | 4863:b6dacc9a39ff Sat Aug 04 23:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing segmentation support. Make instructions observe segment prefixes, default segment rules, segment base addresses. Also fix some microcode and add sib and riprel "keywords" to the x86 specialization of the microassembler. 4604:3ffdd00e6c02 Wed Jun 20 15:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Forgot to check these in... |
H A D | locked_mem.hh | 4151:1060a0f82bdd Mon Mar 05 11:08:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Stub implementation for x86 4120:3e09b5d32c45 Sat Mar 03 11:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add build hooks for x86. |
/gem5/src/arch/sparc/solaris/ | ||
H A D | process.hh | 5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack. 5128:69fb816fa927 Thu Oct 04 03:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Make software trap 3 flush the register windows like the ABI specifies. |
/gem5/ | ||
H A D | .hgignore | 4939:80c00f93a418 Fri Aug 03 19:27:00 EDT 2007 Steve Reinhardt <stever@gmail.com> Add cscope files to .hgignore. 4677:50d1e67c44ec Sat Jul 14 01:39:00 EDT 2007 Nathan Binkert <nate@binkert.org> ignore stuff that we don't want to see in the status |
/gem5/src/arch/mips/ | ||
H A D | dsp.cc | 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode 4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1 src/arch/mips/SConscript: "mips import pt.1". |
H A D | tlb.hh | 5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers 5225:b1de028eea16 Wed Nov 14 15:33:00 EST 2007 Korey Sewell <ksewell@umich.edu> comment and spacing 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode 5184:8782de2949e5 Thu Oct 25 22:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system. 5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors. SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) 5019:2762e580f5db Tue Aug 28 17:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: De-templatize the GenericTLB class. 5014:f9667cf03d3f Mon Aug 27 21:29:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> MIPS: Fixes to get mips to compile. 4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. |
/gem5/src/cpu/ | ||
H A D | func_unit.cc | 5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors. SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. |
/gem5/ext/libelf/ | ||
H A D | SConscript | 5274:7888bf966443 Mon Nov 19 18:23:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Compiling: Make sure that libelf is also compiled for 64bit on OS X. 4781:59a75bd0ddf4 Sat Jul 28 19:49:00 EDT 2007 Nathan Binkert <nate@binkert.org> style: Check/Fix whitespace on SCons files 4504:936dfda07b50 Thu May 31 18:01:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> This is probably a more scons like way to do this 4500:068356f4fa81 Thu May 31 16:45:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> obey the m5 style 4496:7fe59ed05a61 Thu May 31 15:33:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> check that m4 is available before trying to use it 4494:b7c909b5a5e9 Wed May 30 17:08:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Fix compiling on Solaris since Nate's libelf change SConstruct: export env after we've set CC/CXX ext/libelf/SConscript: pull in the CC/CXX variables from env. Use gm4 if it exists ext/libelf/elf_begin.c: ext/libelf/libelf_allocate.c: include errno.h instead of sys/errno.h ext/libelf/elf_common.h: use the more standard uintX_t ext/libelf/elf_strptr.c: ext/libelf/elf_update.c: include sysmacros.h on Solaris for roundup() 4487:a174ee67da68 Mon May 28 18:39:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Fix M4 command line... wasn't working on zizzer. A little more concise now. 4484:7c56a6c9c265 Sat May 26 21:15:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Get rid of GNU libelf and its autoconf nastiness and replace it with FreeBSD's implementation |
/gem5/src/arch/alpha/ | ||
H A D | AlphaTLB.py | 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. 4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. |
H A D | SConsopts | 4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. |
/gem5/src/arch/sparc/ | ||
H A D | SparcTLB.py | 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. 4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. |
H A D | interrupts.hh | 4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg 4103:785279436bdd Sat Mar 03 17:22:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Implement Niagara I/O interface and rework interrupts configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore 4028:e936c7dc2d68 Tue Feb 06 18:47:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> merge my index fix and lisa's fix 4009:1c590619ae6b Fri Feb 02 18:05:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make interrupt code serialize itself and fix indenting 3948:bd29868997f4 Thu Feb 01 15:34:00 EST 2007 Lisa Hsu <hsul@eecs.umich.edu> only increment numPosted if an interrupt of that type hasn't been posted before. 3921:0aa584f53a9b Fri Jan 19 21:33:00 EST 2007 Lisa Hsu <hsul@eecs.umich.edu> some hstick and hintp changes. src/arch/sparc/interrupts.hh: condition hstick matches on HINTP src/arch/sparc/miscregfile.cc: implement HINTP src/arch/sparc/ua2005.cc: don't post interrupt unless it is enabled. 3896:182be4779097 Thu Jan 11 09:18:00 EST 2007 Lisa Hsu <hsul@eecs.umich.edu> Add Trap Level Zero to interrupts, remove some unreachable code that I forgot to remove last time. 3894:60a7b0a3602f Mon Jan 08 18:18:00 EST 2007 Lisa Hsu <hsul@eecs.umich.edu> the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in. src/arch/sparc/interrupts.hh: fill in how we do interrupts on sparc a little bit. 1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU. 2) fill in getInterrupts() a little bit. also, update the bitfield access to be HPSTATE::hpriv, etc. src/arch/sparc/ua2005.cc: 1) update formatting 2) change the way interrupts are done to use the new way to tickle the CPU. src/cpu/base.cc: src/cpu/base.hh: overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value. |
H A D | sparc_traits.hh | 4641:7bfba41846c2 Sun Apr 22 13:43:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the GSR into a renamed control register. It should be split into a renamed part and a control part for the different bitfields, but the renamed part is all that's actually used. |
/gem5/src/mem/ | ||
H A D | MemObject.py | 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. 4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. |
/gem5/src/arch/sparc/isa/formats/mem/ | ||
H A D | blockmem.isa | 5096:eb06635e06ac Tue Sep 25 23:11:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Remove parameter that was only ever set to one value. 4653:19f884e6a48b Tue Jun 19 21:54:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem into doughnut.hpl.hp.com:/home/gblack/newmem-o3-micro src/cpu/base_dyn_inst_impl.hh: src/cpu/o3/fetch_impl.hh: Hand merge 4648:173a212f5091 Tue May 08 09:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a hack to truncate addresses to 32 bits in SE. Paging should be changed to use the architecture's TLB, at which point this can be removed. 4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent. src/arch/x86/isa/macroop.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code. src/arch/x86/isa/microops/base.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation. 4362:95e5f28ce484 Tue Apr 10 20:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Create a filter and a union to translate the SPARC instruction implementations from using doubles to using concatenated singles. 4040:eb894f3fc168 Mon Feb 12 13:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> rename store conditional stuff as extra data so it can be used for conditional swaps as well Add support for a twin 64 bit int load Add Memory barrier and write barrier flags as appropriate Make atomic memory ops atomic src/arch/alpha/isa/mem.isa: src/arch/alpha/locked_mem.hh: src/cpu/base_dyn_inst.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: rename store conditional stuff as extra data so it can be used for conditional swaps as well src/arch/alpha/types.hh: src/arch/mips/types.hh: src/arch/sparc/types.hh: add a largest read data type for statically allocating read buffers in atomic simple cpu src/arch/isa_parser.py: Add support for a twin 64 bit int load src/arch/sparc/isa/decoder.isa: Make atomic memory ops atomic Add Memory barrier and write barrier flags as appropriate src/arch/sparc/isa/formats/mem/basicmem.isa: add post access code block and define a twinload format for twin loads src/arch/sparc/isa/formats/mem/blockmem.isa: remove old microcoded twin load coad src/arch/sparc/isa/formats/mem/mem.isa: swap.isa replaces the code in loadstore.isa src/arch/sparc/isa/formats/mem/util.isa: add a post access code block src/arch/sparc/isa/includes.isa: need bigint.hh for Twin64_t src/arch/sparc/isa/operands.isa: add a twin 64 int type src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: add support for twinloads add support for swap and conditional swap instructions rename store conditional stuff as extra data so it can be used for conditional swaps as well src/mem/packet.cc: src/mem/packet.hh: Add support for atomic swap memory commands src/mem/packet_access.hh: Add endian conversion function for Twin64_t type src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: Add support for atomic swap memory commands Rename sc code to extradata 3980:9bcb2a2e9bb8 Sat Jan 27 01:59:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/isa_traits.hh: src/arch/sparc/system.cc: Hand Merge 3972:2c65c89843c5 Tue Jan 23 01:31:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem into ewok.(none):/home/gblack/m5/newmemo3 src/sim/byteswap.hh: Hand Merge 3970:d54945bab95d Wed Jan 03 00:52:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem 3929:3640569369a5 Thu Jan 25 13:43:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back src/arch/sparc/isa/decoder.isa: fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/formats/mem/blockmem.isa: Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/includes.isa: Use limits for 32bit underflow/overflow detection src/arch/sparc/tlb.cc: only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync src/arch/sparc/tlb_map.hh: add a print function to dump the tlb lookup table src/cpu/simple/base.cc: if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back |
/gem5/util/ | ||
H A D | style.py | 5309:4d3a6e086488 Tue Dec 11 13:41:00 EST 2007 Steve Reinhardt <stever@gmail.com> Fix minor bug in util/style.py 4984:1cbcac3f8144 Tue Aug 21 19:15:00 EDT 2007 Nathan Binkert <nate@binkert.org> style: fix style hook when run from a repo subdir. Before this fix, the style hook would blow up when you did a qrefresh to add a new file, but executed the qrefresh from a repository sub directory. 4980:b386c80ceb05 Tue Aug 14 21:21:00 EDT 2007 Nathan Binkert <nate@binkert.org> style: Don't try to fix files that should be ignored. The style hook was ignoring new files, but processing all modified files. 4794:88afe390fc0f Sun Jul 29 04:38:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge with head. style.py was also missing an argument in one call to modified_lines. 4784:e8b1f87b3a85 Sun Jul 29 00:56:00 EDT 2007 Nathan Binkert <nate@binkert.org> Work around a mercurial bug in bdiff.blocks 4782:50a634ae064a Sat Jul 28 19:55:00 EDT 2007 Nathan Binkert <nate@binkert.org> style: fix stupid bugs 4781:59a75bd0ddf4 Sat Jul 28 19:49:00 EDT 2007 Nathan Binkert <nate@binkert.org> style: Check/Fix whitespace on SCons files 4761:4bb357497886 Mon Jul 23 23:55:00 EDT 2007 Nathan Binkert <nate@binkert.org> Allow the fixwhite stuff to work when committing from a subdir 4745:33b409225928 Sun Jul 22 16:45:00 EDT 2007 Nathan Binkert <nate@binkert.org> do proper style checks for merged files 4744:4a08d0c0f929 Sun Jul 22 12:08:00 EDT 2007 Nathan Binkert <nate@binkert.org> fix the style fixing thing |
/gem5/src/arch/x86/isa/decoder/ | ||
H A D | two_byte_opcodes.isa | 5296:5caa774215cd Sun Dec 02 02:06:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement mov from control register. 5292:a26311673ef0 Sun Dec 02 02:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the LIDT instruction. 5291:5d38610cff05 Sun Dec 02 02:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the lgdt instruction. 5241:a6602acdd046 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the wrcr microop which writes a control register, and some control register work. 5240:6dc723c9c6a9 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement some bit testing instructions. 5238:95f494fd38bd Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Flesh out the opcode groups for two byte opcodes. 5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions. There are no priviledge checks, so these instructions will all work in all modes. 5059:33478a26f73e Thu Sep 06 19:18:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add a square root microop and the SSE sqrt instruction. 5058:be23162b7370 Thu Sep 06 19:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add SSE comparison instructions and microops and move some FP microops to be with the other ones. 5052:791ae1b04d72 Wed Sep 05 02:44:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement an SSE xor microop and instruction. |
/gem5/src/cpu/o3/ | ||
H A D | SConsopts | 4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. |
/gem5/src/cpu/simple/ | ||
H A D | SConsopts | 4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. |
/gem5/src/dev/ | ||
H A D | baddev.hh | 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. |
/gem5/src/sim/ | ||
H A D | InstTracer.py | 4776:8c8407243a2c Sat Jul 28 23:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. |
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/ | ||
H A D | bit_scan.py | 5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode. |
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/ | ||
H A D | horizontal_addition.py | 5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode. |
/gem5/src/arch/x86/isa/insts/simd128/integer/data_reordering/ | ||
H A D | unpack_and_interleave.py | 5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode. |
/gem5/src/arch/x86/isa/insts/simd128/integer/data_transfer/ | ||
H A D | move.py | 5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode. |
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