Searched hist:2007 (Results 226 - 250 of 895) sorted by relevance

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/gem5/src/arch/x86/insts/
H A Dmicroregop.cc5144:61cadaae546a Tue Oct 09 20:20:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Get rid of stray Sparc DPRINTF
5083:49559a8060e8 Wed Sep 19 21:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move the fp microops to their own file with their own base classes in C++ and python.
5077:4c25f95fa600 Thu Sep 13 19:35:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix how ECF is computed in genFlags, and get rid of some duplicate code.
4954:17d8fe61258e Tue Aug 07 18:26:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Added some missing parenthesis in the condition code calculation function.
4953:1181cf10e11e Tue Aug 07 18:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implemented and hooked in SCAS (scan string)
Fixed the asz assembler symbol.
Adjusted the condion checks to have appropriate options.
Implemented the SCAS microcode.
Attached SCAS into the decoder.
4804:4a707cb7065b Mon Jul 30 16:23:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make disassembly use the final register index. Add bits to indicate whether or not register indexes should be "folded".
4713:c208cec7b5b3 Fri Jul 20 17:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fixed width parameter and provided a parameter to flip the carry bit on subtract.
4693:ca44a1014212 Tue Jul 17 21:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make disassembled x86 register indices reflect their size.
This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly.
4688:82d7cbf0e66d Tue Jul 17 18:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add in support for condition code flags.
Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented.
4679:0b39fa8f5eb8 Sat Jul 14 20:14:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Pull some hard coded base classes out of the isa description.
H A Dmicroregop.hh5083:49559a8060e8 Wed Sep 19 21:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move the fp microops to their own file with their own base classes in C++ and python.
4953:1181cf10e11e Tue Aug 07 18:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implemented and hooked in SCAS (scan string)
Fixed the asz assembler symbol.
Adjusted the condion checks to have appropriate options.
Implemented the SCAS microcode.
Attached SCAS into the decoder.
4804:4a707cb7065b Mon Jul 30 16:23:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make disassembly use the final register index. Add bits to indicate whether or not register indexes should be "folded".
4713:c208cec7b5b3 Fri Jul 20 17:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fixed width parameter and provided a parameter to flip the carry bit on subtract.
4688:82d7cbf0e66d Tue Jul 17 18:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add in support for condition code flags.
Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented.
4679:0b39fa8f5eb8 Sat Jul 14 20:14:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Pull some hard coded base classes out of the isa description.
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/
H A Dxreturn.py5295:5268691561b4 Sun Dec 02 02:05:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: First crack at far returns. This is grossly approximate.
5119:a4469f2919f3 Wed Oct 03 01:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/general_purpose/input_output/
H A Dgeneral_io.py5239:0920dfb94514 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.
5161:e7334f2d7bef Fri Oct 19 01:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the in/out instructions. These will still need support from the TLB and memory system.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dstring_io.py5239:0920dfb94514 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.
5167:3668fc87f144 Fri Oct 19 01:42:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the string IO instructions, ins and outs.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/
H A Dvtophys.hh5124:3d8c50376609 Wed Oct 03 02:00:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging.
4162:baef0678866b Mon Mar 05 12:59:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Fill out a stub version of the vtophys header file.
4120:3e09b5d32c45 Sat Mar 03 11:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add build hooks for x86.
/gem5/src/arch/x86/isa/microops/
H A Dbase.isa5083:49559a8060e8 Wed Sep 19 21:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move the fp microops to their own file with their own base classes in C++ and python.
5040:126e4510b5bb Sat Sep 01 01:28:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Major rework of how regop microops are generated.
The new implementation uses metaclass, and gives a lot more precise control
with a lot less verbosity. The flags/no flags reg/imm variants are all handled
by the same python class now which supplies a constructor to the right C++
class based on context.
4679:0b39fa8f5eb8 Sat Jul 14 20:14:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Pull some hard coded base classes out of the isa description.
4561:ade4960f0832 Wed Jun 13 14:05:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Move load/store microops into their own file. They still don't do anything, though.
4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent.

src/arch/x86/isa/macroop.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.
4534:7035ff1aa521 Fri Jun 08 13:16:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix the formatting on a comment.
4524:f051dcff22b3 Mon Jun 04 15:53:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make limm (load immediate) microop
4519:f8da6b45573f Mon Jun 04 11:59:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Reworking x86's microcode system. This is a work in progress, and X86 doesn't compile.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/macroop.isa:
src/arch/x86/isa/main.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/base.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/regop.isa:
src/arch/x86/isa/microops/specop.isa:
Reworking x86's microcode system
4371:c5003760793e Tue Apr 10 13:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Reworked x86 a bit
4344:174e31456abe Fri Apr 06 12:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Consolidated the microcode assembler to help separate it from more x86-centric stuff.
/gem5/src/arch/sparc/
H A DSConsopts4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/
H A Dascii_adjust.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dbcd_adjust.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dextract_sign_mask.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/general_purpose/flags/
H A Dset_and_clear.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/general_purpose/
H A Dload_segment_registers.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/general_purpose/string/
H A Dcompare_strings.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/
H A Dsimultaneous_addition_and_subtraction.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/compare/
H A Dcompare_and_write_mask.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/
H A Dconvert_floating_point_to_floating_point.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/
H A Dunpack_and_interleave.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/logical/
H A Dandp.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/integer/arithmetic/
H A Daddition.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dmultiply_add.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dsubtraction.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/integer/data_reordering/
H A Dpack_with_saturation.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/integer/logical/
H A Dpand.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/
H A Dsave_and_restore_control_and_status.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.

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