Searched hist:13634 (Results 1 - 10 of 10) sorted by relevance
/gem5/src/arch/riscv/linux/ | ||
H A D | linux.cc | 13634:748418e0ca3f Wed Dec 26 20:19:00 EST 2018 Austin Harris <austinharris@utexas.edu> arch-riscv: Enable support for riscv 32-bit in SE mode. This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
H A D | process.hh | 13634:748418e0ca3f Wed Dec 26 20:19:00 EST 2018 Austin Harris <austinharris@utexas.edu> arch-riscv: Enable support for riscv 32-bit in SE mode. This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
H A D | linux.hh | 13634:748418e0ca3f Wed Dec 26 20:19:00 EST 2018 Austin Harris <austinharris@utexas.edu> arch-riscv: Enable support for riscv 32-bit in SE mode. This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
H A D | process.cc | 13634:748418e0ca3f Wed Dec 26 20:19:00 EST 2018 Austin Harris <austinharris@utexas.edu> arch-riscv: Enable support for riscv 32-bit in SE mode. This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
/gem5/src/arch/riscv/ | ||
H A D | types.hh | 13634:748418e0ca3f Wed Dec 26 20:19:00 EST 2018 Austin Harris <austinharris@utexas.edu> arch-riscv: Enable support for riscv 32-bit in SE mode. This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
H A D | process.hh | 13634:748418e0ca3f Wed Dec 26 20:19:00 EST 2018 Austin Harris <austinharris@utexas.edu> arch-riscv: Enable support for riscv 32-bit in SE mode. This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
H A D | process.cc | 13634:748418e0ca3f Wed Dec 26 20:19:00 EST 2018 Austin Harris <austinharris@utexas.edu> arch-riscv: Enable support for riscv 32-bit in SE mode. This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
/gem5/src/base/loader/ | ||
H A D | object_file.hh | 13634:748418e0ca3f Wed Dec 26 20:19:00 EST 2018 Austin Harris <austinharris@utexas.edu> arch-riscv: Enable support for riscv 32-bit in SE mode. This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
H A D | elf_object.cc | 13634:748418e0ca3f Wed Dec 26 20:19:00 EST 2018 Austin Harris <austinharris@utexas.edu> arch-riscv: Enable support for riscv 32-bit in SE mode. This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
/gem5/src/sim/ | ||
H A D | process.cc | 13634:748418e0ca3f Wed Dec 26 20:19:00 EST 2018 Austin Harris <austinharris@utexas.edu> arch-riscv: Enable support for riscv 32-bit in SE mode. This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
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