arch-riscv: initialize RISC-V's thread pointer register in clone syscall

This patch initializes thread pointer register to Thread Local Storage
(TLS)'s pointer given to a clone system call.

Change-Id: I03e2cf4763e6a0ed31f357772a513a05e1e3461b
Reviewed-on: https://gem5-review.googlesource.com/c/9622
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

arch-riscv: Enable support for riscv 32-bit in SE mode.

This patch splits up the riscv SE mode support for 32 and 64-bit.
A future patch will add support for decoding rv32 instructions.

Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/15355
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

sim-se: Refactor clone to avoid most ifdefs

Some parts of clone are architecture dependent. In some cases, we are
able to use architecture-specific helper functions or register
aliases. However, there is still some architecture-specific that is
protected by ifdefs in the common clone implementation.

Move these architecture-specific bits to the architecture-specific OS
class instead to avoid these ifdefs and make the code a bit more
readable.

Change-Id: Ia0903d738d0ba890863bddfa77e3b717db7f45de
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15435
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

arch-riscv: Add missing system calls

This patch adds all system calls present in riscv-gnu-toolchain at
commit hash 65cb174. Many of them do not have implementations in gem5, so
they are just placeholders.

[Remove the variadic macro and replace it with a function that has
default arguments because variadic macros may not be portable across
compilers]
[Remove spaces around default arguments of createSyscall for better
style]
[Switch from using a loose function to using SyscallDesc's new
constructor]

Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9
Reviewed-on: https://gem5-review.googlesource.com/5322
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

riscv: [Patch 6/5] Improve Linux emulation for RISC-V

This is an add-on patch for the original series that implemented RISC-V
that improves the implementation of Linux emulation for SE mode. Basically
it cleans up linux/linux.hh by removing constants that haven't been
defined for the RISC-V Linux proxy kernel and rearranging the stat
struct so it aligns with RISC-V's implementation of it. It also adds
placeholders for system calls that have been given numbers in RISC-V
but haven't been given implementations yet. These system calls are
as follows:
- readlinkat
- sigprocmask
- ioctl
- clock_gettime
- getrusage
- getrlimit
- setrlimit

The first five patches implemented RISC-V with the base ISA and multiply,
floating point, and atomic extensions and added support for detailed
CPU models with memory timing.

[Fixed incompatibility with changes made from patch 1.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>