Searched hist:13 (Results 526 - 550 of 1864) sorted by relevance
/gem5/src/systemc/tests/systemc/kernel/dynamic_processes/sc_join/test02/ | ||
H A D | test02.cpp | 13158:886ca37b7665 Tue Sep 04 21:13:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Make some tests use cout instead of cerr to report completion. cerr goes to simerr, but we compare simout against the golden output. Change-Id: I9270866a92dd06a23d47c1964dacc4872030f30d Reviewed-on: https://gem5-review.googlesource.com/c/12470 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/systemc/tests/systemc/kernel/dynamic_processes/sc_join/test04/ | ||
H A D | test04.cpp | 13158:886ca37b7665 Tue Sep 04 21:13:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Make some tests use cout instead of cerr to report completion. cerr goes to simerr, but we compare simout against the golden output. Change-Id: I9270866a92dd06a23d47c1964dacc4872030f30d Reviewed-on: https://gem5-review.googlesource.com/c/12470 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/systemc/tests/systemc/kernel/dynamic_processes/sc_join/test05/ | ||
H A D | test05.cpp | 13158:886ca37b7665 Tue Sep 04 21:13:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Make some tests use cout instead of cerr to report completion. cerr goes to simerr, but we compare simout against the golden output. Change-Id: I9270866a92dd06a23d47c1964dacc4872030f30d Reviewed-on: https://gem5-review.googlesource.com/c/12470 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/systemc/tests/systemc/kernel/phase_callbacks/test04/ | ||
H A D | register_phase_callbacks.cpp | 12876:e332bbd21d47 Wed Jun 13 21:41:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Remove references to internal constants from the tests. The tests were referring to constants defined in the Accellera systemc implementation which identified various log message types. This change replaces those (sometimes quite long) string constants with their actual value. This doesn't make that interface any more fragile since the constant value won't track between the Accellera version and this one, but it does make its fragility more explicit by using the value directly. If in the future we decide to hide the magical nature of those particular string constants, we could make them into our own constants in the implementation. Regardless, the tests shouldn't refer to internal details of the implementation. Change-Id: I116a7407fcac49367649b250683117f3ccf4f9ed Reviewed-on: https://gem5-review.googlesource.com/11181 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/systemc/tests/systemc/kernel/process_control/reset/method_reset_throw/ | ||
H A D | sc_method_reset_throw.cpp | 12876:e332bbd21d47 Wed Jun 13 21:41:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Remove references to internal constants from the tests. The tests were referring to constants defined in the Accellera systemc implementation which identified various log message types. This change replaces those (sometimes quite long) string constants with their actual value. This doesn't make that interface any more fragile since the constant value won't track between the Accellera version and this one, but it does make its fragility more explicit by using the value directly. If in the future we decide to hide the magical nature of those particular string constants, we could make them into our own constants in the implementation. Regardless, the tests shouldn't refer to internal details of the implementation. Change-Id: I116a7407fcac49367649b250683117f3ccf4f9ed Reviewed-on: https://gem5-review.googlesource.com/11181 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/systemc/tests/systemc/kernel/sc_time/test19/ | ||
H A D | test19.cpp | 12876:e332bbd21d47 Wed Jun 13 21:41:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Remove references to internal constants from the tests. The tests were referring to constants defined in the Accellera systemc implementation which identified various log message types. This change replaces those (sometimes quite long) string constants with their actual value. This doesn't make that interface any more fragile since the constant value won't track between the Accellera version and this one, but it does make its fragility more explicit by using the value directly. If in the future we decide to hide the magical nature of those particular string constants, we could make them into our own constants in the implementation. Regardless, the tests shouldn't refer to internal details of the implementation. Change-Id: I116a7407fcac49367649b250683117f3ccf4f9ed Reviewed-on: https://gem5-review.googlesource.com/11181 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/arch/power/insts/ | ||
H A D | integer.hh | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
H A D | floating.hh | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
/gem5/src/arch/null/ | ||
H A D | isa_traits.hh | 9850:87d6b41749e9 Wed Sep 04 13:22:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> arch: Resurrect the NOISA build target and rename it NULL This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. |
/gem5/src/cpu/testers/traffic_gen/ | ||
H A D | SConscript | 12813:2c023816bec9 Fri Apr 27 13:57:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Add a Python-enabled traffic generator The current traffic generator relies on a configuration file that describes a small machine to generate stimuli. This configuration file is usually generated by the gem5 Python configuration. This creates an unnecessary and fragile step. This changeset introduces a Python-based trace module. When instantiated, the module exposes a start method that takes an iterable object as a parameter (e.g., a generator). The iterable object is expected to represent a list of generators that will be run one after the other. For example: system.tgen = PyTrafficGen() m5.instantiate() def trace(): yield system.tgen.createIdle(1000) yield system.tgen.createExit(0) system.tgen.start(trace()) Change-Id: I58e60ca517e86c197859f4daaa67750066abdc1c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11518 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> 12810:485ca1c27812 Thu Apr 26 13:16:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Split the traffic generator into two classes The traffic generator currently assumes that it is always driven from a configuration file. Split it into a base class (BaseTrafficGen) that handles basic packet generation and a derived class that implements the config handling (TrafficGen). Change-Id: I9407f04c40ad7e40a263c8d1ef29d37ff8e6f1b4 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11515 9666:74aca4cb081e Mon Apr 22 13:20:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> cpu: Make the generators usable outside the TrafficGen module This patch enables the use of the generator behaviours outside the TrafficGen module. This is useful e.g. to allow packet replay modes for other devices in the system without having to replace them with a TrafficGen in the configuration files. This change also enables more specific behaviours to be composed as specific modules, e.g. BaseBandModem can use a number of generators and have application-specific parameters based around a specific set of generators. 9402:f6e3c60f04e5 Mon Jan 07 13:05:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> cpu: Add support for protobuf input for the trace generator This patch adds support for reading input traces encoded using protobuf according to what is done in the CommMonitor. A follow-up patch adds a Python script that can be used to convert the previously used ASCII traces to protobuf equivalents. The appropriate regression input is updated as part of this patch. |
H A D | pygen.cc | 12813:2c023816bec9 Fri Apr 27 13:57:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Add a Python-enabled traffic generator The current traffic generator relies on a configuration file that describes a small machine to generate stimuli. This configuration file is usually generated by the gem5 Python configuration. This creates an unnecessary and fragile step. This changeset introduces a Python-based trace module. When instantiated, the module exposes a start method that takes an iterable object as a parameter (e.g., a generator). The iterable object is expected to represent a list of generators that will be run one after the other. For example: system.tgen = PyTrafficGen() m5.instantiate() def trace(): yield system.tgen.createIdle(1000) yield system.tgen.createExit(0) system.tgen.start(trace()) Change-Id: I58e60ca517e86c197859f4daaa67750066abdc1c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11518 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
H A D | PyTrafficGen.py | 12813:2c023816bec9 Fri Apr 27 13:57:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Add a Python-enabled traffic generator The current traffic generator relies on a configuration file that describes a small machine to generate stimuli. This configuration file is usually generated by the gem5 Python configuration. This creates an unnecessary and fragile step. This changeset introduces a Python-based trace module. When instantiated, the module exposes a start method that takes an iterable object as a parameter (e.g., a generator). The iterable object is expected to represent a list of generators that will be run one after the other. For example: system.tgen = PyTrafficGen() m5.instantiate() def trace(): yield system.tgen.createIdle(1000) yield system.tgen.createExit(0) system.tgen.start(trace()) Change-Id: I58e60ca517e86c197859f4daaa67750066abdc1c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11518 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/mem/ | ||
H A D | drampower.cc | 11229:1b9331fd8966 Wed Nov 25 13:52:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Fix search-replace issues in DRAMPower wrapper license Fix a number of unintentional insertions of 'const'. |
/gem5/system/arm/dt/ | ||
H A D | armv8_big_little.dts | 12761:effd14bda656 Wed Jun 06 13:28:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> system-arm: Split the VExpress_GEM5_V1 base dts With the introduction of the new DPU model, we need different variations of the VExpress_GEM5_V1 platform. This splits the platform dtsi file into a separate file for the base platform and the HDLCD-based platform. This matches the hierarchy in RealView.py. Change-Id: Id02380122655b5d3aa3548a703fdef178bba17d9 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11035 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
/gem5/configs/network/ | ||
H A D | __init__.py | 11670:6ce719503eae Thu Oct 13 03:17:00 EDT 2016 Andreas Hansson <andreas.hansson@arm.com> ruby: Fix regressions and make Ruby configs Python packages This patch moves the addition of network options into the Ruby module to avoid the regressions all having to add it explicitly. Doing this exposes an issue in our current config system though, namely the fact that addtoPath is relative to the Python script being executed. Since both example and regression scripts use the Ruby module we would end up with two different (relative) paths being added. Instead we take a first step at turning the config modules into Python packages, simply by adding a __init__.py in the configs/ruby, configs/topologies and configs/network subdirectories. As a result, we can now add the top-level configs directory to the Python search path, and then use the package names in the various modules. The example scripts are also updated, and the messy path-deducing variations in the scripts are unified. |
/gem5/configs/topologies/ | ||
H A D | __init__.py | 11670:6ce719503eae Thu Oct 13 03:17:00 EDT 2016 Andreas Hansson <andreas.hansson@arm.com> ruby: Fix regressions and make Ruby configs Python packages This patch moves the addition of network options into the Ruby module to avoid the regressions all having to add it explicitly. Doing this exposes an issue in our current config system though, namely the fact that addtoPath is relative to the Python script being executed. Since both example and regression scripts use the Ruby module we would end up with two different (relative) paths being added. Instead we take a first step at turning the config modules into Python packages, simply by adding a __init__.py in the configs/ruby, configs/topologies and configs/network subdirectories. As a result, we can now add the top-level configs directory to the Python search path, and then use the package names in the various modules. The example scripts are also updated, and the messy path-deducing variations in the scripts are unified. |
/gem5/src/arch/alpha/linux/ | ||
H A D | linux.hh | 11383:5ac090acd180 Thu Mar 17 13:24:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: extend mmap system call to support file backed mmaps For O3, which has a stat that counts reg reads, there is an additional reg read per mmap() call since there's an arg we no longer ignore. Otherwise, stats should not be affected. 11382:654272b82e94 Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: add many Linux kernel flags 11381:516213d2f0cf Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: rename OpenFlagTransTable struct The structure definition only had the open system call flag set in mind when it was named, so we rename it here with the intention of using it to define additional tables to translate flags for other system calls in the future. 6689:67d980fcbc7a Sat Oct 24 13:53:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> syscall: Addition of an ioctl command code for Power. |
/gem5/src/arch/alpha/ | ||
H A D | isa.cc | 9425:a24092160ec7 Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@ARM.com> arch: Move the ISA object to a separate section After making the ISA an independent SimObject, it is serialized automatically by the Python world. Previously, this just resulted in an empty ISA section. This patch moves the contents of the ISA to that section and removes the explicit ISA serialization from the thread contexts, which makes it behave like a normal SimObject during serialization. Note: This patch breaks checkpoint backwards compatibility! Use the cpt_upgrader.py utility to upgrade old checkpoints to the new format. 9384:877293183bdf Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@arm.com> arch: Make the ISA class inherit from SimObject The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU. 7678:f19b6a3a8cec Mon Sep 13 22:26:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense. 6678:34191eea18c1 Sat Oct 17 04:13:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ISA: Fix compilation. |
/gem5/src/base/ | ||
H A D | refcnt.hh | 13590:d7e018859709 Mon Feb 13 04:41:00 EST 2017 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> cpu-o3: O3 LSQ Generalisation This patch does a large modification of the LSQ in the O3 model. The main goal of the patch is to remove the 'an operation can be served with one or two memory requests' assumption that is present in the LSQ and the instruction with the req, reqLow, reqHigh triplet, and generalising it to operations that can be addressed with one request, and operations that require many requests, embodied in the SingleDataRequest and the SplitDataRequest. This modification has been done mimicking the minor model to an extent, shifting the responsibilities of dealing with VtoP translation and tracking the status and resources from the DynInst to the LSQ via the LSQRequest. The LSQRequest models the information concerning the operation, handles the creation of fragments for translation and request as well as assembling/splitting the data accordingly. With this modifications, the implementation of vector ISAs, particularly on the memory side, become more rich, as the new model permits a dissociation of the ISA characteristics as vector length, from the microarchitectural characteristics that govern how contiguous loads are executing, allowing exploration of different LSQ to DL1 bus widths to understand the tradeoffs in complexity and performance. Part of the complexities introduced stem from the fact that gem5 keeps a large amount of metadata regarding, in particular, memory operations, thus, when an instruction is squashed while some operation as TLB lookup or cache access is ongoing, when the relevant structure communicates to the LSQ that the operation is over, it tries to access some pieces of data that should have died when the instruction is squashed, leading to asserts, panics, or memory corruption. To ensure the correct behaviour, the LSQRequest rely on assesing who is their owner, and self-destroying if they detect their owner is done with the request, and there will be no subsequent action. For example, in the case of an instruction squashed whal the TLB is doing a walk to serve the translation, when the translation is served by the TLB, the LSQRequest detects that the instruction was squashed, and as the translation is done, no one else expect to access its information, and therefore, it self-destructs. Having destroyed the LSQRequest earlier, would lead to wrong behaviour as the TLB walk may access some fields of it. Additional authors: - Gabor Dozsa <gabor.dozsa@arm.com> Change-Id: I9578a1a3f6b899c390cdd886856a24db68ff7d0c Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13516 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> 8221:8b5f900233ee Wed Apr 13 12:32:00 EDT 2011 Nathan Binkert <nate@binkert.org> refcnt: Update doxygen comments 8220:d9f19c39ddba Wed Apr 13 12:32:00 EDT 2011 Nathan Binkert <nate@binkert.org> refcnt: Inline comparison functions 3877:2432a50b7d25 Wed Dec 27 13:52:00 EST 2006 Nathan Binkert <binkertn@umich.edu> No need to use NULL, just use 0 The result of operator= cannot be an l-value |
/gem5/src/dev/arm/ | ||
H A D | FlashDevice.py | 10801:049eb85e8ea2 Thu Apr 23 13:37:00 EDT 2015 Rene de Jong <rene.dejong@arm.com> arm, dev: Add a NAND flash timing model This adds a NAND flash timing model. This model takes the number of planes into account and is ultimately intended to be used as a high-level performance model for any device using flash. To access the memory, use either readMemory or writeMemory. To make use of the model you will need an interface model such as UFSHostDevice, which is part of a separate patch. At the moment the flash device is part of the ARM device tree since the only use if the UFSHostDevice, and that in turn relies on the ARM GIC. |
H A D | UFSHostDevice.py | 10802:876341add7be Thu Apr 23 13:37:00 EDT 2015 Rene de Jong <rene.dejong@arm.com> arm, dev: Add a UFS device This patch introduces a UFS host controller and a UFS device. More information about the UFS standard can be found at the JEDEC site: http://www.jedec.org/standards-documents/results/jesd220 Note that the model does not implement the complete standard, and as such is not an actual implementation of UFS. The following SCSI commands are implemented: inquiry, read, read capacity, report LUNs, start/stop, test unit ready, verify, write, format unit, send diagnostic, synchronize cache, mode select, mode sense, request sense, unmap, write buffer and read buffer. This is sufficient for usage with Linux and Android. To interact with this model a kernel version 3.9 or above is needed. |
H A D | VirtIOMMIO.py | 12740:beed0805c651 Mon Nov 07 13:21:00 EST 2016 Andreas Sandberg <andreas.sandberg@arm.com> dev-arm: Add a MMIO transport interface for VirtIO The MMIO interface currently only supports a subset of version 0.9.5 of the VirtIO specification. It has the following known limitations: * The queue size hint (the QUEUE_NUM register) is ignored. * Queue alignment is assumed to be hard-coded to VirtQueue::ALIGN_SIZE (4096 bytes). * Only 4096 byte pages are currently supported. Change-Id: Ifd318f5e5bddab0b6a42d8c8af9ff2fbb477f98b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2326 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
/gem5/tests/configs/ | ||
H A D | arm_generic.py | 9665:6dbdeee787cc Mon Apr 22 13:20:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Add a mem-type config option to se/fs scripts This patch enables selection of the memory controller class through a mem-type command-line option. Behind the scenes, this option is treated much like the cpu-type, and a similar framework is used to resolve the valid options, and translate the short-hand description to a valid class. The regression scripts are updated with a hardcoded memory class for the moment. The best solution going forward is probably to get the memory out of the makeSystem functions, but Ruby complicates things as it does not connect the memory controller to the membus. 9649:c717bd5e0a1d Mon Apr 22 13:20:00 EDT 2013 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm: Enable support for triggering a sim panic on kernel panics Add the options 'panic_on_panic' and 'panic_on_oops' to the LinuxArmSystem SimObject. When these option are enabled, the simulator panics when the guest kernel panics or oopses. Enable panic on panic and panic on oops in ARM-based test cases. 9447:156f74caf0d4 Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@ARM.com> tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover. 9380:e428871da248 Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@ARM.com> tests: Create base classes to encapsulate common test configurations Most of the test cases currently contain a large amount of duplicated boiler plate code. This changeset introduces a set of classes that encapsulates most of the functionality when setting up a test configuration. The following base classes are introduced: * BaseSystem - Basic system configuration that can be used for both SE and FS simulation. * BaseFSSystem - Basic FS configuration uni-processor and multi-processor configurations. * BaseFSSystemUniprocessor - Basic FS configuration for uni-processor configurations. This is provided as a way to make existing test cases backwards compatible. Architecture specific implementations are provided for ARM, Alpha, and X86. |
/gem5/util/maint/ | ||
H A D | show_changes_by_file.py | 12893:3813d345cbac Mon Feb 05 13:15:00 EST 2018 Brandon Potter <brandon.potter@amd.com> util: add util/maint/show_changes_by_file.py tool The script diffs an upstream branch and a feature branch to find all files which have been changed between the branches. It then searches for all the corresponding changesets and binds them to the files in the output. The tool's output resembles the following: /path/to/file/ filename git-hash git-hash filename git-hash /path/to/file/ filename git-hash Change-Id: Icd67953748f38dad984488c5445313eaa56fa202 Reviewed-on: https://gem5-review.googlesource.com/7861 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
/gem5/src/arch/arm/tracers/ | ||
H A D | tarmac_record_v8.cc | 12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation This patch introduces the TarmacTracer: an instruction tracer which allows to dump a gem5 execution trace in Tarmac format [1]. The new tracer is supporting either Tarmac and TarmacV8 format specifications. Not every traceable information has been implemented: Implemented Trace Type: Instruction Trace Register Trace Processor Memory Access Trace Unimplemented Trace Type: Program Flow Trace Event Trace Memory Bus Trace [1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9382 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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