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| H A D | miscregs.cc | 12675:f3439303feb4 Tue Apr 17 06:08:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add ARMv8.1 TTBR1_EL2 register This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg table, but stil leaving it unimplemented (Accessing it through MSR/MRS causes an exception) Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10063 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | miscregs.hh | 12675:f3439303feb4 Tue Apr 17 06:08:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add ARMv8.1 TTBR1_EL2 register This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg table, but stil leaving it unimplemented (Accessing it through MSR/MRS causes an exception) Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10063 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | isa.cc | 12675:f3439303feb4 Tue Apr 17 06:08:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add ARMv8.1 TTBR1_EL2 register This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg table, but stil leaving it unimplemented (Accessing it through MSR/MRS causes an exception) Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10063 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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