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/gem5/src/arch/alpha/
H A Dinterrupts.cc5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
H A Dmicrocode_rom.hh5664:3b3756efad89 Sun Oct 12 18:59:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
H A DAlphaInterrupts.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
/gem5/src/arch/x86/isa/
H A Drom.isa5676:cca6726c0d88 Sun Oct 12 23:44:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement local labels for the ROM that actually refer into the ROM.
5667:78b94954f66a Sun Oct 12 20:52:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a handy way to access labels from the ROM in microcode.
5666:e7925fa8f0d6 Sun Oct 12 20:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make X86's microcode ROM actually do something.
/gem5/src/doxygen/images/
H A Dgem5_MS_Fig1.PNG9264:1607119c36bb Tue Sep 25 12:49:00 EDT 2012 Djordje Kovacevic <djordje.kovacevic@arm.com> MEM: Put memory system document into doxygen
H A Dgem5_MS_Fig2.PNG9264:1607119c36bb Tue Sep 25 12:49:00 EDT 2012 Djordje Kovacevic <djordje.kovacevic@arm.com> MEM: Put memory system document into doxygen
H A Dgem5_MS_Fig3.PNG9264:1607119c36bb Tue Sep 25 12:49:00 EDT 2012 Djordje Kovacevic <djordje.kovacevic@arm.com> MEM: Put memory system document into doxygen
H A Dgem5_MS_Fig4.PNG9264:1607119c36bb Tue Sep 25 12:49:00 EDT 2012 Djordje Kovacevic <djordje.kovacevic@arm.com> MEM: Put memory system document into doxygen
H A Dgem5_MS_Fig5.PNG9264:1607119c36bb Tue Sep 25 12:49:00 EDT 2012 Djordje Kovacevic <djordje.kovacevic@arm.com> MEM: Put memory system document into doxygen
H A Dgem5_MS_Fig6.PNG9264:1607119c36bb Tue Sep 25 12:49:00 EDT 2012 Djordje Kovacevic <djordje.kovacevic@arm.com> MEM: Put memory system document into doxygen
H A Dgem5_MS_Fig7.PNG9264:1607119c36bb Tue Sep 25 12:49:00 EDT 2012 Djordje Kovacevic <djordje.kovacevic@arm.com> MEM: Put memory system document into doxygen
H A Dgem5_MS_Fig8.PNG9264:1607119c36bb Tue Sep 25 12:49:00 EDT 2012 Djordje Kovacevic <djordje.kovacevic@arm.com> MEM: Put memory system document into doxygen
H A Dgem5_MS_Fig9.PNG9264:1607119c36bb Tue Sep 25 12:49:00 EDT 2012 Djordje Kovacevic <djordje.kovacevic@arm.com> MEM: Put memory system document into doxygen
/gem5/src/arch/mips/
H A Dmicrocode_rom.hh5664:3b3756efad89 Sun Oct 12 18:59:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
H A DMipsInterrupts.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
/gem5/src/cpu/o3/
H A Dderiv.hh9341:a0eff1e9c773 Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> cpu: O3 add a header declaring the DerivO3CPU

SWIG needs a complete declaration of all wrapped objects. This patch
adds a header file with the DerivO3CPU class and includes it in the
SWIG interface.
/gem5/tests/test-progs/hello/bin/power/linux/
H A DhelloP Hello world! /proc/sys/kernel/osrelease FATAL: kernel too old FATAL: cannot determine kernel version /dev/ ... 6692:a3c85a29b838 Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> test: Hello world test program for Power
includes reference outputs for the Hello World tests on simple-atomic
and o3-timing.
/gem5/util/cpt_upgraders/
H A Dsmt-interrupts.py11150:a8a64cca231b Wed Sep 30 12:14:00 EDT 2015 Mitch Hayenga <mitch.hayenga@arm.com> isa,cpu: Add support for FS SMT Interrupts

Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
H A Darm-sysreg-mapping-ns.py11768:5b80960dcf08 Mon Dec 19 12:03:00 EST 2016 Curtis Dunham <Curtis.Dunham@arm.com> arm: update AArch{64,32} register mappings

Change-Id: Idaaaeb3f7b1a0bdbf18d8e2d46686c78bb411317
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/mem/slicc/generate/
H A Dhtml.py7007:79413d1ec307 Fri Mar 12 21:42:00 EST 2010 Nathan Binkert <nate@binkert.org> slicc: Change the code generation so that the generated code is easier to read
6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
/gem5/src/arch/sparc/
H A Dinterrupts.cc5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
H A DSparcInterrupts.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
/gem5/src/cpu/testers/traffic_gen/
H A Dtrace_gen.cc12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/
H A Dbit_scan.py6344:b7104eda0795 Thu Jul 16 12:27:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix a number of places where the wrong form of a microop was used.
5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them.
5423:536fb3cc5a9b Thu Jun 12 00:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Redo BSF.
5415:5c28e3dbdc8e Thu Jun 12 00:46:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Fix the implementation of BSF.
5414:bed5152f6368 Thu Jun 12 00:45:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Bit scan forward/reverse were accidentally transposed.
/gem5/src/arch/x86/isa/insts/general_purpose/string/
H A Dload_string.py5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them.
5420:dc0041a51920 Thu Jun 12 00:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make string instructions work when rcx=0.
5150:4b5a97744185 Fri Oct 12 23:07:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implemented LODS.

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