Searched hist:12 (Results 876 - 900 of 2449) sorted by relevance

<<31323334353637383940>>

/gem5/src/arch/x86/insts/
H A Dmicrofpop.hh7620:3d8a23caa1ef Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Consolidate extra microop flags into one parameter.

This single parameter replaces the collection of bools that set up various
flavors of microops. A flag parameter also allows other flags to be set like
the serialize before/after flags, etc., without having to change the
constructor.
6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands.
/gem5/src/arch/x86/isa/microops/
H A Dbase.isa7620:3d8a23caa1ef Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Consolidate extra microop flags into one parameter.

This single parameter replaces the collection of bools that set up various
flavors of microops. A flag parameter also allows other flags to be set like
the serialize before/after flags, etc., without having to change the
constructor.
6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands.
5667:78b94954f66a Sun Oct 12 20:52:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a handy way to access labels from the ROM in microcode.
5666:e7925fa8f0d6 Sun Oct 12 20:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make X86's microcode ROM actually do something.
4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent.

src/arch/x86/isa/macroop.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.
4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent.

src/arch/x86/isa/macroop.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.
4344:174e31456abe Fri Apr 06 12:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Consolidated the microcode assembler to help separate it from more x86-centric stuff.
4343:3f11bcf873b3 Fri Apr 06 12:00:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Refactored the x86 isa description some more. There should be more seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere.
/gem5/tests/test-progs/insttest/src/riscv/
H A Drv64i.cpp12428:ddc6b7179c81 Sat Dec 02 00:58:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Make use of ImmOp's polymorphism

This patch makes use of ImmOp's polymorphism to remove unnecessary
casting from the implementations of arithmetic instructions with
immediate operands and to remove the CUIOp format by combining it with
the CIOp format (compressed arithmetic instructions with immediate
operands). Interestingly, RISC-V specifies that instructions with
unsigned immediate operands still need to sign-extend the immediates
from 12 (or 20) bits to 64 bits, so that is left alone.

Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16
Reviewed-on: https://gem5-review.googlesource.com/6401
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
11730:08ab68477ea0 Wed Nov 30 17:12:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 8/5] Added some regression tests to RISC-V

This patch is the eighth patch in a series adding RISC-V to gem5, and
third of the bonus patches to the original series of five. It adds some
regression tests to RISC-V.

Regression tests included:
- se/00.hello
- se/02.insttest (split into several binaries which are not included due
to large size)

The tests added to 00.insttest will need to be build manually; to
facilitate this, a Makefile is included. The required toolchain and
compiler (riscv64-unknown-elf-gcc) can be built from the riscv-tools
GitHub repository at https://github.com/riscv/riscv-tools.

Note that because EBREAK only makes sense when gdb is running or while in
FS mode, it is not included in the linux-rv64i insttest. ERET is not
included because it does not make sense in SE mode and, in fact, causes
a panic by design.

Note also that not every system call is tested in linux-rv64i; of the ones
defined in linux/process.hh, some have been given numbers but not
definitions for the toolchain, or are merely stubs that always return 0. Of
the ones that do work properly, only a subset are tested due to similar
functionality.

Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/arch/power/insts/
H A Dmem.hh12385:288c62455dde Wed Dec 13 02:12:00 EST 2017 Gabe Black <gabeblack@google.com> cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.

Neither of these were used, particularly memAccInst.

Change-Id: I4ac9e44cf624e5de42519d586d7b699f08a2cdfc
Reviewed-on: https://gem5-review.googlesource.com/6601
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/cpu/testers/traffic_gen/
H A Ddram_gen.cc12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dbase_gen.hh12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
H A Ddram_rot_gen.hh12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
H A Ddram_gen.hh12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dlinear_gen.hh12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
H A Drandom_gen.hh12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
H A Didle_gen.hh12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/arch/power/
H A DPowerTLB.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/tests/
H A Dmain.py13540:da30e62884ee Thu Jan 10 10:12:00 EST 2019 Andrea Mondelli <andrea.mondelli@ucf.edu> misc: updated shabang for python script

The default python on MacOS doesn’t have an alias to python2.
The official python version supported in gem5 is Python2.7.

This patch updates the shabang according to the version required in gem5.

Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0
Reviewed-on: https://gem5-review.googlesource.com/c/15375
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
12882:dd87d7f2f3e5 Thu Aug 03 12:28:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests,ext: Add a new testing library proposal

The new test library is split into two parts: The framework which resides
in ext/, and the gem5 helping components in /tests/gem5.

Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/4421
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
/gem5/util/
H A Dgen_arm_fs_files.py13540:da30e62884ee Thu Jan 10 10:12:00 EST 2019 Andrea Mondelli <andrea.mondelli@ucf.edu> misc: updated shabang for python script

The default python on MacOS doesn’t have an alias to python2.
The official python version supported in gem5 is Python2.7.

This patch updates the shabang according to the version required in gem5.

Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0
Reviewed-on: https://gem5-review.googlesource.com/c/15375
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
12643:359e0eff17a3 Tue Mar 27 12:05:00 EDT 2018 Pau Cabre <pau.cabre@metempsy.com> util,arch-arm: Update gen_arm_fs_files.py to use new kernel repos

Now it is using the kernels on https://gem5.googlesource.com/arm

Change-Id: I765f2b8ee48cfd7175e5b17a65db3bf612570c68
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/9481
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/mem/
H A DAddrMapper.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
9259:fc28f3ca5b21 Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a gasket that allows memory ranges to be re-mapped.

For example if DRAM is at two locations and mirrored this patch allows the
mirroring to occur.
/gem5/src/arch/x86/
H A Dx86_traits.hh9010:7891b96e1526 Tue May 22 12:29:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> X86: Split Condition Code register
This patch moves the ECF and EZF bits to individual registers (ecfBit and
ezfBit) and the CF and OF bits to cfofFlag registers. This is being done
so as to lower the read after write dependencies on the the condition code
register. Ultimately we will have the following registers [ZAPS], [OF],
[CF], [ECF], [EZF] and [DF]. Note that this is only one part of the
solution for lowering the dependencies. The other part will check whether
or not the condition code register needs to be actually read. This would
be done through a separate patch.
5658:55f9947891fb Sun Oct 12 17:01:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Fix the ordering of special physical address ranges.
5651:7f0c8006c3d7 Sun Oct 12 16:28:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make APICs communicate through the memory system.
5648:e8abda6e0980 Sun Oct 12 14:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the local APIC accessible through the memory system directly, and make the timer work.
5323:75f7e6366a41 Sat Jan 12 06:39:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the IO ports work using extra physical address lines. Add a serial port.
5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.
/gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/
H A Dconfig.ini11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/
H A Dconfig.ini11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/
H A Dstats.txt11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/
H A Dsimout11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes.
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/
H A Dconfig.ini11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/
H A Dconfig.ini11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing/
H A Dconfig.ini11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
9013:afa278317136 Tue May 22 12:38:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> X86 Regression: update stats due to cc register split
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/00.hello/ref/x86/linux/o3-timing/
H A Dsimout11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
9013:afa278317136 Tue May 22 12:38:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> X86 Regression: update stats due to cc register split
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/
H A Dconfig.ini11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes

Completed in 105 milliseconds

<<31323334353637383940>>