xref: /gem5/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000041                       # Number of seconds simulated
sim_ticks                                    41083000                       # Number of ticks simulated
final_tick                                   41083000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 202272                       # Simulator instruction rate (inst/s)
host_op_rate                                   202193                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1294825774                       # Simulator tick rate (ticks/s)
host_mem_usage                                 252636                       # Number of bytes of host memory used
host_seconds                                     0.03                       # Real time elapsed on the host
sim_insts                                        6413                       # Number of instructions simulated
sim_ops                                          6413                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             23232                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data             10816                       # Number of bytes read from this memory
system.physmem.bytes_read::total                34048                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        23232                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           23232                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                363                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                169                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   532                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            565489375                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            263271913                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               828761288                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       565489375                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          565489375                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           565489375                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           263271913                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              828761288                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           532                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         532                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    34048                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     34048                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  73                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  39                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  36                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  54                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  45                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  21                       # Per bank write bursts
system.physmem.perBankRdBursts::6                   1                       # Per bank write bursts
system.physmem.perBankRdBursts::7                   5                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::9                   1                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 21                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 29                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 19                       # Per bank write bursts
system.physmem.perBankRdBursts::13                127                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 47                       # Per bank write bursts
system.physmem.perBankRdBursts::15                 14                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        40972000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     532                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       443                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                        85                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples           91                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      363.604396                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     235.588514                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     321.826485                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             22     24.18%     24.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           22     24.18%     48.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           13     14.29%     62.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            8      8.79%     71.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            5      5.49%     76.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            4      4.40%     81.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            3      3.30%     84.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            8      8.79%     93.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            6      6.59%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             91                       # Bytes accessed per row activation
system.physmem.totQLat                        6584250                       # Total ticks spent queuing
system.physmem.totMemAccLat                  16559250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      2660000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12376.41                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31126.41                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         828.76                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      828.76                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           6.47                       # Data bus utilization in percentage
system.physmem.busUtilRead                       6.47                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        436                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.95                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        77015.04                       # Average gap between requests
system.physmem.pageHitRate                      81.95                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     264180                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     136620                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   1956360                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3073200.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy                3932430                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                  68640                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy          13617300                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy            928800                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy                 23977530                       # Total energy per rank (pJ)
system.physmem_0.averagePower              583.625643                       # Core power per rank (mW)
system.physmem_0.totalIdleTime               32009500                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE          39500                       # Time in different power states
system.physmem_0.memoryStateTime::REF         1300000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN      2418500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT         7463000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN     29862000                       # Time in different power states
system.physmem_1.actEnergy                     421260                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     208725                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   1842120                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3073200.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy                4023060                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                 174720                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy          14292180                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy            178080                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy                 24213345                       # Total energy per rank (pJ)
system.physmem_1.averagePower              589.365503                       # Core power per rank (mW)
system.physmem_1.totalIdleTime               31744250                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE         288500                       # Time in different power states
system.physmem_1.memoryStateTime::REF         1300000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN       464250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT         7679500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN     31350750                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                    2002                       # Number of BP lookups
system.cpu.branchPred.condPredicted              1237                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               378                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 1602                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     377                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             23.533084                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     234                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 14                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups             333                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits                 14                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses              319                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted          114                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                         1365                       # DTB read hits
system.cpu.dtb.read_misses                         11                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                     1376                       # DTB read accesses
system.cpu.dtb.write_hits                         884                       # DTB write hits
system.cpu.dtb.write_misses                         3                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                     887                       # DTB write accesses
system.cpu.dtb.data_hits                         2249                       # DTB hits
system.cpu.dtb.data_misses                         14                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                     2263                       # DTB accesses
system.cpu.itb.fetch_hits                        2685                       # ITB hits
system.cpu.itb.fetch_misses                        17                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                    2702                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.numSyscalls                    17                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON        41083000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                            82166                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                        6413                       # Number of instructions committed
system.cpu.committedOps                          6413                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                          1093                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                              12.812412                       # CPI: cycles per instruction
system.cpu.ipc                               0.078049                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                  19      0.30%      0.30% # Class of committed instruction
system.cpu.op_class_0::IntAlu                    4331     67.53%     67.83% # Class of committed instruction
system.cpu.op_class_0::IntMult                      1      0.02%     67.85% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     2      0.03%     67.88% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc                 0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::FloatMisc                    0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.88% # Class of committed instruction
system.cpu.op_class_0::MemRead                   1191     18.57%     86.45% # Class of committed instruction
system.cpu.op_class_0::MemWrite                   861     13.43%     99.88% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead                 1      0.02%     99.89% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite                7      0.11%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                     6413                       # Class of committed instruction
system.cpu.tickCycles                           12637                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                           69529                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse           103.987673                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                1990                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.775148                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   103.987673                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.025388                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.025388                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          151                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.041260                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              4591                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             4591                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data         1250                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1250                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          740                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            740                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          1990                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             1990                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         1990                       # number of overall hits
system.cpu.dcache.overall_hits::total            1990                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           96                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            96                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          125                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          221                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            221                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          221                       # number of overall misses
system.cpu.dcache.overall_misses::total           221                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      8545500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      8545500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     10428500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     10428500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     18974000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     18974000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     18974000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     18974000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1346                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1346                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2211                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2211                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2211                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2211                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.071322                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.071322                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.144509                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.144509                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.099955                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.099955                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.099955                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.099955                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        83428                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total        83428                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 85855.203620                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 85855.203620                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 85855.203620                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 85855.203620                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.WriteReq_mshr_hits::cpu.data           52                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data           52                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total           52                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data           52                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total           52                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           96                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           96                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          169                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8449500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      8449500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6089000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      6089000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14538500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     14538500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14538500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     14538500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.071322                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.071322                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076436                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.076436                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076436                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.076436                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83410.958904                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83410.958904                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86026.627219                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 86026.627219                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86026.627219                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 86026.627219                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                 0                       # number of replacements
system.cpu.icache.tags.tagsinuse           175.158440                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                2321                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               364                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              6.376374                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   175.158440                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.085527                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.085527                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          364                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          271                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.177734                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              5734                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             5734                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst         2321                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            2321                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          2321                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             2321                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         2321                       # number of overall hits
system.cpu.icache.overall_hits::total            2321                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          364                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           364                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          364                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            364                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          364                       # number of overall misses
system.cpu.icache.overall_misses::total           364                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     30321500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     30321500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     30321500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     30321500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     30321500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     30321500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         2685                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         2685                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         2685                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         2685                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         2685                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         2685                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.135568                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.135568                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.135568                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.135568                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.135568                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.135568                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83300.824176                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 83300.824176                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 83300.824176                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 83300.824176                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 83300.824176                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 83300.824176                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          364                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          364                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          364                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          364                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          364                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          364                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     29957500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     29957500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     29957500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     29957500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     29957500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     29957500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.135568                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.135568                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.135568                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.135568                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.135568                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.135568                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82300.824176                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82300.824176                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82300.824176                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 82300.824176                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82300.824176                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 82300.824176                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          279.188916                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              532                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.001880                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   175.158050                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   104.030866                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005345                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.003175                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.008520                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          532                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          422                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.016235                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             4796                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            4796                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          363                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          363                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data           96                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total           96                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          363                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          169                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           532                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          363                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          169                       # number of overall misses
system.cpu.l2cache.overall_misses::total          532                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5979500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      5979500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     29400000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     29400000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      8304000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total      8304000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     29400000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     14283500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     43683500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     29400000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     14283500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     43683500                       # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          364                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          364                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           96                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total           96                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          364                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          169                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          533                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          364                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          169                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          533                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.997253                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.997253                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.997253                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.998124                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.997253                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.998124                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81910.958904                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81910.958904                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80991.735537                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80991.735537                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        86500                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        86500                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80991.735537                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84517.751479                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82111.842105                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80991.735537                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84517.751479                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82111.842105                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          363                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          363                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           96                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total           96                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          363                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          169                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          532                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          363                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          532                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5249500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5249500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     25770000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     25770000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7344000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      7344000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     25770000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     12593500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     38363500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     25770000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     12593500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     38363500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.997253                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.997253                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.997253                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.998124                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.997253                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.998124                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71910.958904                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71910.958904                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70991.735537                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70991.735537                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        76500                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        76500                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70991.735537                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74517.751479                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72111.842105                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70991.735537                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74517.751479                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72111.842105                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests          533                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp           460                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          364                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq           96                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          728                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          338                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total              1066                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23296                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10816                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              34112                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples          533                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.001876                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.043315                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                532     99.81%     99.81% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  1      0.19%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            533                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         266500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        546000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        253500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests           532                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                459                       # Transaction distribution
system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           459                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1064                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1064                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        34048                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   34048                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               532                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     532    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 532                       # Request fanout histogram
system.membus.reqLayer0.occupancy              607000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy            2825000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              6.9                       # Layer utilization (%)

---------- End Simulation Statistics   ----------