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/gem5/src/arch/arm/insts/
H A Dbranch.hh12640:02188fc84bae Tue Mar 27 12:31:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix AArch32 branch instructions disassemble

This patch adds the generateDisassembly method for BranchReg, BranchImm
and BranchRegReg Base classes used by AArch32 branch instructions.

Change-Id: I6de015cc213335556d5187df3d4fcd765876262c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9503
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/arch/power/insts/
H A Dinteger.hh6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
H A Dfloating.hh6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
H A Dcondition.hh6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
H A Dmisc.hh6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/arch/null/
H A Disa_traits.hh13347:4085b1fa2288 Fri Oct 12 08:15:00 EDT 2018 Gabe Black <gabeblack@google.com> null: Stop specifying an endianness in isa_traits.hh.

The NULL ISA doesn't really have an endianness. Now that the packet
accessors which consumed that endianness are gone, we can get rid of
that setting as well.

Change-Id: I8dd4c7b8236b07df4458fea377865f30141121d4
Reviewed-on: https://gem5-review.googlesource.com/c/13466
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/cpu/
H A Dinst_pb_trace.hh11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
/gem5/src/cpu/minor/
H A Dfetch1.cc11568:91e95eb78191 Thu Jul 21 12:19:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Fix Minor SMT WFI/drain interaction issues

The behavior of WFI is to cause minor to cease evaluating
pipeline logic until an interrupt is observed, however
a user may wish to drain the system while a core is sleeping
due to a WFI. This patch makes WFI drain. If an actual
drain occurs during a WFI, the CPU is already drained and will
immediately be ready for swapping, checkpointing, etc. This
should not negatively impact performance as WFI instructions
are 'stream-changing' (treated like unpredicted branches), so
all remaining instructions are wrong-path and will be squashed
rapidly.

Change-Id: I63833d5acb53d8dde78f9f0c9611de0ece385e45
11567:560d7fbbddd1 Thu Jul 21 12:19:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Add SMT support to MinorCPU

This patch adds SMT support to the MinorCPU. Currently
RoundRobin or Random thread scheduling are supported.

Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3
11148:1bc3d93c7eaa Wed Sep 30 12:14:00 EDT 2015 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Add per-thread monitors

Adds per-thread address monitors to support FullSystem SMT.
10950:d262e02c26b3 Fri Jul 31 12:04:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Update debug message from Fetch1 isDrained() in Minor

Fix a spurious %s and include the state of the Fetch1 stage in the
debug printout.
/gem5/src/dev/pci/
H A Ddevice.cc13342:1ddb43f47325 Fri Oct 12 08:06:00 EDT 2018 Gabe Black <gabeblack@google.com> dev: Explicitly specify the endianness for packet accessors.

Generally speaking, the endianness of the data devices provide or
accept is dependent on the device and not the ISA the system
executes. This change makes the devices in dev pick an endianness
rather than using the guest's.

For the ISA bus and the UART, accesses are byte sized and so endianness
doesn't matter. The ISA and PCI busses and the devices which use them
are defined to be little endian.

Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f
Reviewed-on: https://gem5-review.googlesource.com/c/13462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/dev/serial/
H A Duart8250.cc13342:1ddb43f47325 Fri Oct 12 08:06:00 EDT 2018 Gabe Black <gabeblack@google.com> dev: Explicitly specify the endianness for packet accessors.

Generally speaking, the endianness of the data devices provide or
accept is dependent on the device and not the ISA the system
executes. This change makes the devices in dev pick an endianness
rather than using the guest's.

For the ISA bus and the UART, accesses are byte sized and so endianness
doesn't matter. The ISA and PCI busses and the devices which use them
are defined to be little endian.

Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f
Reviewed-on: https://gem5-review.googlesource.com/c/13462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/mem/
H A Ddrampower.cc10431:d9415c7f61a9 Tue Jul 29 12:29:00 EDT 2014 Omar Naji <Omar.Naji@arm.com> mem: Add DRAMPower wrapping class

This patch adds a class to wrap DRAMPower Library in gem5.
This class initiates an object of class MemorySpecification
of the DRAMPower Library, passes the parameters from DRAMCtrl.py
to this object and creates an object of drampower library using
the memory specification.
/gem5/src/mem/qos/
H A DQoSTurnaround.py12968:1c2b8dd9241f Thu May 10 12:07:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> mem: Implement base QoS Policies.

This patch implements a base fixed priority policy and an ideal
turnaround policy for the QoS memory controller.

Change-Id: I38ce16f845fc0ec86d6fc4cc5dc5406f213a465e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11972
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/system/arm/dt/
H A Darmv8_big_little.dts11569:2eae1dfaa791 Thu Jul 21 12:19:00 EDT 2016 Gabor Dozsa <gabor.dozsa@arm.com> arm, config: Add an example ARM big.LITTLE(tm) configuration script

An ARM big.LITTLE system consists of two cpu clusters: the big
CPUs are typically complex out-of-order cores and the little
CPUs are simpler in-order ones. The fs_bigLITTLE.py script
can run a full system simulation with various number of big
and little cores and cache hierarchy. The commit also includes
two example device tree files for booting Linux on the
bigLITTLE system.

Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/configs/common/
H A DGPUTLBOptions.py12647:6d7e2f321496 Thu Apr 12 17:38:00 EDT 2018 Tony Gutierrez <anthony.gutierrez@amd.com> configs, mem-ruby: fix issues with style in AMD license

fixes line length and white space issues.

Change-Id: Ia04a91ec68cae2bcdabeb93bb1a0f74e8e5486c3
Reviewed-on: https://gem5-review.googlesource.com/9801
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
/gem5/ext/mcpat/regression/
H A Dregression.py13540:da30e62884ee Thu Jan 10 10:12:00 EST 2019 Andrea Mondelli <andrea.mondelli@ucf.edu> misc: updated shabang for python script

The default python on MacOS doesn’t have an alias to python2.
The official python version supported in gem5 is Python2.7.

This patch updates the shabang according to the version required in gem5.

Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0
Reviewed-on: https://gem5-review.googlesource.com/c/15375
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dverify_output.py13540:da30e62884ee Thu Jan 10 10:12:00 EST 2019 Andrea Mondelli <andrea.mondelli@ucf.edu> misc: updated shabang for python script

The default python on MacOS doesn’t have an alias to python2.
The official python version supported in gem5 is Python2.7.

This patch updates the shabang according to the version required in gem5.

Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0
Reviewed-on: https://gem5-review.googlesource.com/c/15375
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/arch/generic/
H A Dtraits.hh13601:f5c84915eb7f Thu Jan 10 12:26:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu, arch, arch-arm: Wire unused VecElem code in the O3 model

VecElem code had been introduced in order to simulate change of renaming
for vector registers. Most of the work is happening on the rename_map
switchRenameMode. Change of renaming can happen after a squash in the
pipeline.
This patch is also changing the interface to the ISA part so that
a PCState is used instead of ISA in order to check if rename mode
has changed.

Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15601
/gem5/src/arch/sparc/
H A DSparcNativeTrace.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
/gem5/src/arch/x86/
H A DX86NativeTrace.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
/gem5/src/dev/
H A DBadDevice.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
/gem5/src/mem/slicc/
H A Dutil.py6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
/gem5/src/python/m5/
H A Doptions.py5586:d27058799d3a Mon Oct 06 12:31:00 EDT 2008 Nathan Binkert <nate@binkert.org> python: cleanup options parsing stuff so that it properly deals with defaults.
While we're at it, make it possible to run main.py in a somewhat
standalone mode again so that we can test things without compiling.
/gem5/src/systemc/ext/tlm_core/1/analysis/
H A Danalysis.hh13521:74fa3ac44057 Wed Dec 12 19:43:00 EST 2018 Gabe Black <gabeblack@google.com> systemc: Rename tlm_core header files to have a .hh extentension.

This makes those files more consistent with other headers in gem5. The
top level headers (tlm and tlm.h) and the tlm_utils headers were left
alone since the user might reasonably expect those to have a well known
name. The tlm_core headers by comparison are an implementation detail,
and users shouldn't include them directly by name.

Change-Id: Ibc82e8159e47717c79d76f50ed96fdd619294a06
Reviewed-on: https://gem5-review.googlesource.com/c/15067
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
H A Danalysis_fifo.hh13521:74fa3ac44057 Wed Dec 12 19:43:00 EST 2018 Gabe Black <gabeblack@google.com> systemc: Rename tlm_core header files to have a .hh extentension.

This makes those files more consistent with other headers in gem5. The
top level headers (tlm and tlm.h) and the tlm_utils headers were left
alone since the user might reasonably expect those to have a well known
name. The tlm_core headers by comparison are an implementation detail,
and users shouldn't include them directly by name.

Change-Id: Ibc82e8159e47717c79d76f50ed96fdd619294a06
Reviewed-on: https://gem5-review.googlesource.com/c/15067
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
H A Danalysis_if.hh13521:74fa3ac44057 Wed Dec 12 19:43:00 EST 2018 Gabe Black <gabeblack@google.com> systemc: Rename tlm_core header files to have a .hh extentension.

This makes those files more consistent with other headers in gem5. The
top level headers (tlm and tlm.h) and the tlm_utils headers were left
alone since the user might reasonably expect those to have a well known
name. The tlm_core headers by comparison are an implementation detail,
and users shouldn't include them directly by name.

Change-Id: Ibc82e8159e47717c79d76f50ed96fdd619294a06
Reviewed-on: https://gem5-review.googlesource.com/c/15067
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

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