Searched hist:11676 (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/mem/ | ||
| H A D | dram_ctrl.hh | 11676:8a882e297eb2 Thu Oct 13 14:22:00 EDT 2016 Wendy Elsasser <wendy.elsasser@arm.com> mem: Modify drain to ensure banks and power are idled Add constraint that all ranks have to be in PWR_IDLE before signaling drain complete This will ensure that the banks are all closed and the rank has exited any low-power states. On suspend, update the power stats to sync the DRAM power logic The logic maintains the location of the signalDrainDone method, which is still triggered from either: 1) Read response event 2) Next request event This ensures that the drain will complete in the READ bus state and minimizes the changes required. Change-Id: If1476e631ea7d5999fe50a0c9379c5967a90e3d1 Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> |
| H A D | dram_ctrl.cc | 11676:8a882e297eb2 Thu Oct 13 14:22:00 EDT 2016 Wendy Elsasser <wendy.elsasser@arm.com> mem: Modify drain to ensure banks and power are idled Add constraint that all ranks have to be in PWR_IDLE before signaling drain complete This will ensure that the banks are all closed and the rank has exited any low-power states. On suspend, update the power stats to sync the DRAM power logic The logic maintains the location of the signalDrainDone method, which is still triggered from either: 1) Read response event 2) Next request event This ensures that the drain will complete in the READ bus state and minimizes the changes required. Change-Id: If1476e631ea7d5999fe50a0c9379c5967a90e3d1 Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> |
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