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/gem5/src/cpu/simple/ | ||
H A D | timing.cc | 11435:0f1b46dde3fa Thu Apr 07 10:30:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> mem: Remove threadId from memory request class In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu. This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit. |
H A D | atomic.cc | 11435:0f1b46dde3fa Thu Apr 07 10:30:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> mem: Remove threadId from memory request class In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu. This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit. |
/gem5/src/cpu/o3/ | ||
H A D | fetch_impl.hh | 11435:0f1b46dde3fa Thu Apr 07 10:30:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> mem: Remove threadId from memory request class In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu. This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit. |
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