Searched hist:11136 (Results 1 - 4 of 4) sorted by relevance
| /gem5/src/arch/riscv/ | ||
| H A D | faults.hh | 12850:7036cad54910 Sun Jun 10 18:41:00 EDT 2018 Alec Roelke <alec.roelke@gmail.com> arch-riscv: Add xret instructions This patch adds the uret, sret, and mret instructions for use with returning from user-, supervisor-, and machine-level code, respectively. These instructions read the STATUS register to determine the previous privilege level and modify it to re-enable interrupts at the old privilege level. These instructions can only be executed at the corresponding privilege level or higher. Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9 Reviewed-on: https://gem5-review.googlesource.com/11136 Maintainer: Alec Roelke <alec.roelke@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Robert Scheffel <robert.scheffel1@tu-dresden.de> |
| H A D | registers.hh | 12850:7036cad54910 Sun Jun 10 18:41:00 EDT 2018 Alec Roelke <alec.roelke@gmail.com> arch-riscv: Add xret instructions This patch adds the uret, sret, and mret instructions for use with returning from user-, supervisor-, and machine-level code, respectively. These instructions read the STATUS register to determine the previous privilege level and modify it to re-enable interrupts at the old privilege level. These instructions can only be executed at the corresponding privilege level or higher. Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9 Reviewed-on: https://gem5-review.googlesource.com/11136 Maintainer: Alec Roelke <alec.roelke@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Robert Scheffel <robert.scheffel1@tu-dresden.de> |
| /gem5/src/arch/riscv/isa/ | ||
| H A D | decoder.isa | 12850:7036cad54910 Sun Jun 10 18:41:00 EDT 2018 Alec Roelke <alec.roelke@gmail.com> arch-riscv: Add xret instructions This patch adds the uret, sret, and mret instructions for use with returning from user-, supervisor-, and machine-level code, respectively. These instructions read the STATUS register to determine the previous privilege level and modify it to re-enable interrupts at the old privilege level. These instructions can only be executed at the corresponding privilege level or higher. Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9 Reviewed-on: https://gem5-review.googlesource.com/11136 Maintainer: Alec Roelke <alec.roelke@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Robert Scheffel <robert.scheffel1@tu-dresden.de> |
| /gem5/src/mem/cache/ | ||
| H A D | cache.cc | 11136:3fd483cdd458 Fri Sep 25 07:26:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Fix WriteLineReq fill behaviour This patch fixes issues in the interactions between deferred snoops and WriteLineReq. More specifically, the patch addresses an issue where deferred snoops caused assertion failures when being serviced on the arrival of an InvalidateResp. The response packet was perceived to be invalidating, when actually it is not for the cache that sent out the original invalidation request. |
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