Searched hist:11135 (Results 1 - 8 of 8) sorted by relevance
| /gem5/src/arch/riscv/insts/ | ||
| H A D | unknown.hh | 12849:7f43ad13ebf0 Sun Feb 18 22:28:00 EST 2018 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Add support for trap value register RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses. Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Reviewed-on: https://gem5-review.googlesource.com/11135 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
| /gem5/src/arch/riscv/isa/formats/ | ||
| H A D | fp.isa | 12849:7f43ad13ebf0 Sun Feb 18 22:28:00 EST 2018 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Add support for trap value register RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses. Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Reviewed-on: https://gem5-review.googlesource.com/11135 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
| H A D | standard.isa | 12849:7f43ad13ebf0 Sun Feb 18 22:28:00 EST 2018 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Add support for trap value register RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses. Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Reviewed-on: https://gem5-review.googlesource.com/11135 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
| /gem5/src/arch/riscv/ | ||
| H A D | faults.hh | 12849:7f43ad13ebf0 Sun Feb 18 22:28:00 EST 2018 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Add support for trap value register RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses. Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Reviewed-on: https://gem5-review.googlesource.com/11135 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
| H A D | faults.cc | 12849:7f43ad13ebf0 Sun Feb 18 22:28:00 EST 2018 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Add support for trap value register RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses. Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Reviewed-on: https://gem5-review.googlesource.com/11135 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
| /gem5/src/mem/ | ||
| H A D | snoop_filter.hh | 11135:9d09dab39689 Fri Sep 25 07:26:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Comment clean-up for the snoop filter Merely fixing up some style issues and adding more comments. |
| H A D | snoop_filter.cc | 11135:9d09dab39689 Fri Sep 25 07:26:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Comment clean-up for the snoop filter Merely fixing up some style issues and adding more comments. |
| /gem5/src/arch/riscv/isa/ | ||
| H A D | decoder.isa | 12849:7f43ad13ebf0 Sun Feb 18 22:28:00 EST 2018 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Add support for trap value register RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses. Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Reviewed-on: https://gem5-review.googlesource.com/11135 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> |
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