1# See LICENSE for license details. 2 3#***************************************************************************** 4# blt.S 5#----------------------------------------------------------------------------- 6# 7# Test blt instruction. 8# 9 10#include "riscv_test.h" 11#include "test_macros.h" 12 13RVTEST_RV64U 14RVTEST_CODE_BEGIN 15 16 #------------------------------------------------------------- 17 # Branch tests 18 #------------------------------------------------------------- 19 20 # Each test checks both forward and backward branches 21 22 TEST_BR2_OP_TAKEN( 2, blt, 0, 1 ); 23 TEST_BR2_OP_TAKEN( 3, blt, -1, 1 ); 24 TEST_BR2_OP_TAKEN( 4, blt, -2, -1 ); 25 26 TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 ); 27 TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 ); 28 TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 ); 29 TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 ); 30 31 #------------------------------------------------------------- 32 # Bypassing tests 33 #------------------------------------------------------------- 34 35 TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 ); 36 TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 ); 37 TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 ); 38 TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 ); 39 TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 ); 40 TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 ); 41 42 TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 ); 43 TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 ); 44 TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 ); 45 TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 ); 46 TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 ); 47 TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 ); 48 49 #------------------------------------------------------------- 50 # Test delay slot instructions not executed nor bypassed 51 #------------------------------------------------------------- 52 53 TEST_CASE( 21, x1, 3, \ 54 li x1, 1; \ 55 blt x0, x1, 1f; \ 56 addi x1, x1, 1; \ 57 addi x1, x1, 1; \ 58 addi x1, x1, 1; \ 59 addi x1, x1, 1; \ 601: addi x1, x1, 1; \ 61 addi x1, x1, 1; \ 62 ) 63 64 TEST_PASSFAIL 65 66RVTEST_CODE_END 67 68 .data 69RVTEST_DATA_BEGIN 70 71 TEST_DATA 72 73RVTEST_DATA_END 74