stats.txt revision 11507
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.270600 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 270599529500 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711507SCurtis.Dunham@arm.comhost_inst_rate 833752 # Simulator instruction rate (inst/s) 811507SCurtis.Dunham@arm.comhost_op_rate 833752 # Simulator op (including micro ops) rate (op/s) 911507SCurtis.Dunham@arm.comhost_tick_rate 1166291607 # Simulator tick rate (ticks/s) 1011507SCurtis.Dunham@arm.comhost_mem_usage 251752 # Number of bytes of host memory used 1111507SCurtis.Dunham@arm.comhost_seconds 232.02 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 193444518 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 193444756 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 331072 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 5173 # Number of read requests responded to by this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) 2511507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) 2611507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) 2711507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) 2811507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) 2911507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) 3011507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) 3111507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) 3211507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3311507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 401 # Number of system calls 3411507SCurtis.Dunham@arm.comsystem.cpu.numCycles 541199059 # number of cpu cycles simulated 3511507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3611507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 3711507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 193444518 # Number of instructions committed 3811507SCurtis.Dunham@arm.comsystem.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 3911507SCurtis.Dunham@arm.comsystem.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 4011507SCurtis.Dunham@arm.comsystem.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 4111507SCurtis.Dunham@arm.comsystem.cpu.num_func_calls 1957920 # number of times a function call or return occured 4211507SCurtis.Dunham@arm.comsystem.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 4311507SCurtis.Dunham@arm.comsystem.cpu.num_int_insts 167974806 # number of integer instructions 4411507SCurtis.Dunham@arm.comsystem.cpu.num_fp_insts 1970372 # number of float instructions 4511507SCurtis.Dunham@arm.comsystem.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 4611507SCurtis.Dunham@arm.comsystem.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 4711507SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 4811507SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 4911507SCurtis.Dunham@arm.comsystem.cpu.num_mem_refs 76733958 # number of memory refs 5011507SCurtis.Dunham@arm.comsystem.cpu.num_load_insts 57735091 # Number of load instructions 5111507SCurtis.Dunham@arm.comsystem.cpu.num_store_insts 18998867 # Number of store instructions 5211507SCurtis.Dunham@arm.comsystem.cpu.num_idle_cycles 0.002000 # Number of idle cycles 5311507SCurtis.Dunham@arm.comsystem.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles 5411507SCurtis.Dunham@arm.comsystem.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 5511507SCurtis.Dunham@arm.comsystem.cpu.idle_fraction 0.000000 # Percentage of idle cycles 5611507SCurtis.Dunham@arm.comsystem.cpu.Branches 15132745 # Number of branches fetched 5711507SCurtis.Dunham@arm.comsystem.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction 5811507SCurtis.Dunham@arm.comsystem.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction 5911507SCurtis.Dunham@arm.comsystem.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction 6011507SCurtis.Dunham@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction 6111507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction 6211507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction 6311507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction 6411507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction 6511507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction 6611507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction 6711507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction 6811507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction 6911507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction 7011507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction 7111507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction 7211507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction 7311507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction 7411507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction 7511507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction 7611507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction 7711507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction 7811507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction 7911507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction 8011507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction 8111507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction 8211507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction 8311507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction 8411507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction 8511507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 8611507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 8711507SCurtis.Dunham@arm.comsystem.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction 8811507SCurtis.Dunham@arm.comsystem.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction 8911507SCurtis.Dunham@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 9011507SCurtis.Dunham@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 9111507SCurtis.Dunham@arm.comsystem.cpu.op_class::total 193445773 # Class of executed instruction 9211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 2 # number of replacements 9311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use 9411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 9511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 9611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 9711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 9811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor 9911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy 10011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy 10111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 10211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 10311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 10411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 10511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 10611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id 10711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id 10811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses 10911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses 11011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 11111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 11211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 11311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 11411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 11511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 11611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 11711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits 11811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits 11911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 76709932 # number of overall hits 12011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 12111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses 12211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses 12311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses 12411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses 12511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses 12611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses 12711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses 12811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses 12911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 1575 # number of overall misses 13011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles 13111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles 13211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles 13311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles 13411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles 13511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles 13611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles 13711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles 13811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles 13911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles 14011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) 14111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) 14211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) 14311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) 14411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) 14511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) 14611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses 14711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses 14811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses 14911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses 15011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses 15111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses 15211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses 15311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses 15411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses 15511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses 15611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses 15711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses 15811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses 15911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses 16011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency 16111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency 16211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency 16311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency 16411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency 16511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency 16611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency 16711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency 16811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency 16911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency 17011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 17111507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 17211507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 17311507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 17411507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 17511507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 17611507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 2 # number of writebacks 17711507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 2 # number of writebacks 17811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 17911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 18011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 18111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 18211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 18311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses 18411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses 18511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses 18611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses 18711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses 18811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles 18911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles 19011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles 19111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles 19211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles 19311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles 19411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles 19511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles 19611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles 19711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles 19811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 19911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 20011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses 20111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses 20211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses 20311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses 20411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses 20511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses 20611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses 20711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses 20811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency 20911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency 21011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency 21111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency 21211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency 21311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency 21411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 21511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency 21611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 21711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency 21811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 10362 # number of replacements 21911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use 22011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 22111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 22211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 22311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 22411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor 22511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy 22611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy 22711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 22811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 22911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 23011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 23111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 23211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id 23311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id 23411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses 23511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 386903360 # Number of data accesses 23611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 23711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 23811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 23911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 24011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 24111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 193433248 # number of overall hits 24211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 24311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 24411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 24511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 24611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 24711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 12288 # number of overall misses 24811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles 24911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles 25011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles 25111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles 25211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles 25311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles 25411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 25511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 25611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 25711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 25811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 25911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 26011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 26111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 26211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 26311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 26411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 26511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses 26611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency 26711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency 26811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency 26911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency 27011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency 27111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency 27211507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 27311507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 27411507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 27511507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 27611507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 27711507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 27811507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 10362 # number of writebacks 27911507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 10362 # number of writebacks 28011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 28111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 28211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 28311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 28411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 28511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses 28611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles 28711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles 28811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles 28911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles 29011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles 29111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles 29211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 29311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 29411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 29511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 29611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 29711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 29811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency 29911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency 30011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 30111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency 30211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 30311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency 30411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 30511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use 30611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. 30711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 30811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. 30911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 31011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor 31111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor 31211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor 31311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy 31411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy 31511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy 31611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy 31711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id 31811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 31911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id 32011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id 32111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id 32211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id 32311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id 32411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses 32511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses 32611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits 32711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits 32811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits 32911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits 33011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits 33111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits 33211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 33311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits 33411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits 33511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 8691 # number of overall hits 33611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses 33711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses 33811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3597 # number of ReadCleanReq misses 33911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 3597 # number of ReadCleanReq misses 34011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses 34111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses 34211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses 34311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses 34411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses 34511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses 34611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses 34711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 5173 # number of overall misses 34811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles 34911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles 35011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles 35111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles 35211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles 35311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles 35411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles 35511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles 35611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles 35711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles 35811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles 35911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles 36011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) 36111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) 36211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) 36311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses) 36411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) 36511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) 36611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) 36711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses) 36811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 498 # number of ReadSharedReq accesses(hits+misses) 36911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 498 # number of ReadSharedReq accesses(hits+misses) 37011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses 37111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses 37211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses 37311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses 37411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses 37511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses 37611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 37711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 37811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadCleanReq accesses 37911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.292725 # miss rate for ReadCleanReq accesses 38011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 38111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 38211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses 38311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 38411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses 38511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses 38611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 38711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses 38811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency 38911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency 39011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency 39111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency 39211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency 39311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency 39411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency 39511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency 39611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency 39711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency 39811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency 39911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency 40011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 40111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 40211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 40311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 40411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 40511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 40611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 40711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 40811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses 40911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses 41011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses 41111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses 41211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 41311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses 41411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses 41511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses 41611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses 41711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses 41811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles 41911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles 42011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles 42111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles 42211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles 42311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles 42411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles 42511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles 42611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles 42711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles 42811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles 42911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles 43011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 43111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 43211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses 43311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses 43411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 43511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 43611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses 43711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 43811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses 43911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses 44011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 44111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses 44211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency 44311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency 44411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency 44511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency 44611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency 44711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency 44811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency 44911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 45011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency 45111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency 45211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 45311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency 45411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. 45511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. 45611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 45711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 45811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 45911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 46011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 46111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution 46211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution 46311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 46411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 46511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution 46611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution 46711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) 46811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) 46911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) 47011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes) 47111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) 47211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes) 47311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 47411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram 47511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram 47611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram 47711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 47811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram 47911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram 48011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 48111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 48311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 48411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram 48511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) 48611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 48711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 48811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 48911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 49011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 49111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 4095 # Transaction distribution 49211507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 1078 # Transaction distribution 49311507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 1078 # Transaction distribution 49411507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution 49511507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) 49611507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) 49711507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) 49811507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) 49911507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 50011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 5173 # Request fanout histogram 50111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 50211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 50311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 50411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram 50511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 50611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 50711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 50811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 50911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 5173 # Request fanout histogram 51011507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks) 51111507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 51211507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks) 51311507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.0 # Layer utilization (%) 51411507SCurtis.Dunham@arm.com 51511507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 516