stats.txt revision 11507
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.270600 # Number of seconds simulated 4sim_ticks 270599529500 # Number of ticks simulated 5final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 833752 # Simulator instruction rate (inst/s) 8host_op_rate 833752 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1166291607 # Simulator tick rate (ticks/s) 10host_mem_usage 251752 # Number of bytes of host memory used 11host_seconds 232.02 # Real time elapsed on the host 12sim_insts 193444518 # Number of instructions simulated 13sim_ops 193444756 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory 18system.physmem.bytes_read::total 331072 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 401 # Number of system calls 34system.cpu.numCycles 541199059 # number of cpu cycles simulated 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 193444518 # Number of instructions committed 38system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses 41system.cpu.num_func_calls 1957920 # number of times a function call or return occured 42system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls 43system.cpu.num_int_insts 167974806 # number of integer instructions 44system.cpu.num_fp_insts 1970372 # number of float instructions 45system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read 46system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written 47system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read 48system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written 49system.cpu.num_mem_refs 76733958 # number of memory refs 50system.cpu.num_load_insts 57735091 # Number of load instructions 51system.cpu.num_store_insts 18998867 # Number of store instructions 52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 53system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles 54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 56system.cpu.Branches 15132745 # Number of branches fetched 57system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction 58system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction 59system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction 60system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction 61system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction 62system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction 63system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction 64system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction 65system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction 66system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction 67system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction 68system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction 69system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction 70system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction 71system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction 72system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction 73system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction 74system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction 75system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction 76system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction 77system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction 78system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction 79system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction 80system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction 81system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction 82system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction 83system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction 84system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction 87system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction 88system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 193445773 # Class of executed instruction 92system.cpu.dcache.tags.replacements 2 # number of replacements 93system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use 94system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. 97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 98system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor 99system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 104system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id 107system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id 108system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses 109system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses 110system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits 111system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits 112system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits 113system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits 114system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits 115system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits 116system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits 117system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits 118system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits 119system.cpu.dcache.overall_hits::total 76709932 # number of overall hits 120system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses 121system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses 122system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses 123system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses 124system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses 125system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses 126system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses 127system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses 128system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses 129system.cpu.dcache.overall_misses::total 1575 # number of overall misses 130system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles 131system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles 132system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles 133system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles 134system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles 135system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles 136system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles 137system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles 138system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles 139system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles 140system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) 141system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) 142system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) 143system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) 144system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) 145system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) 146system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses 147system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses 148system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses 149system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses 150system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses 151system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses 152system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses 153system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses 154system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses 155system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses 156system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses 157system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses 158system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses 159system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses 160system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency 161system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency 163system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency 164system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency 165system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency 166system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency 167system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency 168system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency 169system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency 170system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 171system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 172system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 173system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 174system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 175system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 176system.cpu.dcache.writebacks::writebacks 2 # number of writebacks 177system.cpu.dcache.writebacks::total 2 # number of writebacks 178system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses 179system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses 181system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses 182system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses 183system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses 184system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses 185system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses 186system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses 187system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses 188system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles 189system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles 190system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles 191system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles 192system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles 193system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles 194system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles 195system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles 196system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles 197system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles 198system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 199system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 200system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses 201system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses 202system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses 203system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses 204system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses 205system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses 206system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses 207system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses 208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency 209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency 210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency 211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency 212system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency 213system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency 214system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 215system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency 216system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency 217system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency 218system.cpu.icache.tags.replacements 10362 # number of replacements 219system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use 220system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. 221system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. 222system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. 223system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 224system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor 225system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy 226system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy 227system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id 228system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 229system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 230system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id 232system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id 233system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id 234system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses 235system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses 236system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits 237system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits 238system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits 239system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits 240system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits 241system.cpu.icache.overall_hits::total 193433248 # number of overall hits 242system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses 243system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses 244system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses 245system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses 246system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses 247system.cpu.icache.overall_misses::total 12288 # number of overall misses 248system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles 249system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles 250system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles 251system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles 252system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles 253system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles 254system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) 255system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) 256system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses 257system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses 258system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses 259system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses 260system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses 261system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses 262system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses 263system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses 264system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses 265system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses 266system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency 267system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency 268system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency 269system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency 270system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency 271system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency 272system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 273system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 274system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 275system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 276system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 277system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 278system.cpu.icache.writebacks::writebacks 10362 # number of writebacks 279system.cpu.icache.writebacks::total 10362 # number of writebacks 280system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses 281system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses 282system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses 283system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses 284system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses 285system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses 286system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles 287system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles 288system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles 289system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles 290system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles 291system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles 292system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 293system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses 294system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses 295system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses 296system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses 297system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses 298system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency 299system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency 300system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 301system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency 302system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency 303system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency 304system.cpu.l2cache.tags.replacements 0 # number of replacements 305system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use 306system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. 307system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. 308system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. 309system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 310system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor 311system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor 312system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor 313system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy 314system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy 315system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy 316system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy 317system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id 318system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 319system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id 320system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id 321system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id 322system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id 323system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id 324system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses 325system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses 326system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits 327system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits 328system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits 329system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits 330system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits 331system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits 332system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits 333system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits 334system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits 335system.cpu.l2cache.overall_hits::total 8691 # number of overall hits 336system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses 337system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses 338system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3597 # number of ReadCleanReq misses 339system.cpu.l2cache.ReadCleanReq_misses::total 3597 # number of ReadCleanReq misses 340system.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses 341system.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses 342system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses 343system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses 344system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses 345system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses 346system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses 347system.cpu.l2cache.overall_misses::total 5173 # number of overall misses 348system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles 349system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles 350system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles 351system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles 352system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles 353system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles 354system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles 355system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles 356system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles 357system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles 358system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles 359system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles 360system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) 361system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) 362system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) 363system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses) 364system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) 365system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) 366system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) 367system.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses) 368system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 498 # number of ReadSharedReq accesses(hits+misses) 369system.cpu.l2cache.ReadSharedReq_accesses::total 498 # number of ReadSharedReq accesses(hits+misses) 370system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses 371system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses 372system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses 373system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses 374system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses 375system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses 376system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 377system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 378system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadCleanReq accesses 379system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.292725 # miss rate for ReadCleanReq accesses 380system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 381system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 382system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses 383system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 384system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses 385system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses 386system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 387system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses 388system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency 389system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency 390system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency 391system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency 392system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency 393system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency 394system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency 395system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency 396system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency 397system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency 398system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency 399system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency 400system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 401system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 402system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 403system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 404system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 405system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 406system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses 407system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses 408system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses 409system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses 410system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses 411system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses 412system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses 413system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses 414system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses 415system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses 416system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses 417system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses 418system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles 419system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles 420system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles 421system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles 422system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles 423system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles 424system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles 425system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles 426system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles 427system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles 428system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles 429system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles 430system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 431system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 432system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses 433system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses 434system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 435system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 436system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses 437system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 438system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses 439system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses 440system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 441system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses 442system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency 443system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency 444system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency 445system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency 446system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency 447system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency 448system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency 449system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 450system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency 451system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency 452system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency 453system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency 454system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. 455system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. 456system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 457system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 458system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 459system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 460system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution 467system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) 468system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) 469system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) 470system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes) 471system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) 472system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes) 473system.cpu.toL2Bus.snoops 0 # Total snoops (count) 474system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram 475system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram 476system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram 477system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 478system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram 479system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram 480system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 481system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 482system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 483system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 484system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram 485system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) 486system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 487system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) 488system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 489system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) 490system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 491system.membus.trans_dist::ReadResp 4095 # Transaction distribution 492system.membus.trans_dist::ReadExReq 1078 # Transaction distribution 493system.membus.trans_dist::ReadExResp 1078 # Transaction distribution 494system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution 495system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) 496system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) 497system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) 498system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) 499system.membus.snoops 0 # Total snoops (count) 500system.membus.snoop_fanout::samples 5173 # Request fanout histogram 501system.membus.snoop_fanout::mean 0 # Request fanout histogram 502system.membus.snoop_fanout::stdev 0 # Request fanout histogram 503system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 504system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram 505system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 506system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 507system.membus.snoop_fanout::min_value 0 # Request fanout histogram 508system.membus.snoop_fanout::max_value 0 # Request fanout histogram 509system.membus.snoop_fanout::total 5173 # Request fanout histogram 510system.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks) 511system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 512system.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks) 513system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 514 515---------- End Simulation Statistics ---------- 516