config.ini revision 9055:38f1926fb599
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=timing 17memories=system.physmem 18num_work_ids=16 19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1 28system_port=system.membus.slave[1] 29 30[system.cpu0] 31type=DerivO3CPU 32children=dcache dtb fuPool icache interrupts itb tracer workload 33BTBEntries=4096 34BTBTagSize=16 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39RASSize=16 40SQEntries=32 41SSITSize=1024 42activity=0 43backComSize=5 44cachePorts=200 45checker=Null 46choiceCtrBits=2 47choicePredictorSize=8192 48clock=500 49commitToDecodeDelay=1 50commitToFetchDelay=1 51commitToIEWDelay=1 52commitToRenameDelay=1 53commitWidth=8 54cpu_id=0 55decodeToFetchDelay=1 56decodeToRenameDelay=1 57decodeWidth=8 58defer_registration=false 59dispatchWidth=8 60do_checkpoint_insts=true 61do_quiesce=true 62do_statistics_insts=true 63dtb=system.cpu0.dtb 64fetchToDecodeDelay=1 65fetchTrapLatency=1 66fetchWidth=8 67forwardComSize=5 68fuPool=system.cpu0.fuPool 69function_trace=false 70function_trace_start=0 71globalCtrBits=2 72globalHistoryBits=13 73globalPredictorSize=8192 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78instShiftAmt=2 79interrupts=system.cpu0.interrupts 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu0.itb 83localCtrBits=2 84localHistoryBits=11 85localHistoryTableSize=2048 86localPredictorSize=2048 87max_insts_all_threads=0 88max_insts_any_thread=0 89max_loads_all_threads=0 90max_loads_any_thread=0 91needsTSO=false 92numIQEntries=64 93numPhysFloatRegs=256 94numPhysIntRegs=256 95numROBEntries=192 96numRobs=1 97numThreads=1 98phase=0 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu0.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu0.workload 124dcache_port=system.cpu0.dcache.cpu_side 125icache_port=system.cpu0.icache.cpu_side 126 127[system.cpu0.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=4 131block_size=64 132forward_snoops=true 133hash_delay=1 134is_top_level=true 135latency=1000 136max_miss_count=0 137mshrs=4 138prefetch_on_access=false 139prefetcher=Null 140prioritizeRequests=false 141repl=Null 142size=32768 143subblock_size=0 144system=system 145tgts_per_mshr=20 146trace_addr=0 147two_queue=false 148write_buffers=8 149cpu_side=system.cpu0.dcache_port 150mem_side=system.toL2Bus.slave[1] 151 152[system.cpu0.dtb] 153type=SparcTLB 154size=64 155 156[system.cpu0.fuPool] 157type=FUPool 158children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 159FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 160 161[system.cpu0.fuPool.FUList0] 162type=FUDesc 163children=opList 164count=6 165opList=system.cpu0.fuPool.FUList0.opList 166 167[system.cpu0.fuPool.FUList0.opList] 168type=OpDesc 169issueLat=1 170opClass=IntAlu 171opLat=1 172 173[system.cpu0.fuPool.FUList1] 174type=FUDesc 175children=opList0 opList1 176count=2 177opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 178 179[system.cpu0.fuPool.FUList1.opList0] 180type=OpDesc 181issueLat=1 182opClass=IntMult 183opLat=3 184 185[system.cpu0.fuPool.FUList1.opList1] 186type=OpDesc 187issueLat=19 188opClass=IntDiv 189opLat=20 190 191[system.cpu0.fuPool.FUList2] 192type=FUDesc 193children=opList0 opList1 opList2 194count=4 195opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 196 197[system.cpu0.fuPool.FUList2.opList0] 198type=OpDesc 199issueLat=1 200opClass=FloatAdd 201opLat=2 202 203[system.cpu0.fuPool.FUList2.opList1] 204type=OpDesc 205issueLat=1 206opClass=FloatCmp 207opLat=2 208 209[system.cpu0.fuPool.FUList2.opList2] 210type=OpDesc 211issueLat=1 212opClass=FloatCvt 213opLat=2 214 215[system.cpu0.fuPool.FUList3] 216type=FUDesc 217children=opList0 opList1 opList2 218count=2 219opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 220 221[system.cpu0.fuPool.FUList3.opList0] 222type=OpDesc 223issueLat=1 224opClass=FloatMult 225opLat=4 226 227[system.cpu0.fuPool.FUList3.opList1] 228type=OpDesc 229issueLat=12 230opClass=FloatDiv 231opLat=12 232 233[system.cpu0.fuPool.FUList3.opList2] 234type=OpDesc 235issueLat=24 236opClass=FloatSqrt 237opLat=24 238 239[system.cpu0.fuPool.FUList4] 240type=FUDesc 241children=opList 242count=0 243opList=system.cpu0.fuPool.FUList4.opList 244 245[system.cpu0.fuPool.FUList4.opList] 246type=OpDesc 247issueLat=1 248opClass=MemRead 249opLat=1 250 251[system.cpu0.fuPool.FUList5] 252type=FUDesc 253children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 254count=4 255opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 256 257[system.cpu0.fuPool.FUList5.opList00] 258type=OpDesc 259issueLat=1 260opClass=SimdAdd 261opLat=1 262 263[system.cpu0.fuPool.FUList5.opList01] 264type=OpDesc 265issueLat=1 266opClass=SimdAddAcc 267opLat=1 268 269[system.cpu0.fuPool.FUList5.opList02] 270type=OpDesc 271issueLat=1 272opClass=SimdAlu 273opLat=1 274 275[system.cpu0.fuPool.FUList5.opList03] 276type=OpDesc 277issueLat=1 278opClass=SimdCmp 279opLat=1 280 281[system.cpu0.fuPool.FUList5.opList04] 282type=OpDesc 283issueLat=1 284opClass=SimdCvt 285opLat=1 286 287[system.cpu0.fuPool.FUList5.opList05] 288type=OpDesc 289issueLat=1 290opClass=SimdMisc 291opLat=1 292 293[system.cpu0.fuPool.FUList5.opList06] 294type=OpDesc 295issueLat=1 296opClass=SimdMult 297opLat=1 298 299[system.cpu0.fuPool.FUList5.opList07] 300type=OpDesc 301issueLat=1 302opClass=SimdMultAcc 303opLat=1 304 305[system.cpu0.fuPool.FUList5.opList08] 306type=OpDesc 307issueLat=1 308opClass=SimdShift 309opLat=1 310 311[system.cpu0.fuPool.FUList5.opList09] 312type=OpDesc 313issueLat=1 314opClass=SimdShiftAcc 315opLat=1 316 317[system.cpu0.fuPool.FUList5.opList10] 318type=OpDesc 319issueLat=1 320opClass=SimdSqrt 321opLat=1 322 323[system.cpu0.fuPool.FUList5.opList11] 324type=OpDesc 325issueLat=1 326opClass=SimdFloatAdd 327opLat=1 328 329[system.cpu0.fuPool.FUList5.opList12] 330type=OpDesc 331issueLat=1 332opClass=SimdFloatAlu 333opLat=1 334 335[system.cpu0.fuPool.FUList5.opList13] 336type=OpDesc 337issueLat=1 338opClass=SimdFloatCmp 339opLat=1 340 341[system.cpu0.fuPool.FUList5.opList14] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatCvt 345opLat=1 346 347[system.cpu0.fuPool.FUList5.opList15] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatDiv 351opLat=1 352 353[system.cpu0.fuPool.FUList5.opList16] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatMisc 357opLat=1 358 359[system.cpu0.fuPool.FUList5.opList17] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatMult 363opLat=1 364 365[system.cpu0.fuPool.FUList5.opList18] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatMultAcc 369opLat=1 370 371[system.cpu0.fuPool.FUList5.opList19] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatSqrt 375opLat=1 376 377[system.cpu0.fuPool.FUList6] 378type=FUDesc 379children=opList 380count=0 381opList=system.cpu0.fuPool.FUList6.opList 382 383[system.cpu0.fuPool.FUList6.opList] 384type=OpDesc 385issueLat=1 386opClass=MemWrite 387opLat=1 388 389[system.cpu0.fuPool.FUList7] 390type=FUDesc 391children=opList0 opList1 392count=4 393opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 394 395[system.cpu0.fuPool.FUList7.opList0] 396type=OpDesc 397issueLat=1 398opClass=MemRead 399opLat=1 400 401[system.cpu0.fuPool.FUList7.opList1] 402type=OpDesc 403issueLat=1 404opClass=MemWrite 405opLat=1 406 407[system.cpu0.fuPool.FUList8] 408type=FUDesc 409children=opList 410count=1 411opList=system.cpu0.fuPool.FUList8.opList 412 413[system.cpu0.fuPool.FUList8.opList] 414type=OpDesc 415issueLat=3 416opClass=IprAccess 417opLat=3 418 419[system.cpu0.icache] 420type=BaseCache 421addr_ranges=0:18446744073709551615 422assoc=1 423block_size=64 424forward_snoops=true 425hash_delay=1 426is_top_level=true 427latency=1000 428max_miss_count=0 429mshrs=4 430prefetch_on_access=false 431prefetcher=Null 432prioritizeRequests=false 433repl=Null 434size=32768 435subblock_size=0 436system=system 437tgts_per_mshr=20 438trace_addr=0 439two_queue=false 440write_buffers=8 441cpu_side=system.cpu0.icache_port 442mem_side=system.toL2Bus.slave[0] 443 444[system.cpu0.interrupts] 445type=SparcInterrupts 446 447[system.cpu0.itb] 448type=SparcTLB 449size=64 450 451[system.cpu0.tracer] 452type=ExeTracer 453 454[system.cpu0.workload] 455type=LiveProcess 456cmd=test_atomic 4 457cwd= 458egid=100 459env= 460errout=cerr 461euid=100 462executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic 463gid=100 464input=cin 465max_stack_size=67108864 466output=cout 467pid=100 468ppid=99 469simpoint=0 470system=system 471uid=100 472 473[system.cpu1] 474type=DerivO3CPU 475children=dcache dtb fuPool icache interrupts itb tracer 476BTBEntries=4096 477BTBTagSize=16 478LFSTSize=1024 479LQEntries=32 480LSQCheckLoads=true 481LSQDepCheckShift=4 482RASSize=16 483SQEntries=32 484SSITSize=1024 485activity=0 486backComSize=5 487cachePorts=200 488checker=Null 489choiceCtrBits=2 490choicePredictorSize=8192 491clock=500 492commitToDecodeDelay=1 493commitToFetchDelay=1 494commitToIEWDelay=1 495commitToRenameDelay=1 496commitWidth=8 497cpu_id=1 498decodeToFetchDelay=1 499decodeToRenameDelay=1 500decodeWidth=8 501defer_registration=false 502dispatchWidth=8 503do_checkpoint_insts=true 504do_quiesce=true 505do_statistics_insts=true 506dtb=system.cpu1.dtb 507fetchToDecodeDelay=1 508fetchTrapLatency=1 509fetchWidth=8 510forwardComSize=5 511fuPool=system.cpu1.fuPool 512function_trace=false 513function_trace_start=0 514globalCtrBits=2 515globalHistoryBits=13 516globalPredictorSize=8192 517iewToCommitDelay=1 518iewToDecodeDelay=1 519iewToFetchDelay=1 520iewToRenameDelay=1 521instShiftAmt=2 522interrupts=system.cpu1.interrupts 523issueToExecuteDelay=1 524issueWidth=8 525itb=system.cpu1.itb 526localCtrBits=2 527localHistoryBits=11 528localHistoryTableSize=2048 529localPredictorSize=2048 530max_insts_all_threads=0 531max_insts_any_thread=0 532max_loads_all_threads=0 533max_loads_any_thread=0 534needsTSO=false 535numIQEntries=64 536numPhysFloatRegs=256 537numPhysIntRegs=256 538numROBEntries=192 539numRobs=1 540numThreads=1 541phase=0 542predType=tournament 543profile=0 544progress_interval=0 545renameToDecodeDelay=1 546renameToFetchDelay=1 547renameToIEWDelay=2 548renameToROBDelay=1 549renameWidth=8 550smtCommitPolicy=RoundRobin 551smtFetchPolicy=SingleThread 552smtIQPolicy=Partitioned 553smtIQThreshold=100 554smtLSQPolicy=Partitioned 555smtLSQThreshold=100 556smtNumFetchingThreads=1 557smtROBPolicy=Partitioned 558smtROBThreshold=100 559squashWidth=8 560store_set_clear_period=250000 561system=system 562tracer=system.cpu1.tracer 563trapLatency=13 564wbDepth=1 565wbWidth=8 566workload=system.cpu0.workload 567dcache_port=system.cpu1.dcache.cpu_side 568icache_port=system.cpu1.icache.cpu_side 569 570[system.cpu1.dcache] 571type=BaseCache 572addr_ranges=0:18446744073709551615 573assoc=4 574block_size=64 575forward_snoops=true 576hash_delay=1 577is_top_level=true 578latency=1000 579max_miss_count=0 580mshrs=4 581prefetch_on_access=false 582prefetcher=Null 583prioritizeRequests=false 584repl=Null 585size=32768 586subblock_size=0 587system=system 588tgts_per_mshr=20 589trace_addr=0 590two_queue=false 591write_buffers=8 592cpu_side=system.cpu1.dcache_port 593mem_side=system.toL2Bus.slave[3] 594 595[system.cpu1.dtb] 596type=SparcTLB 597size=64 598 599[system.cpu1.fuPool] 600type=FUPool 601children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 602FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 603 604[system.cpu1.fuPool.FUList0] 605type=FUDesc 606children=opList 607count=6 608opList=system.cpu1.fuPool.FUList0.opList 609 610[system.cpu1.fuPool.FUList0.opList] 611type=OpDesc 612issueLat=1 613opClass=IntAlu 614opLat=1 615 616[system.cpu1.fuPool.FUList1] 617type=FUDesc 618children=opList0 opList1 619count=2 620opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 621 622[system.cpu1.fuPool.FUList1.opList0] 623type=OpDesc 624issueLat=1 625opClass=IntMult 626opLat=3 627 628[system.cpu1.fuPool.FUList1.opList1] 629type=OpDesc 630issueLat=19 631opClass=IntDiv 632opLat=20 633 634[system.cpu1.fuPool.FUList2] 635type=FUDesc 636children=opList0 opList1 opList2 637count=4 638opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 639 640[system.cpu1.fuPool.FUList2.opList0] 641type=OpDesc 642issueLat=1 643opClass=FloatAdd 644opLat=2 645 646[system.cpu1.fuPool.FUList2.opList1] 647type=OpDesc 648issueLat=1 649opClass=FloatCmp 650opLat=2 651 652[system.cpu1.fuPool.FUList2.opList2] 653type=OpDesc 654issueLat=1 655opClass=FloatCvt 656opLat=2 657 658[system.cpu1.fuPool.FUList3] 659type=FUDesc 660children=opList0 opList1 opList2 661count=2 662opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 663 664[system.cpu1.fuPool.FUList3.opList0] 665type=OpDesc 666issueLat=1 667opClass=FloatMult 668opLat=4 669 670[system.cpu1.fuPool.FUList3.opList1] 671type=OpDesc 672issueLat=12 673opClass=FloatDiv 674opLat=12 675 676[system.cpu1.fuPool.FUList3.opList2] 677type=OpDesc 678issueLat=24 679opClass=FloatSqrt 680opLat=24 681 682[system.cpu1.fuPool.FUList4] 683type=FUDesc 684children=opList 685count=0 686opList=system.cpu1.fuPool.FUList4.opList 687 688[system.cpu1.fuPool.FUList4.opList] 689type=OpDesc 690issueLat=1 691opClass=MemRead 692opLat=1 693 694[system.cpu1.fuPool.FUList5] 695type=FUDesc 696children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 697count=4 698opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 699 700[system.cpu1.fuPool.FUList5.opList00] 701type=OpDesc 702issueLat=1 703opClass=SimdAdd 704opLat=1 705 706[system.cpu1.fuPool.FUList5.opList01] 707type=OpDesc 708issueLat=1 709opClass=SimdAddAcc 710opLat=1 711 712[system.cpu1.fuPool.FUList5.opList02] 713type=OpDesc 714issueLat=1 715opClass=SimdAlu 716opLat=1 717 718[system.cpu1.fuPool.FUList5.opList03] 719type=OpDesc 720issueLat=1 721opClass=SimdCmp 722opLat=1 723 724[system.cpu1.fuPool.FUList5.opList04] 725type=OpDesc 726issueLat=1 727opClass=SimdCvt 728opLat=1 729 730[system.cpu1.fuPool.FUList5.opList05] 731type=OpDesc 732issueLat=1 733opClass=SimdMisc 734opLat=1 735 736[system.cpu1.fuPool.FUList5.opList06] 737type=OpDesc 738issueLat=1 739opClass=SimdMult 740opLat=1 741 742[system.cpu1.fuPool.FUList5.opList07] 743type=OpDesc 744issueLat=1 745opClass=SimdMultAcc 746opLat=1 747 748[system.cpu1.fuPool.FUList5.opList08] 749type=OpDesc 750issueLat=1 751opClass=SimdShift 752opLat=1 753 754[system.cpu1.fuPool.FUList5.opList09] 755type=OpDesc 756issueLat=1 757opClass=SimdShiftAcc 758opLat=1 759 760[system.cpu1.fuPool.FUList5.opList10] 761type=OpDesc 762issueLat=1 763opClass=SimdSqrt 764opLat=1 765 766[system.cpu1.fuPool.FUList5.opList11] 767type=OpDesc 768issueLat=1 769opClass=SimdFloatAdd 770opLat=1 771 772[system.cpu1.fuPool.FUList5.opList12] 773type=OpDesc 774issueLat=1 775opClass=SimdFloatAlu 776opLat=1 777 778[system.cpu1.fuPool.FUList5.opList13] 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833type=FUDesc 834children=opList0 opList1 835count=4 836opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 837 838[system.cpu1.fuPool.FUList7.opList0] 839type=OpDesc 840issueLat=1 841opClass=MemRead 842opLat=1 843 844[system.cpu1.fuPool.FUList7.opList1] 845type=OpDesc 846issueLat=1 847opClass=MemWrite 848opLat=1 849 850[system.cpu1.fuPool.FUList8] 851type=FUDesc 852children=opList 853count=1 854opList=system.cpu1.fuPool.FUList8.opList 855 856[system.cpu1.fuPool.FUList8.opList] 857type=OpDesc 858issueLat=3 859opClass=IprAccess 860opLat=3 861 862[system.cpu1.icache] 863type=BaseCache 864addr_ranges=0:18446744073709551615 865assoc=1 866block_size=64 867forward_snoops=true 868hash_delay=1 869is_top_level=true 870latency=1000 871max_miss_count=0 872mshrs=4 873prefetch_on_access=false 874prefetcher=Null 875prioritizeRequests=false 876repl=Null 877size=32768 878subblock_size=0 879system=system 880tgts_per_mshr=20 881trace_addr=0 882two_queue=false 883write_buffers=8 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1355fetchToDecodeDelay=1 1356fetchTrapLatency=1 1357fetchWidth=8 1358forwardComSize=5 1359fuPool=system.cpu3.fuPool 1360function_trace=false 1361function_trace_start=0 1362globalCtrBits=2 1363globalHistoryBits=13 1364globalPredictorSize=8192 1365iewToCommitDelay=1 1366iewToDecodeDelay=1 1367iewToFetchDelay=1 1368iewToRenameDelay=1 1369instShiftAmt=2 1370interrupts=system.cpu3.interrupts 1371issueToExecuteDelay=1 1372issueWidth=8 1373itb=system.cpu3.itb 1374localCtrBits=2 1375localHistoryBits=11 1376localHistoryTableSize=2048 1377localPredictorSize=2048 1378max_insts_all_threads=0 1379max_insts_any_thread=0 1380max_loads_all_threads=0 1381max_loads_any_thread=0 1382needsTSO=false 1383numIQEntries=64 1384numPhysFloatRegs=256 1385numPhysIntRegs=256 1386numROBEntries=192 1387numRobs=1 1388numThreads=1 1389phase=0 1390predType=tournament 1391profile=0 1392progress_interval=0 1393renameToDecodeDelay=1 1394renameToFetchDelay=1 1395renameToIEWDelay=2 1396renameToROBDelay=1 1397renameWidth=8 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system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1547 1548[system.cpu3.fuPool.FUList5.opList00] 1549type=OpDesc 1550issueLat=1 1551opClass=SimdAdd 1552opLat=1 1553 1554[system.cpu3.fuPool.FUList5.opList01] 1555type=OpDesc 1556issueLat=1 1557opClass=SimdAddAcc 1558opLat=1 1559 1560[system.cpu3.fuPool.FUList5.opList02] 1561type=OpDesc 1562issueLat=1 1563opClass=SimdAlu 1564opLat=1 1565 1566[system.cpu3.fuPool.FUList5.opList03] 1567type=OpDesc 1568issueLat=1 1569opClass=SimdCmp 1570opLat=1 1571 1572[system.cpu3.fuPool.FUList5.opList04] 1573type=OpDesc 1574issueLat=1 1575opClass=SimdCvt 1576opLat=1 1577 1578[system.cpu3.fuPool.FUList5.opList05] 1579type=OpDesc 1580issueLat=1 1581opClass=SimdMisc 1582opLat=1 1583 1584[system.cpu3.fuPool.FUList5.opList06] 1585type=OpDesc 1586issueLat=1 1587opClass=SimdMult 1588opLat=1 1589 1590[system.cpu3.fuPool.FUList5.opList07] 1591type=OpDesc 1592issueLat=1 1593opClass=SimdMultAcc 1594opLat=1 1595 1596[system.cpu3.fuPool.FUList5.opList08] 1597type=OpDesc 1598issueLat=1 1599opClass=SimdShift 1600opLat=1 1601 1602[system.cpu3.fuPool.FUList5.opList09] 1603type=OpDesc 1604issueLat=1 1605opClass=SimdShiftAcc 1606opLat=1 1607 1608[system.cpu3.fuPool.FUList5.opList10] 1609type=OpDesc 1610issueLat=1 1611opClass=SimdSqrt 1612opLat=1 1613 1614[system.cpu3.fuPool.FUList5.opList11] 1615type=OpDesc 1616issueLat=1 1617opClass=SimdFloatAdd 1618opLat=1 1619 1620[system.cpu3.fuPool.FUList5.opList12] 1621type=OpDesc 1622issueLat=1 1623opClass=SimdFloatAlu 1624opLat=1 1625 1626[system.cpu3.fuPool.FUList5.opList13] 1627type=OpDesc 1628issueLat=1 1629opClass=SimdFloatCmp 1630opLat=1 1631 1632[system.cpu3.fuPool.FUList5.opList14] 1633type=OpDesc 1634issueLat=1 1635opClass=SimdFloatCvt 1636opLat=1 1637 1638[system.cpu3.fuPool.FUList5.opList15] 1639type=OpDesc 1640issueLat=1 1641opClass=SimdFloatDiv 1642opLat=1 1643 1644[system.cpu3.fuPool.FUList5.opList16] 1645type=OpDesc 1646issueLat=1 1647opClass=SimdFloatMisc 1648opLat=1 1649 1650[system.cpu3.fuPool.FUList5.opList17] 1651type=OpDesc 1652issueLat=1 1653opClass=SimdFloatMult 1654opLat=1 1655 1656[system.cpu3.fuPool.FUList5.opList18] 1657type=OpDesc 1658issueLat=1 1659opClass=SimdFloatMultAcc 1660opLat=1 1661 1662[system.cpu3.fuPool.FUList5.opList19] 1663type=OpDesc 1664issueLat=1 1665opClass=SimdFloatSqrt 1666opLat=1 1667 1668[system.cpu3.fuPool.FUList6] 1669type=FUDesc 1670children=opList 1671count=0 1672opList=system.cpu3.fuPool.FUList6.opList 1673 1674[system.cpu3.fuPool.FUList6.opList] 1675type=OpDesc 1676issueLat=1 1677opClass=MemWrite 1678opLat=1 1679 1680[system.cpu3.fuPool.FUList7] 1681type=FUDesc 1682children=opList0 opList1 1683count=4 1684opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1685 1686[system.cpu3.fuPool.FUList7.opList0] 1687type=OpDesc 1688issueLat=1 1689opClass=MemRead 1690opLat=1 1691 1692[system.cpu3.fuPool.FUList7.opList1] 1693type=OpDesc 1694issueLat=1 1695opClass=MemWrite 1696opLat=1 1697 1698[system.cpu3.fuPool.FUList8] 1699type=FUDesc 1700children=opList 1701count=1 1702opList=system.cpu3.fuPool.FUList8.opList 1703 1704[system.cpu3.fuPool.FUList8.opList] 1705type=OpDesc 1706issueLat=3 1707opClass=IprAccess 1708opLat=3 1709 1710[system.cpu3.icache] 1711type=BaseCache 1712addr_ranges=0:18446744073709551615 1713assoc=1 1714block_size=64 1715forward_snoops=true 1716hash_delay=1 1717is_top_level=true 1718latency=1000 1719max_miss_count=0 1720mshrs=4 1721prefetch_on_access=false 1722prefetcher=Null 1723prioritizeRequests=false 1724repl=Null 1725size=32768 1726subblock_size=0 1727system=system 1728tgts_per_mshr=20 1729trace_addr=0 1730two_queue=false 1731write_buffers=8 1732cpu_side=system.cpu3.icache_port 1733mem_side=system.toL2Bus.slave[6] 1734 1735[system.cpu3.interrupts] 1736type=SparcInterrupts 1737 1738[system.cpu3.itb] 1739type=SparcTLB 1740size=64 1741 1742[system.cpu3.tracer] 1743type=ExeTracer 1744 1745[system.l2c] 1746type=BaseCache 1747addr_ranges=0:18446744073709551615 1748assoc=8 1749block_size=64 1750forward_snoops=true 1751hash_delay=1 1752is_top_level=false 1753latency=10000 1754max_miss_count=0 1755mshrs=92 1756prefetch_on_access=false 1757prefetcher=Null 1758prioritizeRequests=false 1759repl=Null 1760size=4194304 1761subblock_size=0 1762system=system 1763tgts_per_mshr=16 1764trace_addr=0 1765two_queue=false 1766write_buffers=8 1767cpu_side=system.toL2Bus.master[0] 1768mem_side=system.membus.slave[0] 1769 1770[system.membus] 1771type=CoherentBus 1772block_size=64 1773clock=1000 1774header_cycles=1 1775use_default_range=false 1776width=64 1777master=system.physmem.port[0] 1778slave=system.l2c.mem_side system.system_port 1779 1780[system.physmem] 1781type=SimpleMemory 1782conf_table_reported=false 1783file= 1784in_addr_map=true 1785latency=30000 1786latency_var=0 1787null=false 1788range=0:134217727 1789zero=false 1790port=system.membus.master[0] 1791 1792[system.toL2Bus] 1793type=CoherentBus 1794block_size=64 1795clock=1000 1796header_cycles=1 1797use_default_range=false 1798width=64 1799master=system.l2c.cpu_side 1800slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1801 1802