1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu0] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu0.branchPred 68cacheStorePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu0.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu0.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu0.interrupts 101isa=system.cpu0.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu0.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=1 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false 142syscallRetryLatency=10000 143system=system 144tracer=system.cpu0.tracer 145trapLatency=13 146wbWidth=8 147workload=system.cpu0.workload 148dcache_port=system.cpu0.dcache.cpu_side 149icache_port=system.cpu0.icache.cpu_side 150 151[system.cpu0.branchPred] 152type=TournamentBP 153BTBEntries=4096 154BTBTagSize=16 155RASSize=16 156choiceCtrBits=2 157choicePredictorSize=8192 158eventq_index=0 159globalCtrBits=2 160globalPredictorSize=8192 161indirectHashGHR=true 162indirectHashTargets=true 163indirectPathLength=3 164indirectSets=256 165indirectTagSize=16 166indirectWays=2 167instShiftAmt=2 168localCtrBits=2 169localHistoryTableSize=2048 170localPredictorSize=2048 171numThreads=1 172useIndirect=true 173 174[system.cpu0.dcache] 175type=Cache 176children=tags 177addr_ranges=0:18446744073709551615:0:0:0:0 178assoc=4 179clk_domain=system.cpu_clk_domain 180clusivity=mostly_incl 181data_latency=2 182default_p_state=UNDEFINED 183demand_mshr_reserve=1 184eventq_index=0 185is_read_only=false 186max_miss_count=0 187mshrs=4 188p_state_clk_gate_bins=20 189p_state_clk_gate_max=1000000000000 190p_state_clk_gate_min=1000 191power_model=Null 192prefetch_on_access=false 193prefetcher=Null 194response_latency=2 195sequential_access=false 196size=32768 197system=system 198tag_latency=2 199tags=system.cpu0.dcache.tags 200tgts_per_mshr=20 201write_buffers=8 202writeback_clean=false 203cpu_side=system.cpu0.dcache_port 204mem_side=system.toL2Bus.slave[1] 205 206[system.cpu0.dcache.tags] 207type=LRU 208assoc=4 209block_size=64 210clk_domain=system.cpu_clk_domain 211data_latency=2 212default_p_state=UNDEFINED 213eventq_index=0 214p_state_clk_gate_bins=20 215p_state_clk_gate_max=1000000000000 216p_state_clk_gate_min=1000 217power_model=Null 218sequential_access=false 219size=32768 220tag_latency=2 221 222[system.cpu0.dtb] 223type=SparcTLB 224eventq_index=0 225size=64 226 227[system.cpu0.fuPool] 228type=FUPool 229children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 230FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 231eventq_index=0 232 233[system.cpu0.fuPool.FUList0] 234type=FUDesc 235children=opList 236count=6 237eventq_index=0 238opList=system.cpu0.fuPool.FUList0.opList 239 240[system.cpu0.fuPool.FUList0.opList] 241type=OpDesc 242eventq_index=0 243opClass=IntAlu 244opLat=1 245pipelined=true 246 247[system.cpu0.fuPool.FUList1] 248type=FUDesc 249children=opList0 opList1 250count=2 251eventq_index=0 252opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 253 254[system.cpu0.fuPool.FUList1.opList0] 255type=OpDesc 256eventq_index=0 257opClass=IntMult 258opLat=3 259pipelined=true 260 261[system.cpu0.fuPool.FUList1.opList1] 262type=OpDesc 263eventq_index=0 264opClass=IntDiv 265opLat=20 266pipelined=false 267 268[system.cpu0.fuPool.FUList2] 269type=FUDesc 270children=opList0 opList1 opList2 271count=4 272eventq_index=0 273opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 274 275[system.cpu0.fuPool.FUList2.opList0] 276type=OpDesc 277eventq_index=0 278opClass=FloatAdd 279opLat=2 280pipelined=true 281 282[system.cpu0.fuPool.FUList2.opList1] 283type=OpDesc 284eventq_index=0 285opClass=FloatCmp 286opLat=2 287pipelined=true 288 289[system.cpu0.fuPool.FUList2.opList2] 290type=OpDesc 291eventq_index=0 292opClass=FloatCvt 293opLat=2 294pipelined=true 295 296[system.cpu0.fuPool.FUList3] 297type=FUDesc 298children=opList0 opList1 opList2 opList3 opList4 299count=2 300eventq_index=0 301opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 system.cpu0.fuPool.FUList3.opList3 system.cpu0.fuPool.FUList3.opList4 302 303[system.cpu0.fuPool.FUList3.opList0] 304type=OpDesc 305eventq_index=0 306opClass=FloatMult 307opLat=4 308pipelined=true 309 310[system.cpu0.fuPool.FUList3.opList1] 311type=OpDesc 312eventq_index=0 313opClass=FloatMultAcc 314opLat=5 315pipelined=true 316 317[system.cpu0.fuPool.FUList3.opList2] 318type=OpDesc 319eventq_index=0 320opClass=FloatMisc 321opLat=3 322pipelined=true 323 324[system.cpu0.fuPool.FUList3.opList3] 325type=OpDesc 326eventq_index=0 327opClass=FloatDiv 328opLat=12 329pipelined=false 330 331[system.cpu0.fuPool.FUList3.opList4] 332type=OpDesc 333eventq_index=0 334opClass=FloatSqrt 335opLat=24 336pipelined=false 337 338[system.cpu0.fuPool.FUList4] 339type=FUDesc 340children=opList0 opList1 341count=0 342eventq_index=0 343opList=system.cpu0.fuPool.FUList4.opList0 system.cpu0.fuPool.FUList4.opList1 344 345[system.cpu0.fuPool.FUList4.opList0] 346type=OpDesc 347eventq_index=0 348opClass=MemRead 349opLat=1 350pipelined=true 351 352[system.cpu0.fuPool.FUList4.opList1] 353type=OpDesc 354eventq_index=0 355opClass=FloatMemRead 356opLat=1 357pipelined=true 358 359[system.cpu0.fuPool.FUList5] 360type=FUDesc 361children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 362count=4 363eventq_index=0 364opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 365 366[system.cpu0.fuPool.FUList5.opList00] 367type=OpDesc 368eventq_index=0 369opClass=SimdAdd 370opLat=1 371pipelined=true 372 373[system.cpu0.fuPool.FUList5.opList01] 374type=OpDesc 375eventq_index=0 376opClass=SimdAddAcc 377opLat=1 378pipelined=true 379 380[system.cpu0.fuPool.FUList5.opList02] 381type=OpDesc 382eventq_index=0 383opClass=SimdAlu 384opLat=1 385pipelined=true 386 387[system.cpu0.fuPool.FUList5.opList03] 388type=OpDesc 389eventq_index=0 390opClass=SimdCmp 391opLat=1 392pipelined=true 393 394[system.cpu0.fuPool.FUList5.opList04] 395type=OpDesc 396eventq_index=0 397opClass=SimdCvt 398opLat=1 399pipelined=true 400 401[system.cpu0.fuPool.FUList5.opList05] 402type=OpDesc 403eventq_index=0 404opClass=SimdMisc 405opLat=1 406pipelined=true 407 408[system.cpu0.fuPool.FUList5.opList06] 409type=OpDesc 410eventq_index=0 411opClass=SimdMult 412opLat=1 413pipelined=true 414 415[system.cpu0.fuPool.FUList5.opList07] 416type=OpDesc 417eventq_index=0 418opClass=SimdMultAcc 419opLat=1 420pipelined=true 421 422[system.cpu0.fuPool.FUList5.opList08] 423type=OpDesc 424eventq_index=0 425opClass=SimdShift 426opLat=1 427pipelined=true 428 429[system.cpu0.fuPool.FUList5.opList09] 430type=OpDesc 431eventq_index=0 432opClass=SimdShiftAcc 433opLat=1 434pipelined=true 435 436[system.cpu0.fuPool.FUList5.opList10] 437type=OpDesc 438eventq_index=0 439opClass=SimdSqrt 440opLat=1 441pipelined=true 442 443[system.cpu0.fuPool.FUList5.opList11] 444type=OpDesc 445eventq_index=0 446opClass=SimdFloatAdd 447opLat=1 448pipelined=true 449 450[system.cpu0.fuPool.FUList5.opList12] 451type=OpDesc 452eventq_index=0 453opClass=SimdFloatAlu 454opLat=1 455pipelined=true 456 457[system.cpu0.fuPool.FUList5.opList13] 458type=OpDesc 459eventq_index=0 460opClass=SimdFloatCmp 461opLat=1 462pipelined=true 463 464[system.cpu0.fuPool.FUList5.opList14] 465type=OpDesc 466eventq_index=0 467opClass=SimdFloatCvt 468opLat=1 469pipelined=true 470 471[system.cpu0.fuPool.FUList5.opList15] 472type=OpDesc 473eventq_index=0 474opClass=SimdFloatDiv 475opLat=1 476pipelined=true 477 478[system.cpu0.fuPool.FUList5.opList16] 479type=OpDesc 480eventq_index=0 481opClass=SimdFloatMisc 482opLat=1 483pipelined=true 484 485[system.cpu0.fuPool.FUList5.opList17] 486type=OpDesc 487eventq_index=0 488opClass=SimdFloatMult 489opLat=1 490pipelined=true 491 492[system.cpu0.fuPool.FUList5.opList18] 493type=OpDesc 494eventq_index=0 495opClass=SimdFloatMultAcc 496opLat=1 497pipelined=true 498 499[system.cpu0.fuPool.FUList5.opList19] 500type=OpDesc 501eventq_index=0 502opClass=SimdFloatSqrt 503opLat=1 504pipelined=true 505 506[system.cpu0.fuPool.FUList6] 507type=FUDesc 508children=opList0 opList1 509count=0 510eventq_index=0 511opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 512 513[system.cpu0.fuPool.FUList6.opList0] 514type=OpDesc 515eventq_index=0 516opClass=MemWrite 517opLat=1 518pipelined=true 519 520[system.cpu0.fuPool.FUList6.opList1] 521type=OpDesc 522eventq_index=0 523opClass=FloatMemWrite 524opLat=1 525pipelined=true 526 527[system.cpu0.fuPool.FUList7] 528type=FUDesc 529children=opList0 opList1 opList2 opList3 530count=4 531eventq_index=0 532opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 system.cpu0.fuPool.FUList7.opList2 system.cpu0.fuPool.FUList7.opList3 533 534[system.cpu0.fuPool.FUList7.opList0] 535type=OpDesc 536eventq_index=0 537opClass=MemRead 538opLat=1 539pipelined=true 540 541[system.cpu0.fuPool.FUList7.opList1] 542type=OpDesc 543eventq_index=0 544opClass=MemWrite 545opLat=1 546pipelined=true 547 548[system.cpu0.fuPool.FUList7.opList2] 549type=OpDesc 550eventq_index=0 551opClass=FloatMemRead 552opLat=1 553pipelined=true 554 555[system.cpu0.fuPool.FUList7.opList3] 556type=OpDesc 557eventq_index=0 558opClass=FloatMemWrite 559opLat=1 560pipelined=true 561 562[system.cpu0.fuPool.FUList8] 563type=FUDesc 564children=opList 565count=1 566eventq_index=0 567opList=system.cpu0.fuPool.FUList8.opList 568 569[system.cpu0.fuPool.FUList8.opList] 570type=OpDesc 571eventq_index=0 572opClass=IprAccess 573opLat=3 574pipelined=false 575 576[system.cpu0.icache] 577type=Cache 578children=tags 579addr_ranges=0:18446744073709551615:0:0:0:0 580assoc=1 581clk_domain=system.cpu_clk_domain 582clusivity=mostly_incl 583data_latency=2 584default_p_state=UNDEFINED 585demand_mshr_reserve=1 586eventq_index=0 587is_read_only=true 588max_miss_count=0 589mshrs=4 590p_state_clk_gate_bins=20 591p_state_clk_gate_max=1000000000000 592p_state_clk_gate_min=1000 593power_model=Null 594prefetch_on_access=false 595prefetcher=Null 596response_latency=2 597sequential_access=false 598size=32768 599system=system 600tag_latency=2 601tags=system.cpu0.icache.tags 602tgts_per_mshr=20 603write_buffers=8 604writeback_clean=true 605cpu_side=system.cpu0.icache_port 606mem_side=system.toL2Bus.slave[0] 607 608[system.cpu0.icache.tags] 609type=LRU 610assoc=1 611block_size=64 612clk_domain=system.cpu_clk_domain 613data_latency=2 614default_p_state=UNDEFINED 615eventq_index=0 616p_state_clk_gate_bins=20 617p_state_clk_gate_max=1000000000000 618p_state_clk_gate_min=1000 619power_model=Null 620sequential_access=false 621size=32768 622tag_latency=2 623 624[system.cpu0.interrupts] 625type=SparcInterrupts 626eventq_index=0 627 628[system.cpu0.isa] 629type=SparcISA 630eventq_index=0 631 632[system.cpu0.itb] 633type=SparcTLB 634eventq_index=0 635size=64 636 637[system.cpu0.tracer] 638type=ExeTracer 639eventq_index=0 640 641[system.cpu0.workload] 642type=Process 643cmd=test_atomic 4 644cwd= 645drivers= 646egid=100 647env= 648errout=cerr 649euid=100 650eventq_index=0 651executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic 652gid=100 653input=cin 654kvmInSE=false 655maxStackSize=67108864 656output=cout 657pgid=100 658pid=100 659ppid=0 660simpoint=0 661system=system 662uid=100 663useArchPT=false 664 665[system.cpu1] 666type=DerivO3CPU 667children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 668LFSTSize=1024 669LQEntries=32 670LSQCheckLoads=true 671LSQDepCheckShift=4 672SQEntries=32 673SSITSize=1024 674activity=0 675backComSize=5 676branchPred=system.cpu1.branchPred 677cacheStorePorts=200 678checker=Null 679clk_domain=system.cpu_clk_domain 680commitToDecodeDelay=1 681commitToFetchDelay=1 682commitToIEWDelay=1 683commitToRenameDelay=1 684commitWidth=8 685cpu_id=1 686decodeToFetchDelay=1 687decodeToRenameDelay=1 688decodeWidth=8 689default_p_state=UNDEFINED 690dispatchWidth=8 691do_checkpoint_insts=true 692do_quiesce=true 693do_statistics_insts=true 694dtb=system.cpu1.dtb 695eventq_index=0 696fetchBufferSize=64 697fetchQueueSize=32 698fetchToDecodeDelay=1 699fetchTrapLatency=1 700fetchWidth=8 701forwardComSize=5 702fuPool=system.cpu1.fuPool 703function_trace=false 704function_trace_start=0 705iewToCommitDelay=1 706iewToDecodeDelay=1 707iewToFetchDelay=1 708iewToRenameDelay=1 709interrupts=system.cpu1.interrupts 710isa=system.cpu1.isa 711issueToExecuteDelay=1 712issueWidth=8 713itb=system.cpu1.itb 714max_insts_all_threads=0 715max_insts_any_thread=0 716max_loads_all_threads=0 717max_loads_any_thread=0 718needsTSO=false 719numIQEntries=64 720numPhysCCRegs=0 721numPhysFloatRegs=256 722numPhysIntRegs=256 723numROBEntries=192 724numRobs=1 725numThreads=1 726p_state_clk_gate_bins=20 727p_state_clk_gate_max=1000000000000 728p_state_clk_gate_min=1000 729power_model=Null 730profile=0 731progress_interval=0 732renameToDecodeDelay=1 733renameToFetchDelay=1 734renameToIEWDelay=2 735renameToROBDelay=1 736renameWidth=8 737simpoint_start_insts= 738smtCommitPolicy=RoundRobin 739smtFetchPolicy=SingleThread 740smtIQPolicy=Partitioned 741smtIQThreshold=100 742smtLSQPolicy=Partitioned 743smtLSQThreshold=100 744smtNumFetchingThreads=1 745smtROBPolicy=Partitioned 746smtROBThreshold=100 747socket_id=0 748squashWidth=8 749store_set_clear_period=250000 750switched_out=false 751syscallRetryLatency=10000 752system=system 753tracer=system.cpu1.tracer 754trapLatency=13 755wbWidth=8 756workload=system.cpu0.workload 757dcache_port=system.cpu1.dcache.cpu_side 758icache_port=system.cpu1.icache.cpu_side 759 760[system.cpu1.branchPred] 761type=TournamentBP 762BTBEntries=4096 763BTBTagSize=16 764RASSize=16 765choiceCtrBits=2 766choicePredictorSize=8192 767eventq_index=0 768globalCtrBits=2 769globalPredictorSize=8192 770indirectHashGHR=true 771indirectHashTargets=true 772indirectPathLength=3 773indirectSets=256 774indirectTagSize=16 775indirectWays=2 776instShiftAmt=2 777localCtrBits=2 778localHistoryTableSize=2048 779localPredictorSize=2048 780numThreads=1 781useIndirect=true 782 783[system.cpu1.dcache] 784type=Cache 785children=tags 786addr_ranges=0:18446744073709551615:0:0:0:0 787assoc=4 788clk_domain=system.cpu_clk_domain 789clusivity=mostly_incl 790data_latency=2 791default_p_state=UNDEFINED 792demand_mshr_reserve=1 793eventq_index=0 794is_read_only=false 795max_miss_count=0 796mshrs=4 797p_state_clk_gate_bins=20 798p_state_clk_gate_max=1000000000000 799p_state_clk_gate_min=1000 800power_model=Null 801prefetch_on_access=false 802prefetcher=Null 803response_latency=2 804sequential_access=false 805size=32768 806system=system 807tag_latency=2 808tags=system.cpu1.dcache.tags 809tgts_per_mshr=20 810write_buffers=8 811writeback_clean=false 812cpu_side=system.cpu1.dcache_port 813mem_side=system.toL2Bus.slave[3] 814 815[system.cpu1.dcache.tags] 816type=LRU 817assoc=4 818block_size=64 819clk_domain=system.cpu_clk_domain 820data_latency=2 821default_p_state=UNDEFINED 822eventq_index=0 823p_state_clk_gate_bins=20 824p_state_clk_gate_max=1000000000000 825p_state_clk_gate_min=1000 826power_model=Null 827sequential_access=false 828size=32768 829tag_latency=2 830 831[system.cpu1.dtb] 832type=SparcTLB 833eventq_index=0 834size=64 835 836[system.cpu1.fuPool] 837type=FUPool 838children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 839FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 840eventq_index=0 841 842[system.cpu1.fuPool.FUList0] 843type=FUDesc 844children=opList 845count=6 846eventq_index=0 847opList=system.cpu1.fuPool.FUList0.opList 848 849[system.cpu1.fuPool.FUList0.opList] 850type=OpDesc 851eventq_index=0 852opClass=IntAlu 853opLat=1 854pipelined=true 855 856[system.cpu1.fuPool.FUList1] 857type=FUDesc 858children=opList0 opList1 859count=2 860eventq_index=0 861opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 862 863[system.cpu1.fuPool.FUList1.opList0] 864type=OpDesc 865eventq_index=0 866opClass=IntMult 867opLat=3 868pipelined=true 869 870[system.cpu1.fuPool.FUList1.opList1] 871type=OpDesc 872eventq_index=0 873opClass=IntDiv 874opLat=20 875pipelined=false 876 877[system.cpu1.fuPool.FUList2] 878type=FUDesc 879children=opList0 opList1 opList2 880count=4 881eventq_index=0 882opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 883 884[system.cpu1.fuPool.FUList2.opList0] 885type=OpDesc 886eventq_index=0 887opClass=FloatAdd 888opLat=2 889pipelined=true 890 891[system.cpu1.fuPool.FUList2.opList1] 892type=OpDesc 893eventq_index=0 894opClass=FloatCmp 895opLat=2 896pipelined=true 897 898[system.cpu1.fuPool.FUList2.opList2] 899type=OpDesc 900eventq_index=0 901opClass=FloatCvt 902opLat=2 903pipelined=true 904 905[system.cpu1.fuPool.FUList3] 906type=FUDesc 907children=opList0 opList1 opList2 opList3 opList4 908count=2 909eventq_index=0 910opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 system.cpu1.fuPool.FUList3.opList3 system.cpu1.fuPool.FUList3.opList4 911 912[system.cpu1.fuPool.FUList3.opList0] 913type=OpDesc 914eventq_index=0 915opClass=FloatMult 916opLat=4 917pipelined=true 918 919[system.cpu1.fuPool.FUList3.opList1] 920type=OpDesc 921eventq_index=0 922opClass=FloatMultAcc 923opLat=5 924pipelined=true 925 926[system.cpu1.fuPool.FUList3.opList2] 927type=OpDesc 928eventq_index=0 929opClass=FloatMisc 930opLat=3 931pipelined=true 932 933[system.cpu1.fuPool.FUList3.opList3] 934type=OpDesc 935eventq_index=0 936opClass=FloatDiv 937opLat=12 938pipelined=false 939 940[system.cpu1.fuPool.FUList3.opList4] 941type=OpDesc 942eventq_index=0 943opClass=FloatSqrt 944opLat=24 945pipelined=false 946 947[system.cpu1.fuPool.FUList4] 948type=FUDesc 949children=opList0 opList1 950count=0 951eventq_index=0 952opList=system.cpu1.fuPool.FUList4.opList0 system.cpu1.fuPool.FUList4.opList1 953 954[system.cpu1.fuPool.FUList4.opList0] 955type=OpDesc 956eventq_index=0 957opClass=MemRead 958opLat=1 959pipelined=true 960 961[system.cpu1.fuPool.FUList4.opList1] 962type=OpDesc 963eventq_index=0 964opClass=FloatMemRead 965opLat=1 966pipelined=true 967 968[system.cpu1.fuPool.FUList5] 969type=FUDesc 970children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 971count=4 972eventq_index=0 973opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 974 975[system.cpu1.fuPool.FUList5.opList00] 976type=OpDesc 977eventq_index=0 978opClass=SimdAdd 979opLat=1 980pipelined=true 981 982[system.cpu1.fuPool.FUList5.opList01] 983type=OpDesc 984eventq_index=0 985opClass=SimdAddAcc 986opLat=1 987pipelined=true 988 989[system.cpu1.fuPool.FUList5.opList02] 990type=OpDesc 991eventq_index=0 992opClass=SimdAlu 993opLat=1 994pipelined=true 995 996[system.cpu1.fuPool.FUList5.opList03] 997type=OpDesc 998eventq_index=0 999opClass=SimdCmp 1000opLat=1 1001pipelined=true 1002 1003[system.cpu1.fuPool.FUList5.opList04] 1004type=OpDesc 1005eventq_index=0 1006opClass=SimdCvt 1007opLat=1 1008pipelined=true 1009 1010[system.cpu1.fuPool.FUList5.opList05] 1011type=OpDesc 1012eventq_index=0 1013opClass=SimdMisc 1014opLat=1 1015pipelined=true 1016 1017[system.cpu1.fuPool.FUList5.opList06] 1018type=OpDesc 1019eventq_index=0 1020opClass=SimdMult 1021opLat=1 1022pipelined=true 1023 1024[system.cpu1.fuPool.FUList5.opList07] 1025type=OpDesc 1026eventq_index=0 1027opClass=SimdMultAcc 1028opLat=1 1029pipelined=true 1030 1031[system.cpu1.fuPool.FUList5.opList08] 1032type=OpDesc 1033eventq_index=0 1034opClass=SimdShift 1035opLat=1 1036pipelined=true 1037 1038[system.cpu1.fuPool.FUList5.opList09] 1039type=OpDesc 1040eventq_index=0 1041opClass=SimdShiftAcc 1042opLat=1 1043pipelined=true 1044 1045[system.cpu1.fuPool.FUList5.opList10] 1046type=OpDesc 1047eventq_index=0 1048opClass=SimdSqrt 1049opLat=1 1050pipelined=true 1051 1052[system.cpu1.fuPool.FUList5.opList11] 1053type=OpDesc 1054eventq_index=0 1055opClass=SimdFloatAdd 1056opLat=1 1057pipelined=true 1058 1059[system.cpu1.fuPool.FUList5.opList12] 1060type=OpDesc 1061eventq_index=0 1062opClass=SimdFloatAlu 1063opLat=1 1064pipelined=true 1065 1066[system.cpu1.fuPool.FUList5.opList13] 1067type=OpDesc 1068eventq_index=0 1069opClass=SimdFloatCmp 1070opLat=1 1071pipelined=true 1072 1073[system.cpu1.fuPool.FUList5.opList14] 1074type=OpDesc 1075eventq_index=0 1076opClass=SimdFloatCvt 1077opLat=1 1078pipelined=true 1079 1080[system.cpu1.fuPool.FUList5.opList15] 1081type=OpDesc 1082eventq_index=0 1083opClass=SimdFloatDiv 1084opLat=1 1085pipelined=true 1086 1087[system.cpu1.fuPool.FUList5.opList16] 1088type=OpDesc 1089eventq_index=0 1090opClass=SimdFloatMisc 1091opLat=1 1092pipelined=true 1093 1094[system.cpu1.fuPool.FUList5.opList17] 1095type=OpDesc 1096eventq_index=0 1097opClass=SimdFloatMult 1098opLat=1 1099pipelined=true 1100 1101[system.cpu1.fuPool.FUList5.opList18] 1102type=OpDesc 1103eventq_index=0 1104opClass=SimdFloatMultAcc 1105opLat=1 1106pipelined=true 1107 1108[system.cpu1.fuPool.FUList5.opList19] 1109type=OpDesc 1110eventq_index=0 1111opClass=SimdFloatSqrt 1112opLat=1 1113pipelined=true 1114 1115[system.cpu1.fuPool.FUList6] 1116type=FUDesc 1117children=opList0 opList1 1118count=0 1119eventq_index=0 1120opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1 1121 1122[system.cpu1.fuPool.FUList6.opList0] 1123type=OpDesc 1124eventq_index=0 1125opClass=MemWrite 1126opLat=1 1127pipelined=true 1128 1129[system.cpu1.fuPool.FUList6.opList1] 1130type=OpDesc 1131eventq_index=0 1132opClass=FloatMemWrite 1133opLat=1 1134pipelined=true 1135 1136[system.cpu1.fuPool.FUList7] 1137type=FUDesc 1138children=opList0 opList1 opList2 opList3 1139count=4 1140eventq_index=0 1141opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 system.cpu1.fuPool.FUList7.opList2 system.cpu1.fuPool.FUList7.opList3 1142 1143[system.cpu1.fuPool.FUList7.opList0] 1144type=OpDesc 1145eventq_index=0 1146opClass=MemRead 1147opLat=1 1148pipelined=true 1149 1150[system.cpu1.fuPool.FUList7.opList1] 1151type=OpDesc 1152eventq_index=0 1153opClass=MemWrite 1154opLat=1 1155pipelined=true 1156 1157[system.cpu1.fuPool.FUList7.opList2] 1158type=OpDesc 1159eventq_index=0 1160opClass=FloatMemRead 1161opLat=1 1162pipelined=true 1163 1164[system.cpu1.fuPool.FUList7.opList3] 1165type=OpDesc 1166eventq_index=0 1167opClass=FloatMemWrite 1168opLat=1 1169pipelined=true 1170 1171[system.cpu1.fuPool.FUList8] 1172type=FUDesc 1173children=opList 1174count=1 1175eventq_index=0 1176opList=system.cpu1.fuPool.FUList8.opList 1177 1178[system.cpu1.fuPool.FUList8.opList] 1179type=OpDesc 1180eventq_index=0 1181opClass=IprAccess 1182opLat=3 1183pipelined=false 1184 1185[system.cpu1.icache] 1186type=Cache 1187children=tags 1188addr_ranges=0:18446744073709551615:0:0:0:0 1189assoc=1 1190clk_domain=system.cpu_clk_domain 1191clusivity=mostly_incl 1192data_latency=2 1193default_p_state=UNDEFINED 1194demand_mshr_reserve=1 1195eventq_index=0 1196is_read_only=true 1197max_miss_count=0 1198mshrs=4 1199p_state_clk_gate_bins=20 1200p_state_clk_gate_max=1000000000000 1201p_state_clk_gate_min=1000 1202power_model=Null 1203prefetch_on_access=false 1204prefetcher=Null 1205response_latency=2 1206sequential_access=false 1207size=32768 1208system=system 1209tag_latency=2 1210tags=system.cpu1.icache.tags 1211tgts_per_mshr=20 1212write_buffers=8 1213writeback_clean=true 1214cpu_side=system.cpu1.icache_port 1215mem_side=system.toL2Bus.slave[2] 1216 1217[system.cpu1.icache.tags] 1218type=LRU 1219assoc=1 1220block_size=64 1221clk_domain=system.cpu_clk_domain 1222data_latency=2 1223default_p_state=UNDEFINED 1224eventq_index=0 1225p_state_clk_gate_bins=20 1226p_state_clk_gate_max=1000000000000 1227p_state_clk_gate_min=1000 1228power_model=Null 1229sequential_access=false 1230size=32768 1231tag_latency=2 1232 1233[system.cpu1.interrupts] 1234type=SparcInterrupts 1235eventq_index=0 1236 1237[system.cpu1.isa] 1238type=SparcISA 1239eventq_index=0 1240 1241[system.cpu1.itb] 1242type=SparcTLB 1243eventq_index=0 1244size=64 1245 1246[system.cpu1.tracer] 1247type=ExeTracer 1248eventq_index=0 1249 1250[system.cpu2] 1251type=DerivO3CPU 1252children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1253LFSTSize=1024 1254LQEntries=32 1255LSQCheckLoads=true 1256LSQDepCheckShift=4 1257SQEntries=32 1258SSITSize=1024 1259activity=0 1260backComSize=5 1261branchPred=system.cpu2.branchPred 1262cacheStorePorts=200 1263checker=Null 1264clk_domain=system.cpu_clk_domain 1265commitToDecodeDelay=1 1266commitToFetchDelay=1 1267commitToIEWDelay=1 1268commitToRenameDelay=1 1269commitWidth=8 1270cpu_id=2 1271decodeToFetchDelay=1 1272decodeToRenameDelay=1 1273decodeWidth=8 1274default_p_state=UNDEFINED 1275dispatchWidth=8 1276do_checkpoint_insts=true 1277do_quiesce=true 1278do_statistics_insts=true 1279dtb=system.cpu2.dtb 1280eventq_index=0 1281fetchBufferSize=64 1282fetchQueueSize=32 1283fetchToDecodeDelay=1 1284fetchTrapLatency=1 1285fetchWidth=8 1286forwardComSize=5 1287fuPool=system.cpu2.fuPool 1288function_trace=false 1289function_trace_start=0 1290iewToCommitDelay=1 1291iewToDecodeDelay=1 1292iewToFetchDelay=1 1293iewToRenameDelay=1 1294interrupts=system.cpu2.interrupts 1295isa=system.cpu2.isa 1296issueToExecuteDelay=1 1297issueWidth=8 1298itb=system.cpu2.itb 1299max_insts_all_threads=0 1300max_insts_any_thread=0 1301max_loads_all_threads=0 1302max_loads_any_thread=0 1303needsTSO=false 1304numIQEntries=64 1305numPhysCCRegs=0 1306numPhysFloatRegs=256 1307numPhysIntRegs=256 1308numROBEntries=192 1309numRobs=1 1310numThreads=1 1311p_state_clk_gate_bins=20 1312p_state_clk_gate_max=1000000000000 1313p_state_clk_gate_min=1000 1314power_model=Null 1315profile=0 1316progress_interval=0 1317renameToDecodeDelay=1 1318renameToFetchDelay=1 1319renameToIEWDelay=2 1320renameToROBDelay=1 1321renameWidth=8 1322simpoint_start_insts= 1323smtCommitPolicy=RoundRobin 1324smtFetchPolicy=SingleThread 1325smtIQPolicy=Partitioned 1326smtIQThreshold=100 1327smtLSQPolicy=Partitioned 1328smtLSQThreshold=100 1329smtNumFetchingThreads=1 1330smtROBPolicy=Partitioned 1331smtROBThreshold=100 1332socket_id=0 1333squashWidth=8 1334store_set_clear_period=250000 1335switched_out=false 1336syscallRetryLatency=10000 1337system=system 1338tracer=system.cpu2.tracer 1339trapLatency=13 1340wbWidth=8 1341workload=system.cpu0.workload 1342dcache_port=system.cpu2.dcache.cpu_side 1343icache_port=system.cpu2.icache.cpu_side 1344 1345[system.cpu2.branchPred] 1346type=TournamentBP 1347BTBEntries=4096 1348BTBTagSize=16 1349RASSize=16 1350choiceCtrBits=2 1351choicePredictorSize=8192 1352eventq_index=0 1353globalCtrBits=2 1354globalPredictorSize=8192 1355indirectHashGHR=true 1356indirectHashTargets=true 1357indirectPathLength=3 1358indirectSets=256 1359indirectTagSize=16 1360indirectWays=2 1361instShiftAmt=2 1362localCtrBits=2 1363localHistoryTableSize=2048 1364localPredictorSize=2048 1365numThreads=1 1366useIndirect=true 1367 1368[system.cpu2.dcache] 1369type=Cache 1370children=tags 1371addr_ranges=0:18446744073709551615:0:0:0:0 1372assoc=4 1373clk_domain=system.cpu_clk_domain 1374clusivity=mostly_incl 1375data_latency=2 1376default_p_state=UNDEFINED 1377demand_mshr_reserve=1 1378eventq_index=0 1379is_read_only=false 1380max_miss_count=0 1381mshrs=4 1382p_state_clk_gate_bins=20 1383p_state_clk_gate_max=1000000000000 1384p_state_clk_gate_min=1000 1385power_model=Null 1386prefetch_on_access=false 1387prefetcher=Null 1388response_latency=2 1389sequential_access=false 1390size=32768 1391system=system 1392tag_latency=2 1393tags=system.cpu2.dcache.tags 1394tgts_per_mshr=20 1395write_buffers=8 1396writeback_clean=false 1397cpu_side=system.cpu2.dcache_port 1398mem_side=system.toL2Bus.slave[5] 1399 1400[system.cpu2.dcache.tags] 1401type=LRU 1402assoc=4 1403block_size=64 1404clk_domain=system.cpu_clk_domain 1405data_latency=2 1406default_p_state=UNDEFINED 1407eventq_index=0 1408p_state_clk_gate_bins=20 1409p_state_clk_gate_max=1000000000000 1410p_state_clk_gate_min=1000 1411power_model=Null 1412sequential_access=false 1413size=32768 1414tag_latency=2 1415 1416[system.cpu2.dtb] 1417type=SparcTLB 1418eventq_index=0 1419size=64 1420 1421[system.cpu2.fuPool] 1422type=FUPool 1423children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1424FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1425eventq_index=0 1426 1427[system.cpu2.fuPool.FUList0] 1428type=FUDesc 1429children=opList 1430count=6 1431eventq_index=0 1432opList=system.cpu2.fuPool.FUList0.opList 1433 1434[system.cpu2.fuPool.FUList0.opList] 1435type=OpDesc 1436eventq_index=0 1437opClass=IntAlu 1438opLat=1 1439pipelined=true 1440 1441[system.cpu2.fuPool.FUList1] 1442type=FUDesc 1443children=opList0 opList1 1444count=2 1445eventq_index=0 1446opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1447 1448[system.cpu2.fuPool.FUList1.opList0] 1449type=OpDesc 1450eventq_index=0 1451opClass=IntMult 1452opLat=3 1453pipelined=true 1454 1455[system.cpu2.fuPool.FUList1.opList1] 1456type=OpDesc 1457eventq_index=0 1458opClass=IntDiv 1459opLat=20 1460pipelined=false 1461 1462[system.cpu2.fuPool.FUList2] 1463type=FUDesc 1464children=opList0 opList1 opList2 1465count=4 1466eventq_index=0 1467opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1468 1469[system.cpu2.fuPool.FUList2.opList0] 1470type=OpDesc 1471eventq_index=0 1472opClass=FloatAdd 1473opLat=2 1474pipelined=true 1475 1476[system.cpu2.fuPool.FUList2.opList1] 1477type=OpDesc 1478eventq_index=0 1479opClass=FloatCmp 1480opLat=2 1481pipelined=true 1482 1483[system.cpu2.fuPool.FUList2.opList2] 1484type=OpDesc 1485eventq_index=0 1486opClass=FloatCvt 1487opLat=2 1488pipelined=true 1489 1490[system.cpu2.fuPool.FUList3] 1491type=FUDesc 1492children=opList0 opList1 opList2 opList3 opList4 1493count=2 1494eventq_index=0 1495opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 system.cpu2.fuPool.FUList3.opList3 system.cpu2.fuPool.FUList3.opList4 1496 1497[system.cpu2.fuPool.FUList3.opList0] 1498type=OpDesc 1499eventq_index=0 1500opClass=FloatMult 1501opLat=4 1502pipelined=true 1503 1504[system.cpu2.fuPool.FUList3.opList1] 1505type=OpDesc 1506eventq_index=0 1507opClass=FloatMultAcc 1508opLat=5 1509pipelined=true 1510 1511[system.cpu2.fuPool.FUList3.opList2] 1512type=OpDesc 1513eventq_index=0 1514opClass=FloatMisc 1515opLat=3 1516pipelined=true 1517 1518[system.cpu2.fuPool.FUList3.opList3] 1519type=OpDesc 1520eventq_index=0 1521opClass=FloatDiv 1522opLat=12 1523pipelined=false 1524 1525[system.cpu2.fuPool.FUList3.opList4] 1526type=OpDesc 1527eventq_index=0 1528opClass=FloatSqrt 1529opLat=24 1530pipelined=false 1531 1532[system.cpu2.fuPool.FUList4] 1533type=FUDesc 1534children=opList0 opList1 1535count=0 1536eventq_index=0 1537opList=system.cpu2.fuPool.FUList4.opList0 system.cpu2.fuPool.FUList4.opList1 1538 1539[system.cpu2.fuPool.FUList4.opList0] 1540type=OpDesc 1541eventq_index=0 1542opClass=MemRead 1543opLat=1 1544pipelined=true 1545 1546[system.cpu2.fuPool.FUList4.opList1] 1547type=OpDesc 1548eventq_index=0 1549opClass=FloatMemRead 1550opLat=1 1551pipelined=true 1552 1553[system.cpu2.fuPool.FUList5] 1554type=FUDesc 1555children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1556count=4 1557eventq_index=0 1558opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1559 1560[system.cpu2.fuPool.FUList5.opList00] 1561type=OpDesc 1562eventq_index=0 1563opClass=SimdAdd 1564opLat=1 1565pipelined=true 1566 1567[system.cpu2.fuPool.FUList5.opList01] 1568type=OpDesc 1569eventq_index=0 1570opClass=SimdAddAcc 1571opLat=1 1572pipelined=true 1573 1574[system.cpu2.fuPool.FUList5.opList02] 1575type=OpDesc 1576eventq_index=0 1577opClass=SimdAlu 1578opLat=1 1579pipelined=true 1580 1581[system.cpu2.fuPool.FUList5.opList03] 1582type=OpDesc 1583eventq_index=0 1584opClass=SimdCmp 1585opLat=1 1586pipelined=true 1587 1588[system.cpu2.fuPool.FUList5.opList04] 1589type=OpDesc 1590eventq_index=0 1591opClass=SimdCvt 1592opLat=1 1593pipelined=true 1594 1595[system.cpu2.fuPool.FUList5.opList05] 1596type=OpDesc 1597eventq_index=0 1598opClass=SimdMisc 1599opLat=1 1600pipelined=true 1601 1602[system.cpu2.fuPool.FUList5.opList06] 1603type=OpDesc 1604eventq_index=0 1605opClass=SimdMult 1606opLat=1 1607pipelined=true 1608 1609[system.cpu2.fuPool.FUList5.opList07] 1610type=OpDesc 1611eventq_index=0 1612opClass=SimdMultAcc 1613opLat=1 1614pipelined=true 1615 1616[system.cpu2.fuPool.FUList5.opList08] 1617type=OpDesc 1618eventq_index=0 1619opClass=SimdShift 1620opLat=1 1621pipelined=true 1622 1623[system.cpu2.fuPool.FUList5.opList09] 1624type=OpDesc 1625eventq_index=0 1626opClass=SimdShiftAcc 1627opLat=1 1628pipelined=true 1629 1630[system.cpu2.fuPool.FUList5.opList10] 1631type=OpDesc 1632eventq_index=0 1633opClass=SimdSqrt 1634opLat=1 1635pipelined=true 1636 1637[system.cpu2.fuPool.FUList5.opList11] 1638type=OpDesc 1639eventq_index=0 1640opClass=SimdFloatAdd 1641opLat=1 1642pipelined=true 1643 1644[system.cpu2.fuPool.FUList5.opList12] 1645type=OpDesc 1646eventq_index=0 1647opClass=SimdFloatAlu 1648opLat=1 1649pipelined=true 1650 1651[system.cpu2.fuPool.FUList5.opList13] 1652type=OpDesc 1653eventq_index=0 1654opClass=SimdFloatCmp 1655opLat=1 1656pipelined=true 1657 1658[system.cpu2.fuPool.FUList5.opList14] 1659type=OpDesc 1660eventq_index=0 1661opClass=SimdFloatCvt 1662opLat=1 1663pipelined=true 1664 1665[system.cpu2.fuPool.FUList5.opList15] 1666type=OpDesc 1667eventq_index=0 1668opClass=SimdFloatDiv 1669opLat=1 1670pipelined=true 1671 1672[system.cpu2.fuPool.FUList5.opList16] 1673type=OpDesc 1674eventq_index=0 1675opClass=SimdFloatMisc 1676opLat=1 1677pipelined=true 1678 1679[system.cpu2.fuPool.FUList5.opList17] 1680type=OpDesc 1681eventq_index=0 1682opClass=SimdFloatMult 1683opLat=1 1684pipelined=true 1685 1686[system.cpu2.fuPool.FUList5.opList18] 1687type=OpDesc 1688eventq_index=0 1689opClass=SimdFloatMultAcc 1690opLat=1 1691pipelined=true 1692 1693[system.cpu2.fuPool.FUList5.opList19] 1694type=OpDesc 1695eventq_index=0 1696opClass=SimdFloatSqrt 1697opLat=1 1698pipelined=true 1699 1700[system.cpu2.fuPool.FUList6] 1701type=FUDesc 1702children=opList0 opList1 1703count=0 1704eventq_index=0 1705opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1 1706 1707[system.cpu2.fuPool.FUList6.opList0] 1708type=OpDesc 1709eventq_index=0 1710opClass=MemWrite 1711opLat=1 1712pipelined=true 1713 1714[system.cpu2.fuPool.FUList6.opList1] 1715type=OpDesc 1716eventq_index=0 1717opClass=FloatMemWrite 1718opLat=1 1719pipelined=true 1720 1721[system.cpu2.fuPool.FUList7] 1722type=FUDesc 1723children=opList0 opList1 opList2 opList3 1724count=4 1725eventq_index=0 1726opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 system.cpu2.fuPool.FUList7.opList2 system.cpu2.fuPool.FUList7.opList3 1727 1728[system.cpu2.fuPool.FUList7.opList0] 1729type=OpDesc 1730eventq_index=0 1731opClass=MemRead 1732opLat=1 1733pipelined=true 1734 1735[system.cpu2.fuPool.FUList7.opList1] 1736type=OpDesc 1737eventq_index=0 1738opClass=MemWrite 1739opLat=1 1740pipelined=true 1741 1742[system.cpu2.fuPool.FUList7.opList2] 1743type=OpDesc 1744eventq_index=0 1745opClass=FloatMemRead 1746opLat=1 1747pipelined=true 1748 1749[system.cpu2.fuPool.FUList7.opList3] 1750type=OpDesc 1751eventq_index=0 1752opClass=FloatMemWrite 1753opLat=1 1754pipelined=true 1755 1756[system.cpu2.fuPool.FUList8] 1757type=FUDesc 1758children=opList 1759count=1 1760eventq_index=0 1761opList=system.cpu2.fuPool.FUList8.opList 1762 1763[system.cpu2.fuPool.FUList8.opList] 1764type=OpDesc 1765eventq_index=0 1766opClass=IprAccess 1767opLat=3 1768pipelined=false 1769 1770[system.cpu2.icache] 1771type=Cache 1772children=tags 1773addr_ranges=0:18446744073709551615:0:0:0:0 1774assoc=1 1775clk_domain=system.cpu_clk_domain 1776clusivity=mostly_incl 1777data_latency=2 1778default_p_state=UNDEFINED 1779demand_mshr_reserve=1 1780eventq_index=0 1781is_read_only=true 1782max_miss_count=0 1783mshrs=4 1784p_state_clk_gate_bins=20 1785p_state_clk_gate_max=1000000000000 1786p_state_clk_gate_min=1000 1787power_model=Null 1788prefetch_on_access=false 1789prefetcher=Null 1790response_latency=2 1791sequential_access=false 1792size=32768 1793system=system 1794tag_latency=2 1795tags=system.cpu2.icache.tags 1796tgts_per_mshr=20 1797write_buffers=8 1798writeback_clean=true 1799cpu_side=system.cpu2.icache_port 1800mem_side=system.toL2Bus.slave[4] 1801 1802[system.cpu2.icache.tags] 1803type=LRU 1804assoc=1 1805block_size=64 1806clk_domain=system.cpu_clk_domain 1807data_latency=2 1808default_p_state=UNDEFINED 1809eventq_index=0 1810p_state_clk_gate_bins=20 1811p_state_clk_gate_max=1000000000000 1812p_state_clk_gate_min=1000 1813power_model=Null 1814sequential_access=false 1815size=32768 1816tag_latency=2 1817 1818[system.cpu2.interrupts] 1819type=SparcInterrupts 1820eventq_index=0 1821 1822[system.cpu2.isa] 1823type=SparcISA 1824eventq_index=0 1825 1826[system.cpu2.itb] 1827type=SparcTLB 1828eventq_index=0 1829size=64 1830 1831[system.cpu2.tracer] 1832type=ExeTracer 1833eventq_index=0 1834 1835[system.cpu3] 1836type=DerivO3CPU 1837children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1838LFSTSize=1024 1839LQEntries=32 1840LSQCheckLoads=true 1841LSQDepCheckShift=4 1842SQEntries=32 1843SSITSize=1024 1844activity=0 1845backComSize=5 1846branchPred=system.cpu3.branchPred 1847cacheStorePorts=200 1848checker=Null 1849clk_domain=system.cpu_clk_domain 1850commitToDecodeDelay=1 1851commitToFetchDelay=1 1852commitToIEWDelay=1 1853commitToRenameDelay=1 1854commitWidth=8 1855cpu_id=3 1856decodeToFetchDelay=1 1857decodeToRenameDelay=1 1858decodeWidth=8 1859default_p_state=UNDEFINED 1860dispatchWidth=8 1861do_checkpoint_insts=true 1862do_quiesce=true 1863do_statistics_insts=true 1864dtb=system.cpu3.dtb 1865eventq_index=0 1866fetchBufferSize=64 1867fetchQueueSize=32 1868fetchToDecodeDelay=1 1869fetchTrapLatency=1 1870fetchWidth=8 1871forwardComSize=5 1872fuPool=system.cpu3.fuPool 1873function_trace=false 1874function_trace_start=0 1875iewToCommitDelay=1 1876iewToDecodeDelay=1 1877iewToFetchDelay=1 1878iewToRenameDelay=1 1879interrupts=system.cpu3.interrupts 1880isa=system.cpu3.isa 1881issueToExecuteDelay=1 1882issueWidth=8 1883itb=system.cpu3.itb 1884max_insts_all_threads=0 1885max_insts_any_thread=0 1886max_loads_all_threads=0 1887max_loads_any_thread=0 1888needsTSO=false 1889numIQEntries=64 1890numPhysCCRegs=0 1891numPhysFloatRegs=256 1892numPhysIntRegs=256 1893numROBEntries=192 1894numRobs=1 1895numThreads=1 1896p_state_clk_gate_bins=20 1897p_state_clk_gate_max=1000000000000 1898p_state_clk_gate_min=1000 1899power_model=Null 1900profile=0 1901progress_interval=0 1902renameToDecodeDelay=1 1903renameToFetchDelay=1 1904renameToIEWDelay=2 1905renameToROBDelay=1 1906renameWidth=8 1907simpoint_start_insts= 1908smtCommitPolicy=RoundRobin 1909smtFetchPolicy=SingleThread 1910smtIQPolicy=Partitioned 1911smtIQThreshold=100 1912smtLSQPolicy=Partitioned 1913smtLSQThreshold=100 1914smtNumFetchingThreads=1 1915smtROBPolicy=Partitioned 1916smtROBThreshold=100 1917socket_id=0 1918squashWidth=8 1919store_set_clear_period=250000 1920switched_out=false 1921syscallRetryLatency=10000 1922system=system 1923tracer=system.cpu3.tracer 1924trapLatency=13 1925wbWidth=8 1926workload=system.cpu0.workload 1927dcache_port=system.cpu3.dcache.cpu_side 1928icache_port=system.cpu3.icache.cpu_side 1929 1930[system.cpu3.branchPred] 1931type=TournamentBP 1932BTBEntries=4096 1933BTBTagSize=16 1934RASSize=16 1935choiceCtrBits=2 1936choicePredictorSize=8192 1937eventq_index=0 1938globalCtrBits=2 1939globalPredictorSize=8192 1940indirectHashGHR=true 1941indirectHashTargets=true 1942indirectPathLength=3 1943indirectSets=256 1944indirectTagSize=16 1945indirectWays=2 1946instShiftAmt=2 1947localCtrBits=2 1948localHistoryTableSize=2048 1949localPredictorSize=2048 1950numThreads=1 1951useIndirect=true 1952 1953[system.cpu3.dcache] 1954type=Cache 1955children=tags 1956addr_ranges=0:18446744073709551615:0:0:0:0 1957assoc=4 1958clk_domain=system.cpu_clk_domain 1959clusivity=mostly_incl 1960data_latency=2 1961default_p_state=UNDEFINED 1962demand_mshr_reserve=1 1963eventq_index=0 1964is_read_only=false 1965max_miss_count=0 1966mshrs=4 1967p_state_clk_gate_bins=20 1968p_state_clk_gate_max=1000000000000 1969p_state_clk_gate_min=1000 1970power_model=Null 1971prefetch_on_access=false 1972prefetcher=Null 1973response_latency=2 1974sequential_access=false 1975size=32768 1976system=system 1977tag_latency=2 1978tags=system.cpu3.dcache.tags 1979tgts_per_mshr=20 1980write_buffers=8 1981writeback_clean=false 1982cpu_side=system.cpu3.dcache_port 1983mem_side=system.toL2Bus.slave[7] 1984 1985[system.cpu3.dcache.tags] 1986type=LRU 1987assoc=4 1988block_size=64 1989clk_domain=system.cpu_clk_domain 1990data_latency=2 1991default_p_state=UNDEFINED 1992eventq_index=0 1993p_state_clk_gate_bins=20 1994p_state_clk_gate_max=1000000000000 1995p_state_clk_gate_min=1000 1996power_model=Null 1997sequential_access=false 1998size=32768 1999tag_latency=2 2000 2001[system.cpu3.dtb] 2002type=SparcTLB 2003eventq_index=0 2004size=64 2005 2006[system.cpu3.fuPool] 2007type=FUPool 2008children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 2009FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 2010eventq_index=0 2011 2012[system.cpu3.fuPool.FUList0] 2013type=FUDesc 2014children=opList 2015count=6 2016eventq_index=0 2017opList=system.cpu3.fuPool.FUList0.opList 2018 2019[system.cpu3.fuPool.FUList0.opList] 2020type=OpDesc 2021eventq_index=0 2022opClass=IntAlu 2023opLat=1 2024pipelined=true 2025 2026[system.cpu3.fuPool.FUList1] 2027type=FUDesc 2028children=opList0 opList1 2029count=2 2030eventq_index=0 2031opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 2032 2033[system.cpu3.fuPool.FUList1.opList0] 2034type=OpDesc 2035eventq_index=0 2036opClass=IntMult 2037opLat=3 2038pipelined=true 2039 2040[system.cpu3.fuPool.FUList1.opList1] 2041type=OpDesc 2042eventq_index=0 2043opClass=IntDiv 2044opLat=20 2045pipelined=false 2046 2047[system.cpu3.fuPool.FUList2] 2048type=FUDesc 2049children=opList0 opList1 opList2 2050count=4 2051eventq_index=0 2052opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 2053 2054[system.cpu3.fuPool.FUList2.opList0] 2055type=OpDesc 2056eventq_index=0 2057opClass=FloatAdd 2058opLat=2 2059pipelined=true 2060 2061[system.cpu3.fuPool.FUList2.opList1] 2062type=OpDesc 2063eventq_index=0 2064opClass=FloatCmp 2065opLat=2 2066pipelined=true 2067 2068[system.cpu3.fuPool.FUList2.opList2] 2069type=OpDesc 2070eventq_index=0 2071opClass=FloatCvt 2072opLat=2 2073pipelined=true 2074 2075[system.cpu3.fuPool.FUList3] 2076type=FUDesc 2077children=opList0 opList1 opList2 opList3 opList4 2078count=2 2079eventq_index=0 2080opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 system.cpu3.fuPool.FUList3.opList3 system.cpu3.fuPool.FUList3.opList4 2081 2082[system.cpu3.fuPool.FUList3.opList0] 2083type=OpDesc 2084eventq_index=0 2085opClass=FloatMult 2086opLat=4 2087pipelined=true 2088 2089[system.cpu3.fuPool.FUList3.opList1] 2090type=OpDesc 2091eventq_index=0 2092opClass=FloatMultAcc 2093opLat=5 2094pipelined=true 2095 2096[system.cpu3.fuPool.FUList3.opList2] 2097type=OpDesc 2098eventq_index=0 2099opClass=FloatMisc 2100opLat=3 2101pipelined=true 2102 2103[system.cpu3.fuPool.FUList3.opList3] 2104type=OpDesc 2105eventq_index=0 2106opClass=FloatDiv 2107opLat=12 2108pipelined=false 2109 2110[system.cpu3.fuPool.FUList3.opList4] 2111type=OpDesc 2112eventq_index=0 2113opClass=FloatSqrt 2114opLat=24 2115pipelined=false 2116 2117[system.cpu3.fuPool.FUList4] 2118type=FUDesc 2119children=opList0 opList1 2120count=0 2121eventq_index=0 2122opList=system.cpu3.fuPool.FUList4.opList0 system.cpu3.fuPool.FUList4.opList1 2123 2124[system.cpu3.fuPool.FUList4.opList0] 2125type=OpDesc 2126eventq_index=0 2127opClass=MemRead 2128opLat=1 2129pipelined=true 2130 2131[system.cpu3.fuPool.FUList4.opList1] 2132type=OpDesc 2133eventq_index=0 2134opClass=FloatMemRead 2135opLat=1 2136pipelined=true 2137 2138[system.cpu3.fuPool.FUList5] 2139type=FUDesc 2140children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 2141count=4 2142eventq_index=0 2143opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 2144 2145[system.cpu3.fuPool.FUList5.opList00] 2146type=OpDesc 2147eventq_index=0 2148opClass=SimdAdd 2149opLat=1 2150pipelined=true 2151 2152[system.cpu3.fuPool.FUList5.opList01] 2153type=OpDesc 2154eventq_index=0 2155opClass=SimdAddAcc 2156opLat=1 2157pipelined=true 2158 2159[system.cpu3.fuPool.FUList5.opList02] 2160type=OpDesc 2161eventq_index=0 2162opClass=SimdAlu 2163opLat=1 2164pipelined=true 2165 2166[system.cpu3.fuPool.FUList5.opList03] 2167type=OpDesc 2168eventq_index=0 2169opClass=SimdCmp 2170opLat=1 2171pipelined=true 2172 2173[system.cpu3.fuPool.FUList5.opList04] 2174type=OpDesc 2175eventq_index=0 2176opClass=SimdCvt 2177opLat=1 2178pipelined=true 2179 2180[system.cpu3.fuPool.FUList5.opList05] 2181type=OpDesc 2182eventq_index=0 2183opClass=SimdMisc 2184opLat=1 2185pipelined=true 2186 2187[system.cpu3.fuPool.FUList5.opList06] 2188type=OpDesc 2189eventq_index=0 2190opClass=SimdMult 2191opLat=1 2192pipelined=true 2193 2194[system.cpu3.fuPool.FUList5.opList07] 2195type=OpDesc 2196eventq_index=0 2197opClass=SimdMultAcc 2198opLat=1 2199pipelined=true 2200 2201[system.cpu3.fuPool.FUList5.opList08] 2202type=OpDesc 2203eventq_index=0 2204opClass=SimdShift 2205opLat=1 2206pipelined=true 2207 2208[system.cpu3.fuPool.FUList5.opList09] 2209type=OpDesc 2210eventq_index=0 2211opClass=SimdShiftAcc 2212opLat=1 2213pipelined=true 2214 2215[system.cpu3.fuPool.FUList5.opList10] 2216type=OpDesc 2217eventq_index=0 2218opClass=SimdSqrt 2219opLat=1 2220pipelined=true 2221 2222[system.cpu3.fuPool.FUList5.opList11] 2223type=OpDesc 2224eventq_index=0 2225opClass=SimdFloatAdd 2226opLat=1 2227pipelined=true 2228 2229[system.cpu3.fuPool.FUList5.opList12] 2230type=OpDesc 2231eventq_index=0 2232opClass=SimdFloatAlu 2233opLat=1 2234pipelined=true 2235 2236[system.cpu3.fuPool.FUList5.opList13] 2237type=OpDesc 2238eventq_index=0 2239opClass=SimdFloatCmp 2240opLat=1 2241pipelined=true 2242 2243[system.cpu3.fuPool.FUList5.opList14] 2244type=OpDesc 2245eventq_index=0 2246opClass=SimdFloatCvt 2247opLat=1 2248pipelined=true 2249 2250[system.cpu3.fuPool.FUList5.opList15] 2251type=OpDesc 2252eventq_index=0 2253opClass=SimdFloatDiv 2254opLat=1 2255pipelined=true 2256 2257[system.cpu3.fuPool.FUList5.opList16] 2258type=OpDesc 2259eventq_index=0 2260opClass=SimdFloatMisc 2261opLat=1 2262pipelined=true 2263 2264[system.cpu3.fuPool.FUList5.opList17] 2265type=OpDesc 2266eventq_index=0 2267opClass=SimdFloatMult 2268opLat=1 2269pipelined=true 2270 2271[system.cpu3.fuPool.FUList5.opList18] 2272type=OpDesc 2273eventq_index=0 2274opClass=SimdFloatMultAcc 2275opLat=1 2276pipelined=true 2277 2278[system.cpu3.fuPool.FUList5.opList19] 2279type=OpDesc 2280eventq_index=0 2281opClass=SimdFloatSqrt 2282opLat=1 2283pipelined=true 2284 2285[system.cpu3.fuPool.FUList6] 2286type=FUDesc 2287children=opList0 opList1 2288count=0 2289eventq_index=0 2290opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1 2291 2292[system.cpu3.fuPool.FUList6.opList0] 2293type=OpDesc 2294eventq_index=0 2295opClass=MemWrite 2296opLat=1 2297pipelined=true 2298 2299[system.cpu3.fuPool.FUList6.opList1] 2300type=OpDesc 2301eventq_index=0 2302opClass=FloatMemWrite 2303opLat=1 2304pipelined=true 2305 2306[system.cpu3.fuPool.FUList7] 2307type=FUDesc 2308children=opList0 opList1 opList2 opList3 2309count=4 2310eventq_index=0 2311opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 system.cpu3.fuPool.FUList7.opList2 system.cpu3.fuPool.FUList7.opList3 2312 2313[system.cpu3.fuPool.FUList7.opList0] 2314type=OpDesc 2315eventq_index=0 2316opClass=MemRead 2317opLat=1 2318pipelined=true 2319 2320[system.cpu3.fuPool.FUList7.opList1] 2321type=OpDesc 2322eventq_index=0 2323opClass=MemWrite 2324opLat=1 2325pipelined=true 2326 2327[system.cpu3.fuPool.FUList7.opList2] 2328type=OpDesc 2329eventq_index=0 2330opClass=FloatMemRead 2331opLat=1 2332pipelined=true 2333 2334[system.cpu3.fuPool.FUList7.opList3] 2335type=OpDesc 2336eventq_index=0 2337opClass=FloatMemWrite 2338opLat=1 2339pipelined=true 2340 2341[system.cpu3.fuPool.FUList8] 2342type=FUDesc 2343children=opList 2344count=1 2345eventq_index=0 2346opList=system.cpu3.fuPool.FUList8.opList 2347 2348[system.cpu3.fuPool.FUList8.opList] 2349type=OpDesc 2350eventq_index=0 2351opClass=IprAccess 2352opLat=3 2353pipelined=false 2354 2355[system.cpu3.icache] 2356type=Cache 2357children=tags 2358addr_ranges=0:18446744073709551615:0:0:0:0 2359assoc=1 2360clk_domain=system.cpu_clk_domain 2361clusivity=mostly_incl 2362data_latency=2 2363default_p_state=UNDEFINED 2364demand_mshr_reserve=1 2365eventq_index=0 2366is_read_only=true 2367max_miss_count=0 2368mshrs=4 2369p_state_clk_gate_bins=20 2370p_state_clk_gate_max=1000000000000 2371p_state_clk_gate_min=1000 2372power_model=Null 2373prefetch_on_access=false 2374prefetcher=Null 2375response_latency=2 2376sequential_access=false 2377size=32768 2378system=system 2379tag_latency=2 2380tags=system.cpu3.icache.tags 2381tgts_per_mshr=20 2382write_buffers=8 2383writeback_clean=true 2384cpu_side=system.cpu3.icache_port 2385mem_side=system.toL2Bus.slave[6] 2386 2387[system.cpu3.icache.tags] 2388type=LRU 2389assoc=1 2390block_size=64 2391clk_domain=system.cpu_clk_domain 2392data_latency=2 2393default_p_state=UNDEFINED 2394eventq_index=0 2395p_state_clk_gate_bins=20 2396p_state_clk_gate_max=1000000000000 2397p_state_clk_gate_min=1000 2398power_model=Null 2399sequential_access=false 2400size=32768 2401tag_latency=2 2402 2403[system.cpu3.interrupts] 2404type=SparcInterrupts 2405eventq_index=0 2406 2407[system.cpu3.isa] 2408type=SparcISA 2409eventq_index=0 2410 2411[system.cpu3.itb] 2412type=SparcTLB 2413eventq_index=0 2414size=64 2415 2416[system.cpu3.tracer] 2417type=ExeTracer 2418eventq_index=0 2419 2420[system.cpu_clk_domain] 2421type=SrcClockDomain 2422clock=500 2423domain_id=-1 2424eventq_index=0 2425init_perf_level=0 2426voltage_domain=system.voltage_domain 2427 2428[system.dvfs_handler] 2429type=DVFSHandler 2430domains= 2431enable=false 2432eventq_index=0 2433sys_clk_domain=system.clk_domain 2434transition_latency=100000000 2435 2436[system.l2c] 2437type=Cache 2438children=tags 2439addr_ranges=0:18446744073709551615:0:0:0:0 2440assoc=8 2441clk_domain=system.cpu_clk_domain 2442clusivity=mostly_incl 2443data_latency=20 2444default_p_state=UNDEFINED 2445demand_mshr_reserve=1 2446eventq_index=0 2447is_read_only=false 2448max_miss_count=0 2449mshrs=20 2450p_state_clk_gate_bins=20 2451p_state_clk_gate_max=1000000000000 2452p_state_clk_gate_min=1000 2453power_model=Null 2454prefetch_on_access=false 2455prefetcher=Null 2456response_latency=20 2457sequential_access=false 2458size=4194304 2459system=system 2460tag_latency=20 2461tags=system.l2c.tags 2462tgts_per_mshr=12 2463write_buffers=8 2464writeback_clean=false 2465cpu_side=system.toL2Bus.master[0] 2466mem_side=system.membus.slave[1] 2467 2468[system.l2c.tags] 2469type=LRU 2470assoc=8 2471block_size=64 2472clk_domain=system.cpu_clk_domain 2473data_latency=20 2474default_p_state=UNDEFINED 2475eventq_index=0 2476p_state_clk_gate_bins=20 2477p_state_clk_gate_max=1000000000000 2478p_state_clk_gate_min=1000 2479power_model=Null 2480sequential_access=false 2481size=4194304 2482tag_latency=20 2483 2484[system.membus] 2485type=CoherentXBar 2486children=snoop_filter 2487clk_domain=system.clk_domain 2488default_p_state=UNDEFINED 2489eventq_index=0 2490forward_latency=4 2491frontend_latency=3 2492p_state_clk_gate_bins=20 2493p_state_clk_gate_max=1000000000000 2494p_state_clk_gate_min=1000 2495point_of_coherency=true 2496power_model=Null 2497response_latency=2 2498snoop_filter=system.membus.snoop_filter 2499snoop_response_latency=4 2500system=system 2501use_default_range=false 2502width=16 2503master=system.physmem.port 2504slave=system.system_port system.l2c.mem_side 2505 2506[system.membus.snoop_filter] 2507type=SnoopFilter 2508eventq_index=0 2509lookup_latency=1 2510max_capacity=8388608 2511system=system 2512 2513[system.physmem] 2514type=DRAMCtrl 2515IDD0=0.055000 2516IDD02=0.000000 2517IDD2N=0.032000 2518IDD2N2=0.000000 2519IDD2P0=0.000000 2520IDD2P02=0.000000 2521IDD2P1=0.032000 2522IDD2P12=0.000000 2523IDD3N=0.038000 2524IDD3N2=0.000000 2525IDD3P0=0.000000 2526IDD3P02=0.000000 2527IDD3P1=0.038000 2528IDD3P12=0.000000 2529IDD4R=0.157000 2530IDD4R2=0.000000 2531IDD4W=0.125000 2532IDD4W2=0.000000 2533IDD5=0.235000 2534IDD52=0.000000 2535IDD6=0.020000 2536IDD62=0.000000 2537VDD=1.500000 2538VDD2=0.000000 2539activation_limit=4 2540addr_mapping=RoRaBaCoCh 2541bank_groups_per_rank=0 2542banks_per_rank=8 2543burst_length=8 2544channels=1 2545clk_domain=system.clk_domain 2546conf_table_reported=true 2547default_p_state=UNDEFINED 2548device_bus_width=8 2549device_rowbuffer_size=1024 2550device_size=536870912 2551devices_per_rank=8 2552dll=true 2553eventq_index=0 2554in_addr_map=true 2555kvm_map=true 2556max_accesses_per_row=16 2557mem_sched_policy=frfcfs 2558min_writes_per_switch=16 2559null=false 2560p_state_clk_gate_bins=20 2561p_state_clk_gate_max=1000000000000 2562p_state_clk_gate_min=1000 2563page_policy=open_adaptive 2564power_model=Null 2565range=0:134217727:0:0:0:0 2566ranks_per_channel=2 2567read_buffer_size=32 2568static_backend_latency=10000 2569static_frontend_latency=10000 2570tBURST=5000 2571tCCD_L=0 2572tCK=1250 2573tCL=13750 2574tCS=2500 2575tRAS=35000 2576tRCD=13750 2577tREFI=7800000 2578tRFC=260000 2579tRP=13750 2580tRRD=6000 2581tRRD_L=0 2582tRTP=7500 2583tRTW=2500 2584tWR=15000 2585tWTR=7500 2586tXAW=30000 2587tXP=6000 2588tXPDLL=0 2589tXS=270000 2590tXSDLL=0 2591write_buffer_size=64 2592write_high_thresh_perc=85 2593write_low_thresh_perc=50 2594port=system.membus.master[0] 2595 2596[system.toL2Bus] 2597type=CoherentXBar 2598children=snoop_filter 2599clk_domain=system.cpu_clk_domain 2600default_p_state=UNDEFINED 2601eventq_index=0 2602forward_latency=0 2603frontend_latency=1 2604p_state_clk_gate_bins=20 2605p_state_clk_gate_max=1000000000000 2606p_state_clk_gate_min=1000 2607point_of_coherency=false 2608power_model=Null 2609response_latency=1 2610snoop_filter=system.toL2Bus.snoop_filter 2611snoop_response_latency=1 2612system=system 2613use_default_range=false 2614width=32 2615master=system.l2c.cpu_side 2616slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2617 2618[system.toL2Bus.snoop_filter] 2619type=SnoopFilter 2620eventq_index=0 2621lookup_latency=0 2622max_capacity=8388608 2623system=system 2624 2625[system.voltage_domain] 2626type=VoltageDomain 2627eventq_index=0 2628voltage=1.000000 2629 2630