config.ini revision 8835
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=timing 17memories=system.physmem 18num_work_ids=16 19physmem=system.physmem 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.port[2] 30 31[system.cpu0] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts itb tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu0.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu0.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu0.interrupts 81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu0.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99phase=0 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119system=system 120tracer=system.cpu0.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu0.workload 125dcache_port=system.cpu0.dcache.cpu_side 126icache_port=system.cpu0.icache.cpu_side 127 128[system.cpu0.dcache] 129type=BaseCache 130addr_range=0:18446744073709551615 131assoc=4 132block_size=64 133forward_snoops=true 134hash_delay=1 135is_top_level=true 136latency=1000 137max_miss_count=0 138mshrs=4 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null 143size=32768 144subblock_size=0 145system=system 146tgts_per_mshr=20 147trace_addr=0 148two_queue=false 149write_buffers=8 150cpu_side=system.cpu0.dcache_port 151mem_side=system.toL2Bus.port[2] 152 153[system.cpu0.dtb] 154type=SparcTLB 155size=64 156 157[system.cpu0.fuPool] 158type=FUPool 159children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 160FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 161 162[system.cpu0.fuPool.FUList0] 163type=FUDesc 164children=opList 165count=6 166opList=system.cpu0.fuPool.FUList0.opList 167 168[system.cpu0.fuPool.FUList0.opList] 169type=OpDesc 170issueLat=1 171opClass=IntAlu 172opLat=1 173 174[system.cpu0.fuPool.FUList1] 175type=FUDesc 176children=opList0 opList1 177count=2 178opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 179 180[system.cpu0.fuPool.FUList1.opList0] 181type=OpDesc 182issueLat=1 183opClass=IntMult 184opLat=3 185 186[system.cpu0.fuPool.FUList1.opList1] 187type=OpDesc 188issueLat=19 189opClass=IntDiv 190opLat=20 191 192[system.cpu0.fuPool.FUList2] 193type=FUDesc 194children=opList0 opList1 opList2 195count=4 196opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 197 198[system.cpu0.fuPool.FUList2.opList0] 199type=OpDesc 200issueLat=1 201opClass=FloatAdd 202opLat=2 203 204[system.cpu0.fuPool.FUList2.opList1] 205type=OpDesc 206issueLat=1 207opClass=FloatCmp 208opLat=2 209 210[system.cpu0.fuPool.FUList2.opList2] 211type=OpDesc 212issueLat=1 213opClass=FloatCvt 214opLat=2 215 216[system.cpu0.fuPool.FUList3] 217type=FUDesc 218children=opList0 opList1 opList2 219count=2 220opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 221 222[system.cpu0.fuPool.FUList3.opList0] 223type=OpDesc 224issueLat=1 225opClass=FloatMult 226opLat=4 227 228[system.cpu0.fuPool.FUList3.opList1] 229type=OpDesc 230issueLat=12 231opClass=FloatDiv 232opLat=12 233 234[system.cpu0.fuPool.FUList3.opList2] 235type=OpDesc 236issueLat=24 237opClass=FloatSqrt 238opLat=24 239 240[system.cpu0.fuPool.FUList4] 241type=FUDesc 242children=opList 243count=0 244opList=system.cpu0.fuPool.FUList4.opList 245 246[system.cpu0.fuPool.FUList4.opList] 247type=OpDesc 248issueLat=1 249opClass=MemRead 250opLat=1 251 252[system.cpu0.fuPool.FUList5] 253type=FUDesc 254children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 255count=4 256opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 257 258[system.cpu0.fuPool.FUList5.opList00] 259type=OpDesc 260issueLat=1 261opClass=SimdAdd 262opLat=1 263 264[system.cpu0.fuPool.FUList5.opList01] 265type=OpDesc 266issueLat=1 267opClass=SimdAddAcc 268opLat=1 269 270[system.cpu0.fuPool.FUList5.opList02] 271type=OpDesc 272issueLat=1 273opClass=SimdAlu 274opLat=1 275 276[system.cpu0.fuPool.FUList5.opList03] 277type=OpDesc 278issueLat=1 279opClass=SimdCmp 280opLat=1 281 282[system.cpu0.fuPool.FUList5.opList04] 283type=OpDesc 284issueLat=1 285opClass=SimdCvt 286opLat=1 287 288[system.cpu0.fuPool.FUList5.opList05] 289type=OpDesc 290issueLat=1 291opClass=SimdMisc 292opLat=1 293 294[system.cpu0.fuPool.FUList5.opList06] 295type=OpDesc 296issueLat=1 297opClass=SimdMult 298opLat=1 299 300[system.cpu0.fuPool.FUList5.opList07] 301type=OpDesc 302issueLat=1 303opClass=SimdMultAcc 304opLat=1 305 306[system.cpu0.fuPool.FUList5.opList08] 307type=OpDesc 308issueLat=1 309opClass=SimdShift 310opLat=1 311 312[system.cpu0.fuPool.FUList5.opList09] 313type=OpDesc 314issueLat=1 315opClass=SimdShiftAcc 316opLat=1 317 318[system.cpu0.fuPool.FUList5.opList10] 319type=OpDesc 320issueLat=1 321opClass=SimdSqrt 322opLat=1 323 324[system.cpu0.fuPool.FUList5.opList11] 325type=OpDesc 326issueLat=1 327opClass=SimdFloatAdd 328opLat=1 329 330[system.cpu0.fuPool.FUList5.opList12] 331type=OpDesc 332issueLat=1 333opClass=SimdFloatAlu 334opLat=1 335 336[system.cpu0.fuPool.FUList5.opList13] 337type=OpDesc 338issueLat=1 339opClass=SimdFloatCmp 340opLat=1 341 342[system.cpu0.fuPool.FUList5.opList14] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatCvt 346opLat=1 347 348[system.cpu0.fuPool.FUList5.opList15] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatDiv 352opLat=1 353 354[system.cpu0.fuPool.FUList5.opList16] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatMisc 358opLat=1 359 360[system.cpu0.fuPool.FUList5.opList17] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatMult 364opLat=1 365 366[system.cpu0.fuPool.FUList5.opList18] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatMultAcc 370opLat=1 371 372[system.cpu0.fuPool.FUList5.opList19] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatSqrt 376opLat=1 377 378[system.cpu0.fuPool.FUList6] 379type=FUDesc 380children=opList 381count=0 382opList=system.cpu0.fuPool.FUList6.opList 383 384[system.cpu0.fuPool.FUList6.opList] 385type=OpDesc 386issueLat=1 387opClass=MemWrite 388opLat=1 389 390[system.cpu0.fuPool.FUList7] 391type=FUDesc 392children=opList0 opList1 393count=4 394opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 395 396[system.cpu0.fuPool.FUList7.opList0] 397type=OpDesc 398issueLat=1 399opClass=MemRead 400opLat=1 401 402[system.cpu0.fuPool.FUList7.opList1] 403type=OpDesc 404issueLat=1 405opClass=MemWrite 406opLat=1 407 408[system.cpu0.fuPool.FUList8] 409type=FUDesc 410children=opList 411count=1 412opList=system.cpu0.fuPool.FUList8.opList 413 414[system.cpu0.fuPool.FUList8.opList] 415type=OpDesc 416issueLat=3 417opClass=IprAccess 418opLat=3 419 420[system.cpu0.icache] 421type=BaseCache 422addr_range=0:18446744073709551615 423assoc=1 424block_size=64 425forward_snoops=true 426hash_delay=1 427is_top_level=true 428latency=1000 429max_miss_count=0 430mshrs=4 431prefetch_on_access=false 432prefetcher=Null 433prioritizeRequests=false 434repl=Null 435size=32768 436subblock_size=0 437system=system 438tgts_per_mshr=20 439trace_addr=0 440two_queue=false 441write_buffers=8 442cpu_side=system.cpu0.icache_port 443mem_side=system.toL2Bus.port[1] 444 445[system.cpu0.interrupts] 446type=SparcInterrupts 447 448[system.cpu0.itb] 449type=SparcTLB 450size=64 451 452[system.cpu0.tracer] 453type=ExeTracer 454 455[system.cpu0.workload] 456type=LiveProcess 457cmd=test_atomic 4 458cwd= 459egid=100 460env= 461errout=cerr 462euid=100 463executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic 464gid=100 465input=cin 466max_stack_size=67108864 467output=cout 468pid=100 469ppid=99 470simpoint=0 471system=system 472uid=100 473 474[system.cpu1] 475type=DerivO3CPU 476children=dcache dtb fuPool icache interrupts itb tracer 477BTBEntries=4096 478BTBTagSize=16 479LFSTSize=1024 480LQEntries=32 481LSQCheckLoads=true 482LSQDepCheckShift=4 483RASSize=16 484SQEntries=32 485SSITSize=1024 486activity=0 487backComSize=5 488cachePorts=200 489checker=Null 490choiceCtrBits=2 491choicePredictorSize=8192 492clock=500 493commitToDecodeDelay=1 494commitToFetchDelay=1 495commitToIEWDelay=1 496commitToRenameDelay=1 497commitWidth=8 498cpu_id=1 499decodeToFetchDelay=1 500decodeToRenameDelay=1 501decodeWidth=8 502defer_registration=false 503dispatchWidth=8 504do_checkpoint_insts=true 505do_quiesce=true 506do_statistics_insts=true 507dtb=system.cpu1.dtb 508fetchToDecodeDelay=1 509fetchTrapLatency=1 510fetchWidth=8 511forwardComSize=5 512fuPool=system.cpu1.fuPool 513function_trace=false 514function_trace_start=0 515globalCtrBits=2 516globalHistoryBits=13 517globalPredictorSize=8192 518iewToCommitDelay=1 519iewToDecodeDelay=1 520iewToFetchDelay=1 521iewToRenameDelay=1 522instShiftAmt=2 523interrupts=system.cpu1.interrupts 524issueToExecuteDelay=1 525issueWidth=8 526itb=system.cpu1.itb 527localCtrBits=2 528localHistoryBits=11 529localHistoryTableSize=2048 530localPredictorSize=2048 531max_insts_all_threads=0 532max_insts_any_thread=0 533max_loads_all_threads=0 534max_loads_any_thread=0 535needsTSO=false 536numIQEntries=64 537numPhysFloatRegs=256 538numPhysIntRegs=256 539numROBEntries=192 540numRobs=1 541numThreads=1 542phase=0 543predType=tournament 544profile=0 545progress_interval=0 546renameToDecodeDelay=1 547renameToFetchDelay=1 548renameToIEWDelay=2 549renameToROBDelay=1 550renameWidth=8 551smtCommitPolicy=RoundRobin 552smtFetchPolicy=SingleThread 553smtIQPolicy=Partitioned 554smtIQThreshold=100 555smtLSQPolicy=Partitioned 556smtLSQThreshold=100 557smtNumFetchingThreads=1 558smtROBPolicy=Partitioned 559smtROBThreshold=100 560squashWidth=8 561store_set_clear_period=250000 562system=system 563tracer=system.cpu1.tracer 564trapLatency=13 565wbDepth=1 566wbWidth=8 567workload=system.cpu0.workload 568dcache_port=system.cpu1.dcache.cpu_side 569icache_port=system.cpu1.icache.cpu_side 570 571[system.cpu1.dcache] 572type=BaseCache 573addr_range=0:18446744073709551615 574assoc=4 575block_size=64 576forward_snoops=true 577hash_delay=1 578is_top_level=true 579latency=1000 580max_miss_count=0 581mshrs=4 582prefetch_on_access=false 583prefetcher=Null 584prioritizeRequests=false 585repl=Null 586size=32768 587subblock_size=0 588system=system 589tgts_per_mshr=20 590trace_addr=0 591two_queue=false 592write_buffers=8 593cpu_side=system.cpu1.dcache_port 594mem_side=system.toL2Bus.port[4] 595 596[system.cpu1.dtb] 597type=SparcTLB 598size=64 599 600[system.cpu1.fuPool] 601type=FUPool 602children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 603FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 604 605[system.cpu1.fuPool.FUList0] 606type=FUDesc 607children=opList 608count=6 609opList=system.cpu1.fuPool.FUList0.opList 610 611[system.cpu1.fuPool.FUList0.opList] 612type=OpDesc 613issueLat=1 614opClass=IntAlu 615opLat=1 616 617[system.cpu1.fuPool.FUList1] 618type=FUDesc 619children=opList0 opList1 620count=2 621opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 622 623[system.cpu1.fuPool.FUList1.opList0] 624type=OpDesc 625issueLat=1 626opClass=IntMult 627opLat=3 628 629[system.cpu1.fuPool.FUList1.opList1] 630type=OpDesc 631issueLat=19 632opClass=IntDiv 633opLat=20 634 635[system.cpu1.fuPool.FUList2] 636type=FUDesc 637children=opList0 opList1 opList2 638count=4 639opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 640 641[system.cpu1.fuPool.FUList2.opList0] 642type=OpDesc 643issueLat=1 644opClass=FloatAdd 645opLat=2 646 647[system.cpu1.fuPool.FUList2.opList1] 648type=OpDesc 649issueLat=1 650opClass=FloatCmp 651opLat=2 652 653[system.cpu1.fuPool.FUList2.opList2] 654type=OpDesc 655issueLat=1 656opClass=FloatCvt 657opLat=2 658 659[system.cpu1.fuPool.FUList3] 660type=FUDesc 661children=opList0 opList1 opList2 662count=2 663opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 664 665[system.cpu1.fuPool.FUList3.opList0] 666type=OpDesc 667issueLat=1 668opClass=FloatMult 669opLat=4 670 671[system.cpu1.fuPool.FUList3.opList1] 672type=OpDesc 673issueLat=12 674opClass=FloatDiv 675opLat=12 676 677[system.cpu1.fuPool.FUList3.opList2] 678type=OpDesc 679issueLat=24 680opClass=FloatSqrt 681opLat=24 682 683[system.cpu1.fuPool.FUList4] 684type=FUDesc 685children=opList 686count=0 687opList=system.cpu1.fuPool.FUList4.opList 688 689[system.cpu1.fuPool.FUList4.opList] 690type=OpDesc 691issueLat=1 692opClass=MemRead 693opLat=1 694 695[system.cpu1.fuPool.FUList5] 696type=FUDesc 697children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 698count=4 699opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 700 701[system.cpu1.fuPool.FUList5.opList00] 702type=OpDesc 703issueLat=1 704opClass=SimdAdd 705opLat=1 706 707[system.cpu1.fuPool.FUList5.opList01] 708type=OpDesc 709issueLat=1 710opClass=SimdAddAcc 711opLat=1 712 713[system.cpu1.fuPool.FUList5.opList02] 714type=OpDesc 715issueLat=1 716opClass=SimdAlu 717opLat=1 718 719[system.cpu1.fuPool.FUList5.opList03] 720type=OpDesc 721issueLat=1 722opClass=SimdCmp 723opLat=1 724 725[system.cpu1.fuPool.FUList5.opList04] 726type=OpDesc 727issueLat=1 728opClass=SimdCvt 729opLat=1 730 731[system.cpu1.fuPool.FUList5.opList05] 732type=OpDesc 733issueLat=1 734opClass=SimdMisc 735opLat=1 736 737[system.cpu1.fuPool.FUList5.opList06] 738type=OpDesc 739issueLat=1 740opClass=SimdMult 741opLat=1 742 743[system.cpu1.fuPool.FUList5.opList07] 744type=OpDesc 745issueLat=1 746opClass=SimdMultAcc 747opLat=1 748 749[system.cpu1.fuPool.FUList5.opList08] 750type=OpDesc 751issueLat=1 752opClass=SimdShift 753opLat=1 754 755[system.cpu1.fuPool.FUList5.opList09] 756type=OpDesc 757issueLat=1 758opClass=SimdShiftAcc 759opLat=1 760 761[system.cpu1.fuPool.FUList5.opList10] 762type=OpDesc 763issueLat=1 764opClass=SimdSqrt 765opLat=1 766 767[system.cpu1.fuPool.FUList5.opList11] 768type=OpDesc 769issueLat=1 770opClass=SimdFloatAdd 771opLat=1 772 773[system.cpu1.fuPool.FUList5.opList12] 774type=OpDesc 775issueLat=1 776opClass=SimdFloatAlu 777opLat=1 778 779[system.cpu1.fuPool.FUList5.opList13] 780type=OpDesc 781issueLat=1 782opClass=SimdFloatCmp 783opLat=1 784 785[system.cpu1.fuPool.FUList5.opList14] 786type=OpDesc 787issueLat=1 788opClass=SimdFloatCvt 789opLat=1 790 791[system.cpu1.fuPool.FUList5.opList15] 792type=OpDesc 793issueLat=1 794opClass=SimdFloatDiv 795opLat=1 796 797[system.cpu1.fuPool.FUList5.opList16] 798type=OpDesc 799issueLat=1 800opClass=SimdFloatMisc 801opLat=1 802 803[system.cpu1.fuPool.FUList5.opList17] 804type=OpDesc 805issueLat=1 806opClass=SimdFloatMult 807opLat=1 808 809[system.cpu1.fuPool.FUList5.opList18] 810type=OpDesc 811issueLat=1 812opClass=SimdFloatMultAcc 813opLat=1 814 815[system.cpu1.fuPool.FUList5.opList19] 816type=OpDesc 817issueLat=1 818opClass=SimdFloatSqrt 819opLat=1 820 821[system.cpu1.fuPool.FUList6] 822type=FUDesc 823children=opList 824count=0 825opList=system.cpu1.fuPool.FUList6.opList 826 827[system.cpu1.fuPool.FUList6.opList] 828type=OpDesc 829issueLat=1 830opClass=MemWrite 831opLat=1 832 833[system.cpu1.fuPool.FUList7] 834type=FUDesc 835children=opList0 opList1 836count=4 837opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 838 839[system.cpu1.fuPool.FUList7.opList0] 840type=OpDesc 841issueLat=1 842opClass=MemRead 843opLat=1 844 845[system.cpu1.fuPool.FUList7.opList1] 846type=OpDesc 847issueLat=1 848opClass=MemWrite 849opLat=1 850 851[system.cpu1.fuPool.FUList8] 852type=FUDesc 853children=opList 854count=1 855opList=system.cpu1.fuPool.FUList8.opList 856 857[system.cpu1.fuPool.FUList8.opList] 858type=OpDesc 859issueLat=3 860opClass=IprAccess 861opLat=3 862 863[system.cpu1.icache] 864type=BaseCache 865addr_range=0:18446744073709551615 866assoc=1 867block_size=64 868forward_snoops=true 869hash_delay=1 870is_top_level=true 871latency=1000 872max_miss_count=0 873mshrs=4 874prefetch_on_access=false 875prefetcher=Null 876prioritizeRequests=false 877repl=Null 878size=32768 879subblock_size=0 880system=system 881tgts_per_mshr=20 882trace_addr=0 883two_queue=false 884write_buffers=8 885cpu_side=system.cpu1.icache_port 886mem_side=system.toL2Bus.port[3] 887 888[system.cpu1.interrupts] 889type=SparcInterrupts 890 891[system.cpu1.itb] 892type=SparcTLB 893size=64 894 895[system.cpu1.tracer] 896type=ExeTracer 897 898[system.cpu2] 899type=DerivO3CPU 900children=dcache dtb fuPool icache interrupts itb tracer 901BTBEntries=4096 902BTBTagSize=16 903LFSTSize=1024 904LQEntries=32 905LSQCheckLoads=true 906LSQDepCheckShift=4 907RASSize=16 908SQEntries=32 909SSITSize=1024 910activity=0 911backComSize=5 912cachePorts=200 913checker=Null 914choiceCtrBits=2 915choicePredictorSize=8192 916clock=500 917commitToDecodeDelay=1 918commitToFetchDelay=1 919commitToIEWDelay=1 920commitToRenameDelay=1 921commitWidth=8 922cpu_id=2 923decodeToFetchDelay=1 924decodeToRenameDelay=1 925decodeWidth=8 926defer_registration=false 927dispatchWidth=8 928do_checkpoint_insts=true 929do_quiesce=true 930do_statistics_insts=true 931dtb=system.cpu2.dtb 932fetchToDecodeDelay=1 933fetchTrapLatency=1 934fetchWidth=8 935forwardComSize=5 936fuPool=system.cpu2.fuPool 937function_trace=false 938function_trace_start=0 939globalCtrBits=2 940globalHistoryBits=13 941globalPredictorSize=8192 942iewToCommitDelay=1 943iewToDecodeDelay=1 944iewToFetchDelay=1 945iewToRenameDelay=1 946instShiftAmt=2 947interrupts=system.cpu2.interrupts 948issueToExecuteDelay=1 949issueWidth=8 950itb=system.cpu2.itb 951localCtrBits=2 952localHistoryBits=11 953localHistoryTableSize=2048 954localPredictorSize=2048 955max_insts_all_threads=0 956max_insts_any_thread=0 957max_loads_all_threads=0 958max_loads_any_thread=0 959needsTSO=false 960numIQEntries=64 961numPhysFloatRegs=256 962numPhysIntRegs=256 963numROBEntries=192 964numRobs=1 965numThreads=1 966phase=0 967predType=tournament 968profile=0 969progress_interval=0 970renameToDecodeDelay=1 971renameToFetchDelay=1 972renameToIEWDelay=2 973renameToROBDelay=1 974renameWidth=8 975smtCommitPolicy=RoundRobin 976smtFetchPolicy=SingleThread 977smtIQPolicy=Partitioned 978smtIQThreshold=100 979smtLSQPolicy=Partitioned 980smtLSQThreshold=100 981smtNumFetchingThreads=1 982smtROBPolicy=Partitioned 983smtROBThreshold=100 984squashWidth=8 985store_set_clear_period=250000 986system=system 987tracer=system.cpu2.tracer 988trapLatency=13 989wbDepth=1 990wbWidth=8 991workload=system.cpu0.workload 992dcache_port=system.cpu2.dcache.cpu_side 993icache_port=system.cpu2.icache.cpu_side 994 995[system.cpu2.dcache] 996type=BaseCache 997addr_range=0:18446744073709551615 998assoc=4 999block_size=64 1000forward_snoops=true 1001hash_delay=1 1002is_top_level=true 1003latency=1000 1004max_miss_count=0 1005mshrs=4 1006prefetch_on_access=false 1007prefetcher=Null 1008prioritizeRequests=false 1009repl=Null 1010size=32768 1011subblock_size=0 1012system=system 1013tgts_per_mshr=20 1014trace_addr=0 1015two_queue=false 1016write_buffers=8 1017cpu_side=system.cpu2.dcache_port 1018mem_side=system.toL2Bus.port[6] 1019 1020[system.cpu2.dtb] 1021type=SparcTLB 1022size=64 1023 1024[system.cpu2.fuPool] 1025type=FUPool 1026children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1027FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1028 1029[system.cpu2.fuPool.FUList0] 1030type=FUDesc 1031children=opList 1032count=6 1033opList=system.cpu2.fuPool.FUList0.opList 1034 1035[system.cpu2.fuPool.FUList0.opList] 1036type=OpDesc 1037issueLat=1 1038opClass=IntAlu 1039opLat=1 1040 1041[system.cpu2.fuPool.FUList1] 1042type=FUDesc 1043children=opList0 opList1 1044count=2 1045opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1046 1047[system.cpu2.fuPool.FUList1.opList0] 1048type=OpDesc 1049issueLat=1 1050opClass=IntMult 1051opLat=3 1052 1053[system.cpu2.fuPool.FUList1.opList1] 1054type=OpDesc 1055issueLat=19 1056opClass=IntDiv 1057opLat=20 1058 1059[system.cpu2.fuPool.FUList2] 1060type=FUDesc 1061children=opList0 opList1 opList2 1062count=4 1063opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1064 1065[system.cpu2.fuPool.FUList2.opList0] 1066type=OpDesc 1067issueLat=1 1068opClass=FloatAdd 1069opLat=2 1070 1071[system.cpu2.fuPool.FUList2.opList1] 1072type=OpDesc 1073issueLat=1 1074opClass=FloatCmp 1075opLat=2 1076 1077[system.cpu2.fuPool.FUList2.opList2] 1078type=OpDesc 1079issueLat=1 1080opClass=FloatCvt 1081opLat=2 1082 1083[system.cpu2.fuPool.FUList3] 1084type=FUDesc 1085children=opList0 opList1 opList2 1086count=2 1087opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1088 1089[system.cpu2.fuPool.FUList3.opList0] 1090type=OpDesc 1091issueLat=1 1092opClass=FloatMult 1093opLat=4 1094 1095[system.cpu2.fuPool.FUList3.opList1] 1096type=OpDesc 1097issueLat=12 1098opClass=FloatDiv 1099opLat=12 1100 1101[system.cpu2.fuPool.FUList3.opList2] 1102type=OpDesc 1103issueLat=24 1104opClass=FloatSqrt 1105opLat=24 1106 1107[system.cpu2.fuPool.FUList4] 1108type=FUDesc 1109children=opList 1110count=0 1111opList=system.cpu2.fuPool.FUList4.opList 1112 1113[system.cpu2.fuPool.FUList4.opList] 1114type=OpDesc 1115issueLat=1 1116opClass=MemRead 1117opLat=1 1118 1119[system.cpu2.fuPool.FUList5] 1120type=FUDesc 1121children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1122count=4 1123opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1124 1125[system.cpu2.fuPool.FUList5.opList00] 1126type=OpDesc 1127issueLat=1 1128opClass=SimdAdd 1129opLat=1 1130 1131[system.cpu2.fuPool.FUList5.opList01] 1132type=OpDesc 1133issueLat=1 1134opClass=SimdAddAcc 1135opLat=1 1136 1137[system.cpu2.fuPool.FUList5.opList02] 1138type=OpDesc 1139issueLat=1 1140opClass=SimdAlu 1141opLat=1 1142 1143[system.cpu2.fuPool.FUList5.opList03] 1144type=OpDesc 1145issueLat=1 1146opClass=SimdCmp 1147opLat=1 1148 1149[system.cpu2.fuPool.FUList5.opList04] 1150type=OpDesc 1151issueLat=1 1152opClass=SimdCvt 1153opLat=1 1154 1155[system.cpu2.fuPool.FUList5.opList05] 1156type=OpDesc 1157issueLat=1 1158opClass=SimdMisc 1159opLat=1 1160 1161[system.cpu2.fuPool.FUList5.opList06] 1162type=OpDesc 1163issueLat=1 1164opClass=SimdMult 1165opLat=1 1166 1167[system.cpu2.fuPool.FUList5.opList07] 1168type=OpDesc 1169issueLat=1 1170opClass=SimdMultAcc 1171opLat=1 1172 1173[system.cpu2.fuPool.FUList5.opList08] 1174type=OpDesc 1175issueLat=1 1176opClass=SimdShift 1177opLat=1 1178 1179[system.cpu2.fuPool.FUList5.opList09] 1180type=OpDesc 1181issueLat=1 1182opClass=SimdShiftAcc 1183opLat=1 1184 1185[system.cpu2.fuPool.FUList5.opList10] 1186type=OpDesc 1187issueLat=1 1188opClass=SimdSqrt 1189opLat=1 1190 1191[system.cpu2.fuPool.FUList5.opList11] 1192type=OpDesc 1193issueLat=1 1194opClass=SimdFloatAdd 1195opLat=1 1196 1197[system.cpu2.fuPool.FUList5.opList12] 1198type=OpDesc 1199issueLat=1 1200opClass=SimdFloatAlu 1201opLat=1 1202 1203[system.cpu2.fuPool.FUList5.opList13] 1204type=OpDesc 1205issueLat=1 1206opClass=SimdFloatCmp 1207opLat=1 1208 1209[system.cpu2.fuPool.FUList5.opList14] 1210type=OpDesc 1211issueLat=1 1212opClass=SimdFloatCvt 1213opLat=1 1214 1215[system.cpu2.fuPool.FUList5.opList15] 1216type=OpDesc 1217issueLat=1 1218opClass=SimdFloatDiv 1219opLat=1 1220 1221[system.cpu2.fuPool.FUList5.opList16] 1222type=OpDesc 1223issueLat=1 1224opClass=SimdFloatMisc 1225opLat=1 1226 1227[system.cpu2.fuPool.FUList5.opList17] 1228type=OpDesc 1229issueLat=1 1230opClass=SimdFloatMult 1231opLat=1 1232 1233[system.cpu2.fuPool.FUList5.opList18] 1234type=OpDesc 1235issueLat=1 1236opClass=SimdFloatMultAcc 1237opLat=1 1238 1239[system.cpu2.fuPool.FUList5.opList19] 1240type=OpDesc 1241issueLat=1 1242opClass=SimdFloatSqrt 1243opLat=1 1244 1245[system.cpu2.fuPool.FUList6] 1246type=FUDesc 1247children=opList 1248count=0 1249opList=system.cpu2.fuPool.FUList6.opList 1250 1251[system.cpu2.fuPool.FUList6.opList] 1252type=OpDesc 1253issueLat=1 1254opClass=MemWrite 1255opLat=1 1256 1257[system.cpu2.fuPool.FUList7] 1258type=FUDesc 1259children=opList0 opList1 1260count=4 1261opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1262 1263[system.cpu2.fuPool.FUList7.opList0] 1264type=OpDesc 1265issueLat=1 1266opClass=MemRead 1267opLat=1 1268 1269[system.cpu2.fuPool.FUList7.opList1] 1270type=OpDesc 1271issueLat=1 1272opClass=MemWrite 1273opLat=1 1274 1275[system.cpu2.fuPool.FUList8] 1276type=FUDesc 1277children=opList 1278count=1 1279opList=system.cpu2.fuPool.FUList8.opList 1280 1281[system.cpu2.fuPool.FUList8.opList] 1282type=OpDesc 1283issueLat=3 1284opClass=IprAccess 1285opLat=3 1286 1287[system.cpu2.icache] 1288type=BaseCache 1289addr_range=0:18446744073709551615 1290assoc=1 1291block_size=64 1292forward_snoops=true 1293hash_delay=1 1294is_top_level=true 1295latency=1000 1296max_miss_count=0 1297mshrs=4 1298prefetch_on_access=false 1299prefetcher=Null 1300prioritizeRequests=false 1301repl=Null 1302size=32768 1303subblock_size=0 1304system=system 1305tgts_per_mshr=20 1306trace_addr=0 1307two_queue=false 1308write_buffers=8 1309cpu_side=system.cpu2.icache_port 1310mem_side=system.toL2Bus.port[5] 1311 1312[system.cpu2.interrupts] 1313type=SparcInterrupts 1314 1315[system.cpu2.itb] 1316type=SparcTLB 1317size=64 1318 1319[system.cpu2.tracer] 1320type=ExeTracer 1321 1322[system.cpu3] 1323type=DerivO3CPU 1324children=dcache dtb fuPool icache interrupts itb tracer 1325BTBEntries=4096 1326BTBTagSize=16 1327LFSTSize=1024 1328LQEntries=32 1329LSQCheckLoads=true 1330LSQDepCheckShift=4 1331RASSize=16 1332SQEntries=32 1333SSITSize=1024 1334activity=0 1335backComSize=5 1336cachePorts=200 1337checker=Null 1338choiceCtrBits=2 1339choicePredictorSize=8192 1340clock=500 1341commitToDecodeDelay=1 1342commitToFetchDelay=1 1343commitToIEWDelay=1 1344commitToRenameDelay=1 1345commitWidth=8 1346cpu_id=3 1347decodeToFetchDelay=1 1348decodeToRenameDelay=1 1349decodeWidth=8 1350defer_registration=false 1351dispatchWidth=8 1352do_checkpoint_insts=true 1353do_quiesce=true 1354do_statistics_insts=true 1355dtb=system.cpu3.dtb 1356fetchToDecodeDelay=1 1357fetchTrapLatency=1 1358fetchWidth=8 1359forwardComSize=5 1360fuPool=system.cpu3.fuPool 1361function_trace=false 1362function_trace_start=0 1363globalCtrBits=2 1364globalHistoryBits=13 1365globalPredictorSize=8192 1366iewToCommitDelay=1 1367iewToDecodeDelay=1 1368iewToFetchDelay=1 1369iewToRenameDelay=1 1370instShiftAmt=2 1371interrupts=system.cpu3.interrupts 1372issueToExecuteDelay=1 1373issueWidth=8 1374itb=system.cpu3.itb 1375localCtrBits=2 1376localHistoryBits=11 1377localHistoryTableSize=2048 1378localPredictorSize=2048 1379max_insts_all_threads=0 1380max_insts_any_thread=0 1381max_loads_all_threads=0 1382max_loads_any_thread=0 1383needsTSO=false 1384numIQEntries=64 1385numPhysFloatRegs=256 1386numPhysIntRegs=256 1387numROBEntries=192 1388numRobs=1 1389numThreads=1 1390phase=0 1391predType=tournament 1392profile=0 1393progress_interval=0 1394renameToDecodeDelay=1 1395renameToFetchDelay=1 1396renameToIEWDelay=2 1397renameToROBDelay=1 1398renameWidth=8 1399smtCommitPolicy=RoundRobin 1400smtFetchPolicy=SingleThread 1401smtIQPolicy=Partitioned 1402smtIQThreshold=100 1403smtLSQPolicy=Partitioned 1404smtLSQThreshold=100 1405smtNumFetchingThreads=1 1406smtROBPolicy=Partitioned 1407smtROBThreshold=100 1408squashWidth=8 1409store_set_clear_period=250000 1410system=system 1411tracer=system.cpu3.tracer 1412trapLatency=13 1413wbDepth=1 1414wbWidth=8 1415workload=system.cpu0.workload 1416dcache_port=system.cpu3.dcache.cpu_side 1417icache_port=system.cpu3.icache.cpu_side 1418 1419[system.cpu3.dcache] 1420type=BaseCache 1421addr_range=0:18446744073709551615 1422assoc=4 1423block_size=64 1424forward_snoops=true 1425hash_delay=1 1426is_top_level=true 1427latency=1000 1428max_miss_count=0 1429mshrs=4 1430prefetch_on_access=false 1431prefetcher=Null 1432prioritizeRequests=false 1433repl=Null 1434size=32768 1435subblock_size=0 1436system=system 1437tgts_per_mshr=20 1438trace_addr=0 1439two_queue=false 1440write_buffers=8 1441cpu_side=system.cpu3.dcache_port 1442mem_side=system.toL2Bus.port[8] 1443 1444[system.cpu3.dtb] 1445type=SparcTLB 1446size=64 1447 1448[system.cpu3.fuPool] 1449type=FUPool 1450children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1451FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1452 1453[system.cpu3.fuPool.FUList0] 1454type=FUDesc 1455children=opList 1456count=6 1457opList=system.cpu3.fuPool.FUList0.opList 1458 1459[system.cpu3.fuPool.FUList0.opList] 1460type=OpDesc 1461issueLat=1 1462opClass=IntAlu 1463opLat=1 1464 1465[system.cpu3.fuPool.FUList1] 1466type=FUDesc 1467children=opList0 opList1 1468count=2 1469opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1470 1471[system.cpu3.fuPool.FUList1.opList0] 1472type=OpDesc 1473issueLat=1 1474opClass=IntMult 1475opLat=3 1476 1477[system.cpu3.fuPool.FUList1.opList1] 1478type=OpDesc 1479issueLat=19 1480opClass=IntDiv 1481opLat=20 1482 1483[system.cpu3.fuPool.FUList2] 1484type=FUDesc 1485children=opList0 opList1 opList2 1486count=4 1487opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1488 1489[system.cpu3.fuPool.FUList2.opList0] 1490type=OpDesc 1491issueLat=1 1492opClass=FloatAdd 1493opLat=2 1494 1495[system.cpu3.fuPool.FUList2.opList1] 1496type=OpDesc 1497issueLat=1 1498opClass=FloatCmp 1499opLat=2 1500 1501[system.cpu3.fuPool.FUList2.opList2] 1502type=OpDesc 1503issueLat=1 1504opClass=FloatCvt 1505opLat=2 1506 1507[system.cpu3.fuPool.FUList3] 1508type=FUDesc 1509children=opList0 opList1 opList2 1510count=2 1511opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1512 1513[system.cpu3.fuPool.FUList3.opList0] 1514type=OpDesc 1515issueLat=1 1516opClass=FloatMult 1517opLat=4 1518 1519[system.cpu3.fuPool.FUList3.opList1] 1520type=OpDesc 1521issueLat=12 1522opClass=FloatDiv 1523opLat=12 1524 1525[system.cpu3.fuPool.FUList3.opList2] 1526type=OpDesc 1527issueLat=24 1528opClass=FloatSqrt 1529opLat=24 1530 1531[system.cpu3.fuPool.FUList4] 1532type=FUDesc 1533children=opList 1534count=0 1535opList=system.cpu3.fuPool.FUList4.opList 1536 1537[system.cpu3.fuPool.FUList4.opList] 1538type=OpDesc 1539issueLat=1 1540opClass=MemRead 1541opLat=1 1542 1543[system.cpu3.fuPool.FUList5] 1544type=FUDesc 1545children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1546count=4 1547opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1548 1549[system.cpu3.fuPool.FUList5.opList00] 1550type=OpDesc 1551issueLat=1 1552opClass=SimdAdd 1553opLat=1 1554 1555[system.cpu3.fuPool.FUList5.opList01] 1556type=OpDesc 1557issueLat=1 1558opClass=SimdAddAcc 1559opLat=1 1560 1561[system.cpu3.fuPool.FUList5.opList02] 1562type=OpDesc 1563issueLat=1 1564opClass=SimdAlu 1565opLat=1 1566 1567[system.cpu3.fuPool.FUList5.opList03] 1568type=OpDesc 1569issueLat=1 1570opClass=SimdCmp 1571opLat=1 1572 1573[system.cpu3.fuPool.FUList5.opList04] 1574type=OpDesc 1575issueLat=1 1576opClass=SimdCvt 1577opLat=1 1578 1579[system.cpu3.fuPool.FUList5.opList05] 1580type=OpDesc 1581issueLat=1 1582opClass=SimdMisc 1583opLat=1 1584 1585[system.cpu3.fuPool.FUList5.opList06] 1586type=OpDesc 1587issueLat=1 1588opClass=SimdMult 1589opLat=1 1590 1591[system.cpu3.fuPool.FUList5.opList07] 1592type=OpDesc 1593issueLat=1 1594opClass=SimdMultAcc 1595opLat=1 1596 1597[system.cpu3.fuPool.FUList5.opList08] 1598type=OpDesc 1599issueLat=1 1600opClass=SimdShift 1601opLat=1 1602 1603[system.cpu3.fuPool.FUList5.opList09] 1604type=OpDesc 1605issueLat=1 1606opClass=SimdShiftAcc 1607opLat=1 1608 1609[system.cpu3.fuPool.FUList5.opList10] 1610type=OpDesc 1611issueLat=1 1612opClass=SimdSqrt 1613opLat=1 1614 1615[system.cpu3.fuPool.FUList5.opList11] 1616type=OpDesc 1617issueLat=1 1618opClass=SimdFloatAdd 1619opLat=1 1620 1621[system.cpu3.fuPool.FUList5.opList12] 1622type=OpDesc 1623issueLat=1 1624opClass=SimdFloatAlu 1625opLat=1 1626 1627[system.cpu3.fuPool.FUList5.opList13] 1628type=OpDesc 1629issueLat=1 1630opClass=SimdFloatCmp 1631opLat=1 1632 1633[system.cpu3.fuPool.FUList5.opList14] 1634type=OpDesc 1635issueLat=1 1636opClass=SimdFloatCvt 1637opLat=1 1638 1639[system.cpu3.fuPool.FUList5.opList15] 1640type=OpDesc 1641issueLat=1 1642opClass=SimdFloatDiv 1643opLat=1 1644 1645[system.cpu3.fuPool.FUList5.opList16] 1646type=OpDesc 1647issueLat=1 1648opClass=SimdFloatMisc 1649opLat=1 1650 1651[system.cpu3.fuPool.FUList5.opList17] 1652type=OpDesc 1653issueLat=1 1654opClass=SimdFloatMult 1655opLat=1 1656 1657[system.cpu3.fuPool.FUList5.opList18] 1658type=OpDesc 1659issueLat=1 1660opClass=SimdFloatMultAcc 1661opLat=1 1662 1663[system.cpu3.fuPool.FUList5.opList19] 1664type=OpDesc 1665issueLat=1 1666opClass=SimdFloatSqrt 1667opLat=1 1668 1669[system.cpu3.fuPool.FUList6] 1670type=FUDesc 1671children=opList 1672count=0 1673opList=system.cpu3.fuPool.FUList6.opList 1674 1675[system.cpu3.fuPool.FUList6.opList] 1676type=OpDesc 1677issueLat=1 1678opClass=MemWrite 1679opLat=1 1680 1681[system.cpu3.fuPool.FUList7] 1682type=FUDesc 1683children=opList0 opList1 1684count=4 1685opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1686 1687[system.cpu3.fuPool.FUList7.opList0] 1688type=OpDesc 1689issueLat=1 1690opClass=MemRead 1691opLat=1 1692 1693[system.cpu3.fuPool.FUList7.opList1] 1694type=OpDesc 1695issueLat=1 1696opClass=MemWrite 1697opLat=1 1698 1699[system.cpu3.fuPool.FUList8] 1700type=FUDesc 1701children=opList 1702count=1 1703opList=system.cpu3.fuPool.FUList8.opList 1704 1705[system.cpu3.fuPool.FUList8.opList] 1706type=OpDesc 1707issueLat=3 1708opClass=IprAccess 1709opLat=3 1710 1711[system.cpu3.icache] 1712type=BaseCache 1713addr_range=0:18446744073709551615 1714assoc=1 1715block_size=64 1716forward_snoops=true 1717hash_delay=1 1718is_top_level=true 1719latency=1000 1720max_miss_count=0 1721mshrs=4 1722prefetch_on_access=false 1723prefetcher=Null 1724prioritizeRequests=false 1725repl=Null 1726size=32768 1727subblock_size=0 1728system=system 1729tgts_per_mshr=20 1730trace_addr=0 1731two_queue=false 1732write_buffers=8 1733cpu_side=system.cpu3.icache_port 1734mem_side=system.toL2Bus.port[7] 1735 1736[system.cpu3.interrupts] 1737type=SparcInterrupts 1738 1739[system.cpu3.itb] 1740type=SparcTLB 1741size=64 1742 1743[system.cpu3.tracer] 1744type=ExeTracer 1745 1746[system.l2c] 1747type=BaseCache 1748addr_range=0:18446744073709551615 1749assoc=8 1750block_size=64 1751forward_snoops=true 1752hash_delay=1 1753is_top_level=false 1754latency=10000 1755max_miss_count=0 1756mshrs=92 1757prefetch_on_access=false 1758prefetcher=Null 1759prioritizeRequests=false 1760repl=Null 1761size=4194304 1762subblock_size=0 1763system=system 1764tgts_per_mshr=16 1765trace_addr=0 1766two_queue=false 1767write_buffers=8 1768cpu_side=system.toL2Bus.port[0] 1769mem_side=system.membus.port[0] 1770 1771[system.membus] 1772type=Bus 1773block_size=64 1774bus_id=0 1775clock=1000 1776header_cycles=1 1777use_default_range=false 1778width=64 1779port=system.l2c.mem_side system.physmem.port[0] system.system_port 1780 1781[system.physmem] 1782type=PhysicalMemory 1783file= 1784latency=30000 1785latency_var=0 1786null=false 1787range=0:134217727 1788zero=false 1789port=system.membus.port[1] 1790 1791[system.toL2Bus] 1792type=Bus 1793block_size=64 1794bus_id=0 1795clock=1000 1796header_cycles=1 1797use_default_range=false 1798width=64 1799port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1800 1801