config.ini revision 8802:ef66a9083bc4
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus 11mem_mode=timing 12memories=system.physmem 13num_work_ids=16 14physmem=system.physmem 15work_begin_ckpt_count=0 16work_begin_cpu_id_exit=-1 17work_begin_exit_count=0 18work_cpus_ckpt_count=0 19work_end_ckpt_count=0 20work_end_exit_count=0 21work_item_id=-1 22system_port=system.membus.port[2] 23 24[system.cpu0] 25type=DerivO3CPU 26children=dcache dtb fuPool icache itb tracer workload 27BTBEntries=4096 28BTBTagSize=16 29LFSTSize=1024 30LQEntries=32 31LSQCheckLoads=true 32LSQDepCheckShift=4 33RASSize=16 34SQEntries=32 35SSITSize=1024 36activity=0 37backComSize=5 38cachePorts=200 39checker=Null 40choiceCtrBits=2 41choicePredictorSize=8192 42clock=500 43commitToDecodeDelay=1 44commitToFetchDelay=1 45commitToIEWDelay=1 46commitToRenameDelay=1 47commitWidth=8 48cpu_id=0 49decodeToFetchDelay=1 50decodeToRenameDelay=1 51decodeWidth=8 52defer_registration=false 53dispatchWidth=8 54do_checkpoint_insts=true 55do_statistics_insts=true 56dtb=system.cpu0.dtb 57fetchToDecodeDelay=1 58fetchTrapLatency=1 59fetchWidth=8 60forwardComSize=5 61fuPool=system.cpu0.fuPool 62function_trace=false 63function_trace_start=0 64globalCtrBits=2 65globalHistoryBits=13 66globalPredictorSize=8192 67iewToCommitDelay=1 68iewToDecodeDelay=1 69iewToFetchDelay=1 70iewToRenameDelay=1 71instShiftAmt=2 72issueToExecuteDelay=1 73issueWidth=8 74itb=system.cpu0.itb 75localCtrBits=2 76localHistoryBits=11 77localHistoryTableSize=2048 78localPredictorSize=2048 79max_insts_all_threads=0 80max_insts_any_thread=0 81max_loads_all_threads=0 82max_loads_any_thread=0 83numIQEntries=64 84numPhysFloatRegs=256 85numPhysIntRegs=256 86numROBEntries=192 87numRobs=1 88numThreads=1 89phase=0 90predType=tournament 91progress_interval=0 92renameToDecodeDelay=1 93renameToFetchDelay=1 94renameToIEWDelay=2 95renameToROBDelay=1 96renameWidth=8 97smtCommitPolicy=RoundRobin 98smtFetchPolicy=SingleThread 99smtIQPolicy=Partitioned 100smtIQThreshold=100 101smtLSQPolicy=Partitioned 102smtLSQThreshold=100 103smtNumFetchingThreads=1 104smtROBPolicy=Partitioned 105smtROBThreshold=100 106squashWidth=8 107store_set_clear_period=250000 108system=system 109tracer=system.cpu0.tracer 110trapLatency=13 111wbDepth=1 112wbWidth=8 113workload=system.cpu0.workload 114dcache_port=system.cpu0.dcache.cpu_side 115icache_port=system.cpu0.icache.cpu_side 116 117[system.cpu0.dcache] 118type=BaseCache 119addr_range=0:18446744073709551615 120assoc=4 121block_size=64 122forward_snoops=true 123hash_delay=1 124is_top_level=true 125latency=1000 126max_miss_count=0 127mshrs=4 128num_cpus=1 129prefetch_data_accesses_only=false 130prefetch_degree=1 131prefetch_latency=10000 132prefetch_on_access=false 133prefetch_past_page=false 134prefetch_policy=none 135prefetch_serial_squash=false 136prefetch_use_cpu_id=true 137prefetcher_size=100 138prioritizeRequests=false 139repl=Null 140size=32768 141subblock_size=0 142tgts_per_mshr=20 143trace_addr=0 144two_queue=false 145write_buffers=8 146cpu_side=system.cpu0.dcache_port 147mem_side=system.toL2Bus.port[2] 148 149[system.cpu0.dtb] 150type=SparcTLB 151size=64 152 153[system.cpu0.fuPool] 154type=FUPool 155children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 156FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 157 158[system.cpu0.fuPool.FUList0] 159type=FUDesc 160children=opList 161count=6 162opList=system.cpu0.fuPool.FUList0.opList 163 164[system.cpu0.fuPool.FUList0.opList] 165type=OpDesc 166issueLat=1 167opClass=IntAlu 168opLat=1 169 170[system.cpu0.fuPool.FUList1] 171type=FUDesc 172children=opList0 opList1 173count=2 174opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 175 176[system.cpu0.fuPool.FUList1.opList0] 177type=OpDesc 178issueLat=1 179opClass=IntMult 180opLat=3 181 182[system.cpu0.fuPool.FUList1.opList1] 183type=OpDesc 184issueLat=19 185opClass=IntDiv 186opLat=20 187 188[system.cpu0.fuPool.FUList2] 189type=FUDesc 190children=opList0 opList1 opList2 191count=4 192opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 193 194[system.cpu0.fuPool.FUList2.opList0] 195type=OpDesc 196issueLat=1 197opClass=FloatAdd 198opLat=2 199 200[system.cpu0.fuPool.FUList2.opList1] 201type=OpDesc 202issueLat=1 203opClass=FloatCmp 204opLat=2 205 206[system.cpu0.fuPool.FUList2.opList2] 207type=OpDesc 208issueLat=1 209opClass=FloatCvt 210opLat=2 211 212[system.cpu0.fuPool.FUList3] 213type=FUDesc 214children=opList0 opList1 opList2 215count=2 216opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 217 218[system.cpu0.fuPool.FUList3.opList0] 219type=OpDesc 220issueLat=1 221opClass=FloatMult 222opLat=4 223 224[system.cpu0.fuPool.FUList3.opList1] 225type=OpDesc 226issueLat=12 227opClass=FloatDiv 228opLat=12 229 230[system.cpu0.fuPool.FUList3.opList2] 231type=OpDesc 232issueLat=24 233opClass=FloatSqrt 234opLat=24 235 236[system.cpu0.fuPool.FUList4] 237type=FUDesc 238children=opList 239count=0 240opList=system.cpu0.fuPool.FUList4.opList 241 242[system.cpu0.fuPool.FUList4.opList] 243type=OpDesc 244issueLat=1 245opClass=MemRead 246opLat=1 247 248[system.cpu0.fuPool.FUList5] 249type=FUDesc 250children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 251count=4 252opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 253 254[system.cpu0.fuPool.FUList5.opList00] 255type=OpDesc 256issueLat=1 257opClass=SimdAdd 258opLat=1 259 260[system.cpu0.fuPool.FUList5.opList01] 261type=OpDesc 262issueLat=1 263opClass=SimdAddAcc 264opLat=1 265 266[system.cpu0.fuPool.FUList5.opList02] 267type=OpDesc 268issueLat=1 269opClass=SimdAlu 270opLat=1 271 272[system.cpu0.fuPool.FUList5.opList03] 273type=OpDesc 274issueLat=1 275opClass=SimdCmp 276opLat=1 277 278[system.cpu0.fuPool.FUList5.opList04] 279type=OpDesc 280issueLat=1 281opClass=SimdCvt 282opLat=1 283 284[system.cpu0.fuPool.FUList5.opList05] 285type=OpDesc 286issueLat=1 287opClass=SimdMisc 288opLat=1 289 290[system.cpu0.fuPool.FUList5.opList06] 291type=OpDesc 292issueLat=1 293opClass=SimdMult 294opLat=1 295 296[system.cpu0.fuPool.FUList5.opList07] 297type=OpDesc 298issueLat=1 299opClass=SimdMultAcc 300opLat=1 301 302[system.cpu0.fuPool.FUList5.opList08] 303type=OpDesc 304issueLat=1 305opClass=SimdShift 306opLat=1 307 308[system.cpu0.fuPool.FUList5.opList09] 309type=OpDesc 310issueLat=1 311opClass=SimdShiftAcc 312opLat=1 313 314[system.cpu0.fuPool.FUList5.opList10] 315type=OpDesc 316issueLat=1 317opClass=SimdSqrt 318opLat=1 319 320[system.cpu0.fuPool.FUList5.opList11] 321type=OpDesc 322issueLat=1 323opClass=SimdFloatAdd 324opLat=1 325 326[system.cpu0.fuPool.FUList5.opList12] 327type=OpDesc 328issueLat=1 329opClass=SimdFloatAlu 330opLat=1 331 332[system.cpu0.fuPool.FUList5.opList13] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatCmp 336opLat=1 337 338[system.cpu0.fuPool.FUList5.opList14] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatCvt 342opLat=1 343 344[system.cpu0.fuPool.FUList5.opList15] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatDiv 348opLat=1 349 350[system.cpu0.fuPool.FUList5.opList16] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatMisc 354opLat=1 355 356[system.cpu0.fuPool.FUList5.opList17] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatMult 360opLat=1 361 362[system.cpu0.fuPool.FUList5.opList18] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatMultAcc 366opLat=1 367 368[system.cpu0.fuPool.FUList5.opList19] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatSqrt 372opLat=1 373 374[system.cpu0.fuPool.FUList6] 375type=FUDesc 376children=opList 377count=0 378opList=system.cpu0.fuPool.FUList6.opList 379 380[system.cpu0.fuPool.FUList6.opList] 381type=OpDesc 382issueLat=1 383opClass=MemWrite 384opLat=1 385 386[system.cpu0.fuPool.FUList7] 387type=FUDesc 388children=opList0 opList1 389count=4 390opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 391 392[system.cpu0.fuPool.FUList7.opList0] 393type=OpDesc 394issueLat=1 395opClass=MemRead 396opLat=1 397 398[system.cpu0.fuPool.FUList7.opList1] 399type=OpDesc 400issueLat=1 401opClass=MemWrite 402opLat=1 403 404[system.cpu0.fuPool.FUList8] 405type=FUDesc 406children=opList 407count=1 408opList=system.cpu0.fuPool.FUList8.opList 409 410[system.cpu0.fuPool.FUList8.opList] 411type=OpDesc 412issueLat=3 413opClass=IprAccess 414opLat=3 415 416[system.cpu0.icache] 417type=BaseCache 418addr_range=0:18446744073709551615 419assoc=1 420block_size=64 421forward_snoops=true 422hash_delay=1 423is_top_level=true 424latency=1000 425max_miss_count=0 426mshrs=4 427num_cpus=1 428prefetch_data_accesses_only=false 429prefetch_degree=1 430prefetch_latency=10000 431prefetch_on_access=false 432prefetch_past_page=false 433prefetch_policy=none 434prefetch_serial_squash=false 435prefetch_use_cpu_id=true 436prefetcher_size=100 437prioritizeRequests=false 438repl=Null 439size=32768 440subblock_size=0 441tgts_per_mshr=20 442trace_addr=0 443two_queue=false 444write_buffers=8 445cpu_side=system.cpu0.icache_port 446mem_side=system.toL2Bus.port[1] 447 448[system.cpu0.itb] 449type=SparcTLB 450size=64 451 452[system.cpu0.tracer] 453type=ExeTracer 454 455[system.cpu0.workload] 456type=LiveProcess 457cmd=test_atomic 4 458cwd= 459egid=100 460env= 461errout=cerr 462euid=100 463executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic 464gid=100 465input=cin 466max_stack_size=67108864 467output=cout 468pid=100 469ppid=99 470simpoint=0 471system=system 472uid=100 473 474[system.cpu1] 475type=DerivO3CPU 476children=dcache dtb fuPool icache itb tracer 477BTBEntries=4096 478BTBTagSize=16 479LFSTSize=1024 480LQEntries=32 481LSQCheckLoads=true 482LSQDepCheckShift=4 483RASSize=16 484SQEntries=32 485SSITSize=1024 486activity=0 487backComSize=5 488cachePorts=200 489checker=Null 490choiceCtrBits=2 491choicePredictorSize=8192 492clock=500 493commitToDecodeDelay=1 494commitToFetchDelay=1 495commitToIEWDelay=1 496commitToRenameDelay=1 497commitWidth=8 498cpu_id=1 499decodeToFetchDelay=1 500decodeToRenameDelay=1 501decodeWidth=8 502defer_registration=false 503dispatchWidth=8 504do_checkpoint_insts=true 505do_statistics_insts=true 506dtb=system.cpu1.dtb 507fetchToDecodeDelay=1 508fetchTrapLatency=1 509fetchWidth=8 510forwardComSize=5 511fuPool=system.cpu1.fuPool 512function_trace=false 513function_trace_start=0 514globalCtrBits=2 515globalHistoryBits=13 516globalPredictorSize=8192 517iewToCommitDelay=1 518iewToDecodeDelay=1 519iewToFetchDelay=1 520iewToRenameDelay=1 521instShiftAmt=2 522issueToExecuteDelay=1 523issueWidth=8 524itb=system.cpu1.itb 525localCtrBits=2 526localHistoryBits=11 527localHistoryTableSize=2048 528localPredictorSize=2048 529max_insts_all_threads=0 530max_insts_any_thread=0 531max_loads_all_threads=0 532max_loads_any_thread=0 533numIQEntries=64 534numPhysFloatRegs=256 535numPhysIntRegs=256 536numROBEntries=192 537numRobs=1 538numThreads=1 539phase=0 540predType=tournament 541progress_interval=0 542renameToDecodeDelay=1 543renameToFetchDelay=1 544renameToIEWDelay=2 545renameToROBDelay=1 546renameWidth=8 547smtCommitPolicy=RoundRobin 548smtFetchPolicy=SingleThread 549smtIQPolicy=Partitioned 550smtIQThreshold=100 551smtLSQPolicy=Partitioned 552smtLSQThreshold=100 553smtNumFetchingThreads=1 554smtROBPolicy=Partitioned 555smtROBThreshold=100 556squashWidth=8 557store_set_clear_period=250000 558system=system 559tracer=system.cpu1.tracer 560trapLatency=13 561wbDepth=1 562wbWidth=8 563workload=system.cpu0.workload 564dcache_port=system.cpu1.dcache.cpu_side 565icache_port=system.cpu1.icache.cpu_side 566 567[system.cpu1.dcache] 568type=BaseCache 569addr_range=0:18446744073709551615 570assoc=4 571block_size=64 572forward_snoops=true 573hash_delay=1 574is_top_level=true 575latency=1000 576max_miss_count=0 577mshrs=4 578num_cpus=1 579prefetch_data_accesses_only=false 580prefetch_degree=1 581prefetch_latency=10000 582prefetch_on_access=false 583prefetch_past_page=false 584prefetch_policy=none 585prefetch_serial_squash=false 586prefetch_use_cpu_id=true 587prefetcher_size=100 588prioritizeRequests=false 589repl=Null 590size=32768 591subblock_size=0 592tgts_per_mshr=20 593trace_addr=0 594two_queue=false 595write_buffers=8 596cpu_side=system.cpu1.dcache_port 597mem_side=system.toL2Bus.port[4] 598 599[system.cpu1.dtb] 600type=SparcTLB 601size=64 602 603[system.cpu1.fuPool] 604type=FUPool 605children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 606FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 607 608[system.cpu1.fuPool.FUList0] 609type=FUDesc 610children=opList 611count=6 612opList=system.cpu1.fuPool.FUList0.opList 613 614[system.cpu1.fuPool.FUList0.opList] 615type=OpDesc 616issueLat=1 617opClass=IntAlu 618opLat=1 619 620[system.cpu1.fuPool.FUList1] 621type=FUDesc 622children=opList0 opList1 623count=2 624opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 625 626[system.cpu1.fuPool.FUList1.opList0] 627type=OpDesc 628issueLat=1 629opClass=IntMult 630opLat=3 631 632[system.cpu1.fuPool.FUList1.opList1] 633type=OpDesc 634issueLat=19 635opClass=IntDiv 636opLat=20 637 638[system.cpu1.fuPool.FUList2] 639type=FUDesc 640children=opList0 opList1 opList2 641count=4 642opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 643 644[system.cpu1.fuPool.FUList2.opList0] 645type=OpDesc 646issueLat=1 647opClass=FloatAdd 648opLat=2 649 650[system.cpu1.fuPool.FUList2.opList1] 651type=OpDesc 652issueLat=1 653opClass=FloatCmp 654opLat=2 655 656[system.cpu1.fuPool.FUList2.opList2] 657type=OpDesc 658issueLat=1 659opClass=FloatCvt 660opLat=2 661 662[system.cpu1.fuPool.FUList3] 663type=FUDesc 664children=opList0 opList1 opList2 665count=2 666opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 667 668[system.cpu1.fuPool.FUList3.opList0] 669type=OpDesc 670issueLat=1 671opClass=FloatMult 672opLat=4 673 674[system.cpu1.fuPool.FUList3.opList1] 675type=OpDesc 676issueLat=12 677opClass=FloatDiv 678opLat=12 679 680[system.cpu1.fuPool.FUList3.opList2] 681type=OpDesc 682issueLat=24 683opClass=FloatSqrt 684opLat=24 685 686[system.cpu1.fuPool.FUList4] 687type=FUDesc 688children=opList 689count=0 690opList=system.cpu1.fuPool.FUList4.opList 691 692[system.cpu1.fuPool.FUList4.opList] 693type=OpDesc 694issueLat=1 695opClass=MemRead 696opLat=1 697 698[system.cpu1.fuPool.FUList5] 699type=FUDesc 700children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 701count=4 702opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 703 704[system.cpu1.fuPool.FUList5.opList00] 705type=OpDesc 706issueLat=1 707opClass=SimdAdd 708opLat=1 709 710[system.cpu1.fuPool.FUList5.opList01] 711type=OpDesc 712issueLat=1 713opClass=SimdAddAcc 714opLat=1 715 716[system.cpu1.fuPool.FUList5.opList02] 717type=OpDesc 718issueLat=1 719opClass=SimdAlu 720opLat=1 721 722[system.cpu1.fuPool.FUList5.opList03] 723type=OpDesc 724issueLat=1 725opClass=SimdCmp 726opLat=1 727 728[system.cpu1.fuPool.FUList5.opList04] 729type=OpDesc 730issueLat=1 731opClass=SimdCvt 732opLat=1 733 734[system.cpu1.fuPool.FUList5.opList05] 735type=OpDesc 736issueLat=1 737opClass=SimdMisc 738opLat=1 739 740[system.cpu1.fuPool.FUList5.opList06] 741type=OpDesc 742issueLat=1 743opClass=SimdMult 744opLat=1 745 746[system.cpu1.fuPool.FUList5.opList07] 747type=OpDesc 748issueLat=1 749opClass=SimdMultAcc 750opLat=1 751 752[system.cpu1.fuPool.FUList5.opList08] 753type=OpDesc 754issueLat=1 755opClass=SimdShift 756opLat=1 757 758[system.cpu1.fuPool.FUList5.opList09] 759type=OpDesc 760issueLat=1 761opClass=SimdShiftAcc 762opLat=1 763 764[system.cpu1.fuPool.FUList5.opList10] 765type=OpDesc 766issueLat=1 767opClass=SimdSqrt 768opLat=1 769 770[system.cpu1.fuPool.FUList5.opList11] 771type=OpDesc 772issueLat=1 773opClass=SimdFloatAdd 774opLat=1 775 776[system.cpu1.fuPool.FUList5.opList12] 777type=OpDesc 778issueLat=1 779opClass=SimdFloatAlu 780opLat=1 781 782[system.cpu1.fuPool.FUList5.opList13] 783type=OpDesc 784issueLat=1 785opClass=SimdFloatCmp 786opLat=1 787 788[system.cpu1.fuPool.FUList5.opList14] 789type=OpDesc 790issueLat=1 791opClass=SimdFloatCvt 792opLat=1 793 794[system.cpu1.fuPool.FUList5.opList15] 795type=OpDesc 796issueLat=1 797opClass=SimdFloatDiv 798opLat=1 799 800[system.cpu1.fuPool.FUList5.opList16] 801type=OpDesc 802issueLat=1 803opClass=SimdFloatMisc 804opLat=1 805 806[system.cpu1.fuPool.FUList5.opList17] 807type=OpDesc 808issueLat=1 809opClass=SimdFloatMult 810opLat=1 811 812[system.cpu1.fuPool.FUList5.opList18] 813type=OpDesc 814issueLat=1 815opClass=SimdFloatMultAcc 816opLat=1 817 818[system.cpu1.fuPool.FUList5.opList19] 819type=OpDesc 820issueLat=1 821opClass=SimdFloatSqrt 822opLat=1 823 824[system.cpu1.fuPool.FUList6] 825type=FUDesc 826children=opList 827count=0 828opList=system.cpu1.fuPool.FUList6.opList 829 830[system.cpu1.fuPool.FUList6.opList] 831type=OpDesc 832issueLat=1 833opClass=MemWrite 834opLat=1 835 836[system.cpu1.fuPool.FUList7] 837type=FUDesc 838children=opList0 opList1 839count=4 840opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 841 842[system.cpu1.fuPool.FUList7.opList0] 843type=OpDesc 844issueLat=1 845opClass=MemRead 846opLat=1 847 848[system.cpu1.fuPool.FUList7.opList1] 849type=OpDesc 850issueLat=1 851opClass=MemWrite 852opLat=1 853 854[system.cpu1.fuPool.FUList8] 855type=FUDesc 856children=opList 857count=1 858opList=system.cpu1.fuPool.FUList8.opList 859 860[system.cpu1.fuPool.FUList8.opList] 861type=OpDesc 862issueLat=3 863opClass=IprAccess 864opLat=3 865 866[system.cpu1.icache] 867type=BaseCache 868addr_range=0:18446744073709551615 869assoc=1 870block_size=64 871forward_snoops=true 872hash_delay=1 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1544issueLat=24 1545opClass=FloatSqrt 1546opLat=24 1547 1548[system.cpu3.fuPool.FUList4] 1549type=FUDesc 1550children=opList 1551count=0 1552opList=system.cpu3.fuPool.FUList4.opList 1553 1554[system.cpu3.fuPool.FUList4.opList] 1555type=OpDesc 1556issueLat=1 1557opClass=MemRead 1558opLat=1 1559 1560[system.cpu3.fuPool.FUList5] 1561type=FUDesc 1562children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1563count=4 1564opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1565 1566[system.cpu3.fuPool.FUList5.opList00] 1567type=OpDesc 1568issueLat=1 1569opClass=SimdAdd 1570opLat=1 1571 1572[system.cpu3.fuPool.FUList5.opList01] 1573type=OpDesc 1574issueLat=1 1575opClass=SimdAddAcc 1576opLat=1 1577 1578[system.cpu3.fuPool.FUList5.opList02] 1579type=OpDesc 1580issueLat=1 1581opClass=SimdAlu 1582opLat=1 1583 1584[system.cpu3.fuPool.FUList5.opList03] 1585type=OpDesc 1586issueLat=1 1587opClass=SimdCmp 1588opLat=1 1589 1590[system.cpu3.fuPool.FUList5.opList04] 1591type=OpDesc 1592issueLat=1 1593opClass=SimdCvt 1594opLat=1 1595 1596[system.cpu3.fuPool.FUList5.opList05] 1597type=OpDesc 1598issueLat=1 1599opClass=SimdMisc 1600opLat=1 1601 1602[system.cpu3.fuPool.FUList5.opList06] 1603type=OpDesc 1604issueLat=1 1605opClass=SimdMult 1606opLat=1 1607 1608[system.cpu3.fuPool.FUList5.opList07] 1609type=OpDesc 1610issueLat=1 1611opClass=SimdMultAcc 1612opLat=1 1613 1614[system.cpu3.fuPool.FUList5.opList08] 1615type=OpDesc 1616issueLat=1 1617opClass=SimdShift 1618opLat=1 1619 1620[system.cpu3.fuPool.FUList5.opList09] 1621type=OpDesc 1622issueLat=1 1623opClass=SimdShiftAcc 1624opLat=1 1625 1626[system.cpu3.fuPool.FUList5.opList10] 1627type=OpDesc 1628issueLat=1 1629opClass=SimdSqrt 1630opLat=1 1631 1632[system.cpu3.fuPool.FUList5.opList11] 1633type=OpDesc 1634issueLat=1 1635opClass=SimdFloatAdd 1636opLat=1 1637 1638[system.cpu3.fuPool.FUList5.opList12] 1639type=OpDesc 1640issueLat=1 1641opClass=SimdFloatAlu 1642opLat=1 1643 1644[system.cpu3.fuPool.FUList5.opList13] 1645type=OpDesc 1646issueLat=1 1647opClass=SimdFloatCmp 1648opLat=1 1649 1650[system.cpu3.fuPool.FUList5.opList14] 1651type=OpDesc 1652issueLat=1 1653opClass=SimdFloatCvt 1654opLat=1 1655 1656[system.cpu3.fuPool.FUList5.opList15] 1657type=OpDesc 1658issueLat=1 1659opClass=SimdFloatDiv 1660opLat=1 1661 1662[system.cpu3.fuPool.FUList5.opList16] 1663type=OpDesc 1664issueLat=1 1665opClass=SimdFloatMisc 1666opLat=1 1667 1668[system.cpu3.fuPool.FUList5.opList17] 1669type=OpDesc 1670issueLat=1 1671opClass=SimdFloatMult 1672opLat=1 1673 1674[system.cpu3.fuPool.FUList5.opList18] 1675type=OpDesc 1676issueLat=1 1677opClass=SimdFloatMultAcc 1678opLat=1 1679 1680[system.cpu3.fuPool.FUList5.opList19] 1681type=OpDesc 1682issueLat=1 1683opClass=SimdFloatSqrt 1684opLat=1 1685 1686[system.cpu3.fuPool.FUList6] 1687type=FUDesc 1688children=opList 1689count=0 1690opList=system.cpu3.fuPool.FUList6.opList 1691 1692[system.cpu3.fuPool.FUList6.opList] 1693type=OpDesc 1694issueLat=1 1695opClass=MemWrite 1696opLat=1 1697 1698[system.cpu3.fuPool.FUList7] 1699type=FUDesc 1700children=opList0 opList1 1701count=4 1702opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 1703 1704[system.cpu3.fuPool.FUList7.opList0] 1705type=OpDesc 1706issueLat=1 1707opClass=MemRead 1708opLat=1 1709 1710[system.cpu3.fuPool.FUList7.opList1] 1711type=OpDesc 1712issueLat=1 1713opClass=MemWrite 1714opLat=1 1715 1716[system.cpu3.fuPool.FUList8] 1717type=FUDesc 1718children=opList 1719count=1 1720opList=system.cpu3.fuPool.FUList8.opList 1721 1722[system.cpu3.fuPool.FUList8.opList] 1723type=OpDesc 1724issueLat=3 1725opClass=IprAccess 1726opLat=3 1727 1728[system.cpu3.icache] 1729type=BaseCache 1730addr_range=0:18446744073709551615 1731assoc=1 1732block_size=64 1733forward_snoops=true 1734hash_delay=1 1735is_top_level=true 1736latency=1000 1737max_miss_count=0 1738mshrs=4 1739num_cpus=1 1740prefetch_data_accesses_only=false 1741prefetch_degree=1 1742prefetch_latency=10000 1743prefetch_on_access=false 1744prefetch_past_page=false 1745prefetch_policy=none 1746prefetch_serial_squash=false 1747prefetch_use_cpu_id=true 1748prefetcher_size=100 1749prioritizeRequests=false 1750repl=Null 1751size=32768 1752subblock_size=0 1753tgts_per_mshr=20 1754trace_addr=0 1755two_queue=false 1756write_buffers=8 1757cpu_side=system.cpu3.icache_port 1758mem_side=system.toL2Bus.port[7] 1759 1760[system.cpu3.itb] 1761type=SparcTLB 1762size=64 1763 1764[system.cpu3.tracer] 1765type=ExeTracer 1766 1767[system.l2c] 1768type=BaseCache 1769addr_range=0:18446744073709551615 1770assoc=8 1771block_size=64 1772forward_snoops=true 1773hash_delay=1 1774is_top_level=false 1775latency=10000 1776max_miss_count=0 1777mshrs=92 1778num_cpus=4 1779prefetch_data_accesses_only=false 1780prefetch_degree=1 1781prefetch_latency=100000 1782prefetch_on_access=false 1783prefetch_past_page=false 1784prefetch_policy=none 1785prefetch_serial_squash=false 1786prefetch_use_cpu_id=true 1787prefetcher_size=100 1788prioritizeRequests=false 1789repl=Null 1790size=4194304 1791subblock_size=0 1792tgts_per_mshr=16 1793trace_addr=0 1794two_queue=false 1795write_buffers=8 1796cpu_side=system.toL2Bus.port[0] 1797mem_side=system.membus.port[0] 1798 1799[system.membus] 1800type=Bus 1801block_size=64 1802bus_id=0 1803clock=1000 1804header_cycles=1 1805use_default_range=false 1806width=64 1807port=system.l2c.mem_side system.physmem.port[0] system.system_port 1808 1809[system.physmem] 1810type=PhysicalMemory 1811file= 1812latency=30000 1813latency_var=0 1814null=false 1815range=0:134217727 1816zero=false 1817port=system.membus.port[1] 1818 1819[system.toL2Bus] 1820type=Bus 1821block_size=64 1822bus_id=0 1823clock=1000 1824header_cycles=1 1825use_default_range=false 1826width=64 1827port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 1828 1829