config.ini revision 11384
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu0] 50type=DerivO3CPU 51children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 52LFSTSize=1024 53LQEntries=32 54LSQCheckLoads=true 55LSQDepCheckShift=4 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60branchPred=system.cpu0.branchPred 61cachePorts=200 62checker=Null 63clk_domain=system.cpu_clk_domain 64commitToDecodeDelay=1 65commitToFetchDelay=1 66commitToIEWDelay=1 67commitToRenameDelay=1 68commitWidth=8 69cpu_id=0 70decodeToFetchDelay=1 71decodeToRenameDelay=1 72decodeWidth=8 73dispatchWidth=8 74do_checkpoint_insts=true 75do_quiesce=true 76do_statistics_insts=true 77dtb=system.cpu0.dtb 78eventq_index=0 79fetchBufferSize=64 80fetchQueueSize=32 81fetchToDecodeDelay=1 82fetchTrapLatency=1 83fetchWidth=8 84forwardComSize=5 85fuPool=system.cpu0.fuPool 86function_trace=false 87function_trace_start=0 88iewToCommitDelay=1 89iewToDecodeDelay=1 90iewToFetchDelay=1 91iewToRenameDelay=1 92interrupts=system.cpu0.interrupts 93isa=system.cpu0.isa 94issueToExecuteDelay=1 95issueWidth=8 96itb=system.cpu0.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=false 102numIQEntries=64 103numPhysCCRegs=0 104numPhysFloatRegs=256 105numPhysIntRegs=256 106numROBEntries=192 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=2 114renameToROBDelay=1 115renameWidth=8 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu0.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu0.workload 135dcache_port=system.cpu0.dcache.cpu_side 136icache_port=system.cpu0.icache.cpu_side 137 138[system.cpu0.branchPred] 139type=TournamentBP 140BTBEntries=4096 141BTBTagSize=16 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149localCtrBits=2 150localHistoryTableSize=2048 151localPredictorSize=2048 152numThreads=1 153 154[system.cpu0.dcache] 155type=Cache 156children=tags 157addr_ranges=0:18446744073709551615 158assoc=4 159clk_domain=system.cpu_clk_domain 160clusivity=mostly_incl 161demand_mshr_reserve=1 162eventq_index=0 163hit_latency=2 164is_read_only=false 165max_miss_count=0 166mshrs=4 167prefetch_on_access=false 168prefetcher=Null 169response_latency=2 170sequential_access=false 171size=32768 172system=system 173tags=system.cpu0.dcache.tags 174tgts_per_mshr=20 175write_buffers=8 176writeback_clean=false 177cpu_side=system.cpu0.dcache_port 178mem_side=system.toL2Bus.slave[1] 179 180[system.cpu0.dcache.tags] 181type=LRU 182assoc=4 183block_size=64 184clk_domain=system.cpu_clk_domain 185eventq_index=0 186hit_latency=2 187sequential_access=false 188size=32768 189 190[system.cpu0.dtb] 191type=SparcTLB 192eventq_index=0 193size=64 194 195[system.cpu0.fuPool] 196type=FUPool 197children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 198FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 199eventq_index=0 200 201[system.cpu0.fuPool.FUList0] 202type=FUDesc 203children=opList 204count=6 205eventq_index=0 206opList=system.cpu0.fuPool.FUList0.opList 207 208[system.cpu0.fuPool.FUList0.opList] 209type=OpDesc 210eventq_index=0 211opClass=IntAlu 212opLat=1 213pipelined=true 214 215[system.cpu0.fuPool.FUList1] 216type=FUDesc 217children=opList0 opList1 218count=2 219eventq_index=0 220opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 221 222[system.cpu0.fuPool.FUList1.opList0] 223type=OpDesc 224eventq_index=0 225opClass=IntMult 226opLat=3 227pipelined=true 228 229[system.cpu0.fuPool.FUList1.opList1] 230type=OpDesc 231eventq_index=0 232opClass=IntDiv 233opLat=20 234pipelined=false 235 236[system.cpu0.fuPool.FUList2] 237type=FUDesc 238children=opList0 opList1 opList2 239count=4 240eventq_index=0 241opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 242 243[system.cpu0.fuPool.FUList2.opList0] 244type=OpDesc 245eventq_index=0 246opClass=FloatAdd 247opLat=2 248pipelined=true 249 250[system.cpu0.fuPool.FUList2.opList1] 251type=OpDesc 252eventq_index=0 253opClass=FloatCmp 254opLat=2 255pipelined=true 256 257[system.cpu0.fuPool.FUList2.opList2] 258type=OpDesc 259eventq_index=0 260opClass=FloatCvt 261opLat=2 262pipelined=true 263 264[system.cpu0.fuPool.FUList3] 265type=FUDesc 266children=opList0 opList1 opList2 267count=2 268eventq_index=0 269opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 270 271[system.cpu0.fuPool.FUList3.opList0] 272type=OpDesc 273eventq_index=0 274opClass=FloatMult 275opLat=4 276pipelined=true 277 278[system.cpu0.fuPool.FUList3.opList1] 279type=OpDesc 280eventq_index=0 281opClass=FloatDiv 282opLat=12 283pipelined=false 284 285[system.cpu0.fuPool.FUList3.opList2] 286type=OpDesc 287eventq_index=0 288opClass=FloatSqrt 289opLat=24 290pipelined=false 291 292[system.cpu0.fuPool.FUList4] 293type=FUDesc 294children=opList 295count=0 296eventq_index=0 297opList=system.cpu0.fuPool.FUList4.opList 298 299[system.cpu0.fuPool.FUList4.opList] 300type=OpDesc 301eventq_index=0 302opClass=MemRead 303opLat=1 304pipelined=true 305 306[system.cpu0.fuPool.FUList5] 307type=FUDesc 308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 309count=4 310eventq_index=0 311opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 312 313[system.cpu0.fuPool.FUList5.opList00] 314type=OpDesc 315eventq_index=0 316opClass=SimdAdd 317opLat=1 318pipelined=true 319 320[system.cpu0.fuPool.FUList5.opList01] 321type=OpDesc 322eventq_index=0 323opClass=SimdAddAcc 324opLat=1 325pipelined=true 326 327[system.cpu0.fuPool.FUList5.opList02] 328type=OpDesc 329eventq_index=0 330opClass=SimdAlu 331opLat=1 332pipelined=true 333 334[system.cpu0.fuPool.FUList5.opList03] 335type=OpDesc 336eventq_index=0 337opClass=SimdCmp 338opLat=1 339pipelined=true 340 341[system.cpu0.fuPool.FUList5.opList04] 342type=OpDesc 343eventq_index=0 344opClass=SimdCvt 345opLat=1 346pipelined=true 347 348[system.cpu0.fuPool.FUList5.opList05] 349type=OpDesc 350eventq_index=0 351opClass=SimdMisc 352opLat=1 353pipelined=true 354 355[system.cpu0.fuPool.FUList5.opList06] 356type=OpDesc 357eventq_index=0 358opClass=SimdMult 359opLat=1 360pipelined=true 361 362[system.cpu0.fuPool.FUList5.opList07] 363type=OpDesc 364eventq_index=0 365opClass=SimdMultAcc 366opLat=1 367pipelined=true 368 369[system.cpu0.fuPool.FUList5.opList08] 370type=OpDesc 371eventq_index=0 372opClass=SimdShift 373opLat=1 374pipelined=true 375 376[system.cpu0.fuPool.FUList5.opList09] 377type=OpDesc 378eventq_index=0 379opClass=SimdShiftAcc 380opLat=1 381pipelined=true 382 383[system.cpu0.fuPool.FUList5.opList10] 384type=OpDesc 385eventq_index=0 386opClass=SimdSqrt 387opLat=1 388pipelined=true 389 390[system.cpu0.fuPool.FUList5.opList11] 391type=OpDesc 392eventq_index=0 393opClass=SimdFloatAdd 394opLat=1 395pipelined=true 396 397[system.cpu0.fuPool.FUList5.opList12] 398type=OpDesc 399eventq_index=0 400opClass=SimdFloatAlu 401opLat=1 402pipelined=true 403 404[system.cpu0.fuPool.FUList5.opList13] 405type=OpDesc 406eventq_index=0 407opClass=SimdFloatCmp 408opLat=1 409pipelined=true 410 411[system.cpu0.fuPool.FUList5.opList14] 412type=OpDesc 413eventq_index=0 414opClass=SimdFloatCvt 415opLat=1 416pipelined=true 417 418[system.cpu0.fuPool.FUList5.opList15] 419type=OpDesc 420eventq_index=0 421opClass=SimdFloatDiv 422opLat=1 423pipelined=true 424 425[system.cpu0.fuPool.FUList5.opList16] 426type=OpDesc 427eventq_index=0 428opClass=SimdFloatMisc 429opLat=1 430pipelined=true 431 432[system.cpu0.fuPool.FUList5.opList17] 433type=OpDesc 434eventq_index=0 435opClass=SimdFloatMult 436opLat=1 437pipelined=true 438 439[system.cpu0.fuPool.FUList5.opList18] 440type=OpDesc 441eventq_index=0 442opClass=SimdFloatMultAcc 443opLat=1 444pipelined=true 445 446[system.cpu0.fuPool.FUList5.opList19] 447type=OpDesc 448eventq_index=0 449opClass=SimdFloatSqrt 450opLat=1 451pipelined=true 452 453[system.cpu0.fuPool.FUList6] 454type=FUDesc 455children=opList 456count=0 457eventq_index=0 458opList=system.cpu0.fuPool.FUList6.opList 459 460[system.cpu0.fuPool.FUList6.opList] 461type=OpDesc 462eventq_index=0 463opClass=MemWrite 464opLat=1 465pipelined=true 466 467[system.cpu0.fuPool.FUList7] 468type=FUDesc 469children=opList0 opList1 470count=4 471eventq_index=0 472opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 473 474[system.cpu0.fuPool.FUList7.opList0] 475type=OpDesc 476eventq_index=0 477opClass=MemRead 478opLat=1 479pipelined=true 480 481[system.cpu0.fuPool.FUList7.opList1] 482type=OpDesc 483eventq_index=0 484opClass=MemWrite 485opLat=1 486pipelined=true 487 488[system.cpu0.fuPool.FUList8] 489type=FUDesc 490children=opList 491count=1 492eventq_index=0 493opList=system.cpu0.fuPool.FUList8.opList 494 495[system.cpu0.fuPool.FUList8.opList] 496type=OpDesc 497eventq_index=0 498opClass=IprAccess 499opLat=3 500pipelined=false 501 502[system.cpu0.icache] 503type=Cache 504children=tags 505addr_ranges=0:18446744073709551615 506assoc=1 507clk_domain=system.cpu_clk_domain 508clusivity=mostly_incl 509demand_mshr_reserve=1 510eventq_index=0 511hit_latency=2 512is_read_only=true 513max_miss_count=0 514mshrs=4 515prefetch_on_access=false 516prefetcher=Null 517response_latency=2 518sequential_access=false 519size=32768 520system=system 521tags=system.cpu0.icache.tags 522tgts_per_mshr=20 523write_buffers=8 524writeback_clean=true 525cpu_side=system.cpu0.icache_port 526mem_side=system.toL2Bus.slave[0] 527 528[system.cpu0.icache.tags] 529type=LRU 530assoc=1 531block_size=64 532clk_domain=system.cpu_clk_domain 533eventq_index=0 534hit_latency=2 535sequential_access=false 536size=32768 537 538[system.cpu0.interrupts] 539type=SparcInterrupts 540eventq_index=0 541 542[system.cpu0.isa] 543type=SparcISA 544eventq_index=0 545 546[system.cpu0.itb] 547type=SparcTLB 548eventq_index=0 549size=64 550 551[system.cpu0.tracer] 552type=ExeTracer 553eventq_index=0 554 555[system.cpu0.workload] 556type=LiveProcess 557cmd=test_atomic 4 558cwd= 559drivers= 560egid=100 561env= 562errout=cerr 563euid=100 564eventq_index=0 565executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic 566gid=100 567input=cin 568kvmInSE=false 569max_stack_size=67108864 570output=cout 571pid=100 572ppid=99 573simpoint=0 574system=system 575uid=100 576useArchPT=false 577 578[system.cpu1] 579type=DerivO3CPU 580children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 581LFSTSize=1024 582LQEntries=32 583LSQCheckLoads=true 584LSQDepCheckShift=4 585SQEntries=32 586SSITSize=1024 587activity=0 588backComSize=5 589branchPred=system.cpu1.branchPred 590cachePorts=200 591checker=Null 592clk_domain=system.cpu_clk_domain 593commitToDecodeDelay=1 594commitToFetchDelay=1 595commitToIEWDelay=1 596commitToRenameDelay=1 597commitWidth=8 598cpu_id=1 599decodeToFetchDelay=1 600decodeToRenameDelay=1 601decodeWidth=8 602dispatchWidth=8 603do_checkpoint_insts=true 604do_quiesce=true 605do_statistics_insts=true 606dtb=system.cpu1.dtb 607eventq_index=0 608fetchBufferSize=64 609fetchQueueSize=32 610fetchToDecodeDelay=1 611fetchTrapLatency=1 612fetchWidth=8 613forwardComSize=5 614fuPool=system.cpu1.fuPool 615function_trace=false 616function_trace_start=0 617iewToCommitDelay=1 618iewToDecodeDelay=1 619iewToFetchDelay=1 620iewToRenameDelay=1 621interrupts=system.cpu1.interrupts 622isa=system.cpu1.isa 623issueToExecuteDelay=1 624issueWidth=8 625itb=system.cpu1.itb 626max_insts_all_threads=0 627max_insts_any_thread=0 628max_loads_all_threads=0 629max_loads_any_thread=0 630needsTSO=false 631numIQEntries=64 632numPhysCCRegs=0 633numPhysFloatRegs=256 634numPhysIntRegs=256 635numROBEntries=192 636numRobs=1 637numThreads=1 638profile=0 639progress_interval=0 640renameToDecodeDelay=1 641renameToFetchDelay=1 642renameToIEWDelay=2 643renameToROBDelay=1 644renameWidth=8 645simpoint_start_insts= 646smtCommitPolicy=RoundRobin 647smtFetchPolicy=SingleThread 648smtIQPolicy=Partitioned 649smtIQThreshold=100 650smtLSQPolicy=Partitioned 651smtLSQThreshold=100 652smtNumFetchingThreads=1 653smtROBPolicy=Partitioned 654smtROBThreshold=100 655socket_id=0 656squashWidth=8 657store_set_clear_period=250000 658switched_out=false 659system=system 660tracer=system.cpu1.tracer 661trapLatency=13 662wbWidth=8 663workload=system.cpu0.workload 664dcache_port=system.cpu1.dcache.cpu_side 665icache_port=system.cpu1.icache.cpu_side 666 667[system.cpu1.branchPred] 668type=TournamentBP 669BTBEntries=4096 670BTBTagSize=16 671RASSize=16 672choiceCtrBits=2 673choicePredictorSize=8192 674eventq_index=0 675globalCtrBits=2 676globalPredictorSize=8192 677instShiftAmt=2 678localCtrBits=2 679localHistoryTableSize=2048 680localPredictorSize=2048 681numThreads=1 682 683[system.cpu1.dcache] 684type=Cache 685children=tags 686addr_ranges=0:18446744073709551615 687assoc=4 688clk_domain=system.cpu_clk_domain 689clusivity=mostly_incl 690demand_mshr_reserve=1 691eventq_index=0 692hit_latency=2 693is_read_only=false 694max_miss_count=0 695mshrs=4 696prefetch_on_access=false 697prefetcher=Null 698response_latency=2 699sequential_access=false 700size=32768 701system=system 702tags=system.cpu1.dcache.tags 703tgts_per_mshr=20 704write_buffers=8 705writeback_clean=false 706cpu_side=system.cpu1.dcache_port 707mem_side=system.toL2Bus.slave[3] 708 709[system.cpu1.dcache.tags] 710type=LRU 711assoc=4 712block_size=64 713clk_domain=system.cpu_clk_domain 714eventq_index=0 715hit_latency=2 716sequential_access=false 717size=32768 718 719[system.cpu1.dtb] 720type=SparcTLB 721eventq_index=0 722size=64 723 724[system.cpu1.fuPool] 725type=FUPool 726children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 727FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 728eventq_index=0 729 730[system.cpu1.fuPool.FUList0] 731type=FUDesc 732children=opList 733count=6 734eventq_index=0 735opList=system.cpu1.fuPool.FUList0.opList 736 737[system.cpu1.fuPool.FUList0.opList] 738type=OpDesc 739eventq_index=0 740opClass=IntAlu 741opLat=1 742pipelined=true 743 744[system.cpu1.fuPool.FUList1] 745type=FUDesc 746children=opList0 opList1 747count=2 748eventq_index=0 749opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 750 751[system.cpu1.fuPool.FUList1.opList0] 752type=OpDesc 753eventq_index=0 754opClass=IntMult 755opLat=3 756pipelined=true 757 758[system.cpu1.fuPool.FUList1.opList1] 759type=OpDesc 760eventq_index=0 761opClass=IntDiv 762opLat=20 763pipelined=false 764 765[system.cpu1.fuPool.FUList2] 766type=FUDesc 767children=opList0 opList1 opList2 768count=4 769eventq_index=0 770opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 771 772[system.cpu1.fuPool.FUList2.opList0] 773type=OpDesc 774eventq_index=0 775opClass=FloatAdd 776opLat=2 777pipelined=true 778 779[system.cpu1.fuPool.FUList2.opList1] 780type=OpDesc 781eventq_index=0 782opClass=FloatCmp 783opLat=2 784pipelined=true 785 786[system.cpu1.fuPool.FUList2.opList2] 787type=OpDesc 788eventq_index=0 789opClass=FloatCvt 790opLat=2 791pipelined=true 792 793[system.cpu1.fuPool.FUList3] 794type=FUDesc 795children=opList0 opList1 opList2 796count=2 797eventq_index=0 798opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 799 800[system.cpu1.fuPool.FUList3.opList0] 801type=OpDesc 802eventq_index=0 803opClass=FloatMult 804opLat=4 805pipelined=true 806 807[system.cpu1.fuPool.FUList3.opList1] 808type=OpDesc 809eventq_index=0 810opClass=FloatDiv 811opLat=12 812pipelined=false 813 814[system.cpu1.fuPool.FUList3.opList2] 815type=OpDesc 816eventq_index=0 817opClass=FloatSqrt 818opLat=24 819pipelined=false 820 821[system.cpu1.fuPool.FUList4] 822type=FUDesc 823children=opList 824count=0 825eventq_index=0 826opList=system.cpu1.fuPool.FUList4.opList 827 828[system.cpu1.fuPool.FUList4.opList] 829type=OpDesc 830eventq_index=0 831opClass=MemRead 832opLat=1 833pipelined=true 834 835[system.cpu1.fuPool.FUList5] 836type=FUDesc 837children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 838count=4 839eventq_index=0 840opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 841 842[system.cpu1.fuPool.FUList5.opList00] 843type=OpDesc 844eventq_index=0 845opClass=SimdAdd 846opLat=1 847pipelined=true 848 849[system.cpu1.fuPool.FUList5.opList01] 850type=OpDesc 851eventq_index=0 852opClass=SimdAddAcc 853opLat=1 854pipelined=true 855 856[system.cpu1.fuPool.FUList5.opList02] 857type=OpDesc 858eventq_index=0 859opClass=SimdAlu 860opLat=1 861pipelined=true 862 863[system.cpu1.fuPool.FUList5.opList03] 864type=OpDesc 865eventq_index=0 866opClass=SimdCmp 867opLat=1 868pipelined=true 869 870[system.cpu1.fuPool.FUList5.opList04] 871type=OpDesc 872eventq_index=0 873opClass=SimdCvt 874opLat=1 875pipelined=true 876 877[system.cpu1.fuPool.FUList5.opList05] 878type=OpDesc 879eventq_index=0 880opClass=SimdMisc 881opLat=1 882pipelined=true 883 884[system.cpu1.fuPool.FUList5.opList06] 885type=OpDesc 886eventq_index=0 887opClass=SimdMult 888opLat=1 889pipelined=true 890 891[system.cpu1.fuPool.FUList5.opList07] 892type=OpDesc 893eventq_index=0 894opClass=SimdMultAcc 895opLat=1 896pipelined=true 897 898[system.cpu1.fuPool.FUList5.opList08] 899type=OpDesc 900eventq_index=0 901opClass=SimdShift 902opLat=1 903pipelined=true 904 905[system.cpu1.fuPool.FUList5.opList09] 906type=OpDesc 907eventq_index=0 908opClass=SimdShiftAcc 909opLat=1 910pipelined=true 911 912[system.cpu1.fuPool.FUList5.opList10] 913type=OpDesc 914eventq_index=0 915opClass=SimdSqrt 916opLat=1 917pipelined=true 918 919[system.cpu1.fuPool.FUList5.opList11] 920type=OpDesc 921eventq_index=0 922opClass=SimdFloatAdd 923opLat=1 924pipelined=true 925 926[system.cpu1.fuPool.FUList5.opList12] 927type=OpDesc 928eventq_index=0 929opClass=SimdFloatAlu 930opLat=1 931pipelined=true 932 933[system.cpu1.fuPool.FUList5.opList13] 934type=OpDesc 935eventq_index=0 936opClass=SimdFloatCmp 937opLat=1 938pipelined=true 939 940[system.cpu1.fuPool.FUList5.opList14] 941type=OpDesc 942eventq_index=0 943opClass=SimdFloatCvt 944opLat=1 945pipelined=true 946 947[system.cpu1.fuPool.FUList5.opList15] 948type=OpDesc 949eventq_index=0 950opClass=SimdFloatDiv 951opLat=1 952pipelined=true 953 954[system.cpu1.fuPool.FUList5.opList16] 955type=OpDesc 956eventq_index=0 957opClass=SimdFloatMisc 958opLat=1 959pipelined=true 960 961[system.cpu1.fuPool.FUList5.opList17] 962type=OpDesc 963eventq_index=0 964opClass=SimdFloatMult 965opLat=1 966pipelined=true 967 968[system.cpu1.fuPool.FUList5.opList18] 969type=OpDesc 970eventq_index=0 971opClass=SimdFloatMultAcc 972opLat=1 973pipelined=true 974 975[system.cpu1.fuPool.FUList5.opList19] 976type=OpDesc 977eventq_index=0 978opClass=SimdFloatSqrt 979opLat=1 980pipelined=true 981 982[system.cpu1.fuPool.FUList6] 983type=FUDesc 984children=opList 985count=0 986eventq_index=0 987opList=system.cpu1.fuPool.FUList6.opList 988 989[system.cpu1.fuPool.FUList6.opList] 990type=OpDesc 991eventq_index=0 992opClass=MemWrite 993opLat=1 994pipelined=true 995 996[system.cpu1.fuPool.FUList7] 997type=FUDesc 998children=opList0 opList1 999count=4 1000eventq_index=0 1001opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 1002 1003[system.cpu1.fuPool.FUList7.opList0] 1004type=OpDesc 1005eventq_index=0 1006opClass=MemRead 1007opLat=1 1008pipelined=true 1009 1010[system.cpu1.fuPool.FUList7.opList1] 1011type=OpDesc 1012eventq_index=0 1013opClass=MemWrite 1014opLat=1 1015pipelined=true 1016 1017[system.cpu1.fuPool.FUList8] 1018type=FUDesc 1019children=opList 1020count=1 1021eventq_index=0 1022opList=system.cpu1.fuPool.FUList8.opList 1023 1024[system.cpu1.fuPool.FUList8.opList] 1025type=OpDesc 1026eventq_index=0 1027opClass=IprAccess 1028opLat=3 1029pipelined=false 1030 1031[system.cpu1.icache] 1032type=Cache 1033children=tags 1034addr_ranges=0:18446744073709551615 1035assoc=1 1036clk_domain=system.cpu_clk_domain 1037clusivity=mostly_incl 1038demand_mshr_reserve=1 1039eventq_index=0 1040hit_latency=2 1041is_read_only=true 1042max_miss_count=0 1043mshrs=4 1044prefetch_on_access=false 1045prefetcher=Null 1046response_latency=2 1047sequential_access=false 1048size=32768 1049system=system 1050tags=system.cpu1.icache.tags 1051tgts_per_mshr=20 1052write_buffers=8 1053writeback_clean=true 1054cpu_side=system.cpu1.icache_port 1055mem_side=system.toL2Bus.slave[2] 1056 1057[system.cpu1.icache.tags] 1058type=LRU 1059assoc=1 1060block_size=64 1061clk_domain=system.cpu_clk_domain 1062eventq_index=0 1063hit_latency=2 1064sequential_access=false 1065size=32768 1066 1067[system.cpu1.interrupts] 1068type=SparcInterrupts 1069eventq_index=0 1070 1071[system.cpu1.isa] 1072type=SparcISA 1073eventq_index=0 1074 1075[system.cpu1.itb] 1076type=SparcTLB 1077eventq_index=0 1078size=64 1079 1080[system.cpu1.tracer] 1081type=ExeTracer 1082eventq_index=0 1083 1084[system.cpu2] 1085type=DerivO3CPU 1086children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1087LFSTSize=1024 1088LQEntries=32 1089LSQCheckLoads=true 1090LSQDepCheckShift=4 1091SQEntries=32 1092SSITSize=1024 1093activity=0 1094backComSize=5 1095branchPred=system.cpu2.branchPred 1096cachePorts=200 1097checker=Null 1098clk_domain=system.cpu_clk_domain 1099commitToDecodeDelay=1 1100commitToFetchDelay=1 1101commitToIEWDelay=1 1102commitToRenameDelay=1 1103commitWidth=8 1104cpu_id=2 1105decodeToFetchDelay=1 1106decodeToRenameDelay=1 1107decodeWidth=8 1108dispatchWidth=8 1109do_checkpoint_insts=true 1110do_quiesce=true 1111do_statistics_insts=true 1112dtb=system.cpu2.dtb 1113eventq_index=0 1114fetchBufferSize=64 1115fetchQueueSize=32 1116fetchToDecodeDelay=1 1117fetchTrapLatency=1 1118fetchWidth=8 1119forwardComSize=5 1120fuPool=system.cpu2.fuPool 1121function_trace=false 1122function_trace_start=0 1123iewToCommitDelay=1 1124iewToDecodeDelay=1 1125iewToFetchDelay=1 1126iewToRenameDelay=1 1127interrupts=system.cpu2.interrupts 1128isa=system.cpu2.isa 1129issueToExecuteDelay=1 1130issueWidth=8 1131itb=system.cpu2.itb 1132max_insts_all_threads=0 1133max_insts_any_thread=0 1134max_loads_all_threads=0 1135max_loads_any_thread=0 1136needsTSO=false 1137numIQEntries=64 1138numPhysCCRegs=0 1139numPhysFloatRegs=256 1140numPhysIntRegs=256 1141numROBEntries=192 1142numRobs=1 1143numThreads=1 1144profile=0 1145progress_interval=0 1146renameToDecodeDelay=1 1147renameToFetchDelay=1 1148renameToIEWDelay=2 1149renameToROBDelay=1 1150renameWidth=8 1151simpoint_start_insts= 1152smtCommitPolicy=RoundRobin 1153smtFetchPolicy=SingleThread 1154smtIQPolicy=Partitioned 1155smtIQThreshold=100 1156smtLSQPolicy=Partitioned 1157smtLSQThreshold=100 1158smtNumFetchingThreads=1 1159smtROBPolicy=Partitioned 1160smtROBThreshold=100 1161socket_id=0 1162squashWidth=8 1163store_set_clear_period=250000 1164switched_out=false 1165system=system 1166tracer=system.cpu2.tracer 1167trapLatency=13 1168wbWidth=8 1169workload=system.cpu0.workload 1170dcache_port=system.cpu2.dcache.cpu_side 1171icache_port=system.cpu2.icache.cpu_side 1172 1173[system.cpu2.branchPred] 1174type=TournamentBP 1175BTBEntries=4096 1176BTBTagSize=16 1177RASSize=16 1178choiceCtrBits=2 1179choicePredictorSize=8192 1180eventq_index=0 1181globalCtrBits=2 1182globalPredictorSize=8192 1183instShiftAmt=2 1184localCtrBits=2 1185localHistoryTableSize=2048 1186localPredictorSize=2048 1187numThreads=1 1188 1189[system.cpu2.dcache] 1190type=Cache 1191children=tags 1192addr_ranges=0:18446744073709551615 1193assoc=4 1194clk_domain=system.cpu_clk_domain 1195clusivity=mostly_incl 1196demand_mshr_reserve=1 1197eventq_index=0 1198hit_latency=2 1199is_read_only=false 1200max_miss_count=0 1201mshrs=4 1202prefetch_on_access=false 1203prefetcher=Null 1204response_latency=2 1205sequential_access=false 1206size=32768 1207system=system 1208tags=system.cpu2.dcache.tags 1209tgts_per_mshr=20 1210write_buffers=8 1211writeback_clean=false 1212cpu_side=system.cpu2.dcache_port 1213mem_side=system.toL2Bus.slave[5] 1214 1215[system.cpu2.dcache.tags] 1216type=LRU 1217assoc=4 1218block_size=64 1219clk_domain=system.cpu_clk_domain 1220eventq_index=0 1221hit_latency=2 1222sequential_access=false 1223size=32768 1224 1225[system.cpu2.dtb] 1226type=SparcTLB 1227eventq_index=0 1228size=64 1229 1230[system.cpu2.fuPool] 1231type=FUPool 1232children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1233FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1234eventq_index=0 1235 1236[system.cpu2.fuPool.FUList0] 1237type=FUDesc 1238children=opList 1239count=6 1240eventq_index=0 1241opList=system.cpu2.fuPool.FUList0.opList 1242 1243[system.cpu2.fuPool.FUList0.opList] 1244type=OpDesc 1245eventq_index=0 1246opClass=IntAlu 1247opLat=1 1248pipelined=true 1249 1250[system.cpu2.fuPool.FUList1] 1251type=FUDesc 1252children=opList0 opList1 1253count=2 1254eventq_index=0 1255opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1256 1257[system.cpu2.fuPool.FUList1.opList0] 1258type=OpDesc 1259eventq_index=0 1260opClass=IntMult 1261opLat=3 1262pipelined=true 1263 1264[system.cpu2.fuPool.FUList1.opList1] 1265type=OpDesc 1266eventq_index=0 1267opClass=IntDiv 1268opLat=20 1269pipelined=false 1270 1271[system.cpu2.fuPool.FUList2] 1272type=FUDesc 1273children=opList0 opList1 opList2 1274count=4 1275eventq_index=0 1276opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1277 1278[system.cpu2.fuPool.FUList2.opList0] 1279type=OpDesc 1280eventq_index=0 1281opClass=FloatAdd 1282opLat=2 1283pipelined=true 1284 1285[system.cpu2.fuPool.FUList2.opList1] 1286type=OpDesc 1287eventq_index=0 1288opClass=FloatCmp 1289opLat=2 1290pipelined=true 1291 1292[system.cpu2.fuPool.FUList2.opList2] 1293type=OpDesc 1294eventq_index=0 1295opClass=FloatCvt 1296opLat=2 1297pipelined=true 1298 1299[system.cpu2.fuPool.FUList3] 1300type=FUDesc 1301children=opList0 opList1 opList2 1302count=2 1303eventq_index=0 1304opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1305 1306[system.cpu2.fuPool.FUList3.opList0] 1307type=OpDesc 1308eventq_index=0 1309opClass=FloatMult 1310opLat=4 1311pipelined=true 1312 1313[system.cpu2.fuPool.FUList3.opList1] 1314type=OpDesc 1315eventq_index=0 1316opClass=FloatDiv 1317opLat=12 1318pipelined=false 1319 1320[system.cpu2.fuPool.FUList3.opList2] 1321type=OpDesc 1322eventq_index=0 1323opClass=FloatSqrt 1324opLat=24 1325pipelined=false 1326 1327[system.cpu2.fuPool.FUList4] 1328type=FUDesc 1329children=opList 1330count=0 1331eventq_index=0 1332opList=system.cpu2.fuPool.FUList4.opList 1333 1334[system.cpu2.fuPool.FUList4.opList] 1335type=OpDesc 1336eventq_index=0 1337opClass=MemRead 1338opLat=1 1339pipelined=true 1340 1341[system.cpu2.fuPool.FUList5] 1342type=FUDesc 1343children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1344count=4 1345eventq_index=0 1346opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1347 1348[system.cpu2.fuPool.FUList5.opList00] 1349type=OpDesc 1350eventq_index=0 1351opClass=SimdAdd 1352opLat=1 1353pipelined=true 1354 1355[system.cpu2.fuPool.FUList5.opList01] 1356type=OpDesc 1357eventq_index=0 1358opClass=SimdAddAcc 1359opLat=1 1360pipelined=true 1361 1362[system.cpu2.fuPool.FUList5.opList02] 1363type=OpDesc 1364eventq_index=0 1365opClass=SimdAlu 1366opLat=1 1367pipelined=true 1368 1369[system.cpu2.fuPool.FUList5.opList03] 1370type=OpDesc 1371eventq_index=0 1372opClass=SimdCmp 1373opLat=1 1374pipelined=true 1375 1376[system.cpu2.fuPool.FUList5.opList04] 1377type=OpDesc 1378eventq_index=0 1379opClass=SimdCvt 1380opLat=1 1381pipelined=true 1382 1383[system.cpu2.fuPool.FUList5.opList05] 1384type=OpDesc 1385eventq_index=0 1386opClass=SimdMisc 1387opLat=1 1388pipelined=true 1389 1390[system.cpu2.fuPool.FUList5.opList06] 1391type=OpDesc 1392eventq_index=0 1393opClass=SimdMult 1394opLat=1 1395pipelined=true 1396 1397[system.cpu2.fuPool.FUList5.opList07] 1398type=OpDesc 1399eventq_index=0 1400opClass=SimdMultAcc 1401opLat=1 1402pipelined=true 1403 1404[system.cpu2.fuPool.FUList5.opList08] 1405type=OpDesc 1406eventq_index=0 1407opClass=SimdShift 1408opLat=1 1409pipelined=true 1410 1411[system.cpu2.fuPool.FUList5.opList09] 1412type=OpDesc 1413eventq_index=0 1414opClass=SimdShiftAcc 1415opLat=1 1416pipelined=true 1417 1418[system.cpu2.fuPool.FUList5.opList10] 1419type=OpDesc 1420eventq_index=0 1421opClass=SimdSqrt 1422opLat=1 1423pipelined=true 1424 1425[system.cpu2.fuPool.FUList5.opList11] 1426type=OpDesc 1427eventq_index=0 1428opClass=SimdFloatAdd 1429opLat=1 1430pipelined=true 1431 1432[system.cpu2.fuPool.FUList5.opList12] 1433type=OpDesc 1434eventq_index=0 1435opClass=SimdFloatAlu 1436opLat=1 1437pipelined=true 1438 1439[system.cpu2.fuPool.FUList5.opList13] 1440type=OpDesc 1441eventq_index=0 1442opClass=SimdFloatCmp 1443opLat=1 1444pipelined=true 1445 1446[system.cpu2.fuPool.FUList5.opList14] 1447type=OpDesc 1448eventq_index=0 1449opClass=SimdFloatCvt 1450opLat=1 1451pipelined=true 1452 1453[system.cpu2.fuPool.FUList5.opList15] 1454type=OpDesc 1455eventq_index=0 1456opClass=SimdFloatDiv 1457opLat=1 1458pipelined=true 1459 1460[system.cpu2.fuPool.FUList5.opList16] 1461type=OpDesc 1462eventq_index=0 1463opClass=SimdFloatMisc 1464opLat=1 1465pipelined=true 1466 1467[system.cpu2.fuPool.FUList5.opList17] 1468type=OpDesc 1469eventq_index=0 1470opClass=SimdFloatMult 1471opLat=1 1472pipelined=true 1473 1474[system.cpu2.fuPool.FUList5.opList18] 1475type=OpDesc 1476eventq_index=0 1477opClass=SimdFloatMultAcc 1478opLat=1 1479pipelined=true 1480 1481[system.cpu2.fuPool.FUList5.opList19] 1482type=OpDesc 1483eventq_index=0 1484opClass=SimdFloatSqrt 1485opLat=1 1486pipelined=true 1487 1488[system.cpu2.fuPool.FUList6] 1489type=FUDesc 1490children=opList 1491count=0 1492eventq_index=0 1493opList=system.cpu2.fuPool.FUList6.opList 1494 1495[system.cpu2.fuPool.FUList6.opList] 1496type=OpDesc 1497eventq_index=0 1498opClass=MemWrite 1499opLat=1 1500pipelined=true 1501 1502[system.cpu2.fuPool.FUList7] 1503type=FUDesc 1504children=opList0 opList1 1505count=4 1506eventq_index=0 1507opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1508 1509[system.cpu2.fuPool.FUList7.opList0] 1510type=OpDesc 1511eventq_index=0 1512opClass=MemRead 1513opLat=1 1514pipelined=true 1515 1516[system.cpu2.fuPool.FUList7.opList1] 1517type=OpDesc 1518eventq_index=0 1519opClass=MemWrite 1520opLat=1 1521pipelined=true 1522 1523[system.cpu2.fuPool.FUList8] 1524type=FUDesc 1525children=opList 1526count=1 1527eventq_index=0 1528opList=system.cpu2.fuPool.FUList8.opList 1529 1530[system.cpu2.fuPool.FUList8.opList] 1531type=OpDesc 1532eventq_index=0 1533opClass=IprAccess 1534opLat=3 1535pipelined=false 1536 1537[system.cpu2.icache] 1538type=Cache 1539children=tags 1540addr_ranges=0:18446744073709551615 1541assoc=1 1542clk_domain=system.cpu_clk_domain 1543clusivity=mostly_incl 1544demand_mshr_reserve=1 1545eventq_index=0 1546hit_latency=2 1547is_read_only=true 1548max_miss_count=0 1549mshrs=4 1550prefetch_on_access=false 1551prefetcher=Null 1552response_latency=2 1553sequential_access=false 1554size=32768 1555system=system 1556tags=system.cpu2.icache.tags 1557tgts_per_mshr=20 1558write_buffers=8 1559writeback_clean=true 1560cpu_side=system.cpu2.icache_port 1561mem_side=system.toL2Bus.slave[4] 1562 1563[system.cpu2.icache.tags] 1564type=LRU 1565assoc=1 1566block_size=64 1567clk_domain=system.cpu_clk_domain 1568eventq_index=0 1569hit_latency=2 1570sequential_access=false 1571size=32768 1572 1573[system.cpu2.interrupts] 1574type=SparcInterrupts 1575eventq_index=0 1576 1577[system.cpu2.isa] 1578type=SparcISA 1579eventq_index=0 1580 1581[system.cpu2.itb] 1582type=SparcTLB 1583eventq_index=0 1584size=64 1585 1586[system.cpu2.tracer] 1587type=ExeTracer 1588eventq_index=0 1589 1590[system.cpu3] 1591type=DerivO3CPU 1592children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1593LFSTSize=1024 1594LQEntries=32 1595LSQCheckLoads=true 1596LSQDepCheckShift=4 1597SQEntries=32 1598SSITSize=1024 1599activity=0 1600backComSize=5 1601branchPred=system.cpu3.branchPred 1602cachePorts=200 1603checker=Null 1604clk_domain=system.cpu_clk_domain 1605commitToDecodeDelay=1 1606commitToFetchDelay=1 1607commitToIEWDelay=1 1608commitToRenameDelay=1 1609commitWidth=8 1610cpu_id=3 1611decodeToFetchDelay=1 1612decodeToRenameDelay=1 1613decodeWidth=8 1614dispatchWidth=8 1615do_checkpoint_insts=true 1616do_quiesce=true 1617do_statistics_insts=true 1618dtb=system.cpu3.dtb 1619eventq_index=0 1620fetchBufferSize=64 1621fetchQueueSize=32 1622fetchToDecodeDelay=1 1623fetchTrapLatency=1 1624fetchWidth=8 1625forwardComSize=5 1626fuPool=system.cpu3.fuPool 1627function_trace=false 1628function_trace_start=0 1629iewToCommitDelay=1 1630iewToDecodeDelay=1 1631iewToFetchDelay=1 1632iewToRenameDelay=1 1633interrupts=system.cpu3.interrupts 1634isa=system.cpu3.isa 1635issueToExecuteDelay=1 1636issueWidth=8 1637itb=system.cpu3.itb 1638max_insts_all_threads=0 1639max_insts_any_thread=0 1640max_loads_all_threads=0 1641max_loads_any_thread=0 1642needsTSO=false 1643numIQEntries=64 1644numPhysCCRegs=0 1645numPhysFloatRegs=256 1646numPhysIntRegs=256 1647numROBEntries=192 1648numRobs=1 1649numThreads=1 1650profile=0 1651progress_interval=0 1652renameToDecodeDelay=1 1653renameToFetchDelay=1 1654renameToIEWDelay=2 1655renameToROBDelay=1 1656renameWidth=8 1657simpoint_start_insts= 1658smtCommitPolicy=RoundRobin 1659smtFetchPolicy=SingleThread 1660smtIQPolicy=Partitioned 1661smtIQThreshold=100 1662smtLSQPolicy=Partitioned 1663smtLSQThreshold=100 1664smtNumFetchingThreads=1 1665smtROBPolicy=Partitioned 1666smtROBThreshold=100 1667socket_id=0 1668squashWidth=8 1669store_set_clear_period=250000 1670switched_out=false 1671system=system 1672tracer=system.cpu3.tracer 1673trapLatency=13 1674wbWidth=8 1675workload=system.cpu0.workload 1676dcache_port=system.cpu3.dcache.cpu_side 1677icache_port=system.cpu3.icache.cpu_side 1678 1679[system.cpu3.branchPred] 1680type=TournamentBP 1681BTBEntries=4096 1682BTBTagSize=16 1683RASSize=16 1684choiceCtrBits=2 1685choicePredictorSize=8192 1686eventq_index=0 1687globalCtrBits=2 1688globalPredictorSize=8192 1689instShiftAmt=2 1690localCtrBits=2 1691localHistoryTableSize=2048 1692localPredictorSize=2048 1693numThreads=1 1694 1695[system.cpu3.dcache] 1696type=Cache 1697children=tags 1698addr_ranges=0:18446744073709551615 1699assoc=4 1700clk_domain=system.cpu_clk_domain 1701clusivity=mostly_incl 1702demand_mshr_reserve=1 1703eventq_index=0 1704hit_latency=2 1705is_read_only=false 1706max_miss_count=0 1707mshrs=4 1708prefetch_on_access=false 1709prefetcher=Null 1710response_latency=2 1711sequential_access=false 1712size=32768 1713system=system 1714tags=system.cpu3.dcache.tags 1715tgts_per_mshr=20 1716write_buffers=8 1717writeback_clean=false 1718cpu_side=system.cpu3.dcache_port 1719mem_side=system.toL2Bus.slave[7] 1720 1721[system.cpu3.dcache.tags] 1722type=LRU 1723assoc=4 1724block_size=64 1725clk_domain=system.cpu_clk_domain 1726eventq_index=0 1727hit_latency=2 1728sequential_access=false 1729size=32768 1730 1731[system.cpu3.dtb] 1732type=SparcTLB 1733eventq_index=0 1734size=64 1735 1736[system.cpu3.fuPool] 1737type=FUPool 1738children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1739FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1740eventq_index=0 1741 1742[system.cpu3.fuPool.FUList0] 1743type=FUDesc 1744children=opList 1745count=6 1746eventq_index=0 1747opList=system.cpu3.fuPool.FUList0.opList 1748 1749[system.cpu3.fuPool.FUList0.opList] 1750type=OpDesc 1751eventq_index=0 1752opClass=IntAlu 1753opLat=1 1754pipelined=true 1755 1756[system.cpu3.fuPool.FUList1] 1757type=FUDesc 1758children=opList0 opList1 1759count=2 1760eventq_index=0 1761opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1762 1763[system.cpu3.fuPool.FUList1.opList0] 1764type=OpDesc 1765eventq_index=0 1766opClass=IntMult 1767opLat=3 1768pipelined=true 1769 1770[system.cpu3.fuPool.FUList1.opList1] 1771type=OpDesc 1772eventq_index=0 1773opClass=IntDiv 1774opLat=20 1775pipelined=false 1776 1777[system.cpu3.fuPool.FUList2] 1778type=FUDesc 1779children=opList0 opList1 opList2 1780count=4 1781eventq_index=0 1782opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1783 1784[system.cpu3.fuPool.FUList2.opList0] 1785type=OpDesc 1786eventq_index=0 1787opClass=FloatAdd 1788opLat=2 1789pipelined=true 1790 1791[system.cpu3.fuPool.FUList2.opList1] 1792type=OpDesc 1793eventq_index=0 1794opClass=FloatCmp 1795opLat=2 1796pipelined=true 1797 1798[system.cpu3.fuPool.FUList2.opList2] 1799type=OpDesc 1800eventq_index=0 1801opClass=FloatCvt 1802opLat=2 1803pipelined=true 1804 1805[system.cpu3.fuPool.FUList3] 1806type=FUDesc 1807children=opList0 opList1 opList2 1808count=2 1809eventq_index=0 1810opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1811 1812[system.cpu3.fuPool.FUList3.opList0] 1813type=OpDesc 1814eventq_index=0 1815opClass=FloatMult 1816opLat=4 1817pipelined=true 1818 1819[system.cpu3.fuPool.FUList3.opList1] 1820type=OpDesc 1821eventq_index=0 1822opClass=FloatDiv 1823opLat=12 1824pipelined=false 1825 1826[system.cpu3.fuPool.FUList3.opList2] 1827type=OpDesc 1828eventq_index=0 1829opClass=FloatSqrt 1830opLat=24 1831pipelined=false 1832 1833[system.cpu3.fuPool.FUList4] 1834type=FUDesc 1835children=opList 1836count=0 1837eventq_index=0 1838opList=system.cpu3.fuPool.FUList4.opList 1839 1840[system.cpu3.fuPool.FUList4.opList] 1841type=OpDesc 1842eventq_index=0 1843opClass=MemRead 1844opLat=1 1845pipelined=true 1846 1847[system.cpu3.fuPool.FUList5] 1848type=FUDesc 1849children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1850count=4 1851eventq_index=0 1852opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1853 1854[system.cpu3.fuPool.FUList5.opList00] 1855type=OpDesc 1856eventq_index=0 1857opClass=SimdAdd 1858opLat=1 1859pipelined=true 1860 1861[system.cpu3.fuPool.FUList5.opList01] 1862type=OpDesc 1863eventq_index=0 1864opClass=SimdAddAcc 1865opLat=1 1866pipelined=true 1867 1868[system.cpu3.fuPool.FUList5.opList02] 1869type=OpDesc 1870eventq_index=0 1871opClass=SimdAlu 1872opLat=1 1873pipelined=true 1874 1875[system.cpu3.fuPool.FUList5.opList03] 1876type=OpDesc 1877eventq_index=0 1878opClass=SimdCmp 1879opLat=1 1880pipelined=true 1881 1882[system.cpu3.fuPool.FUList5.opList04] 1883type=OpDesc 1884eventq_index=0 1885opClass=SimdCvt 1886opLat=1 1887pipelined=true 1888 1889[system.cpu3.fuPool.FUList5.opList05] 1890type=OpDesc 1891eventq_index=0 1892opClass=SimdMisc 1893opLat=1 1894pipelined=true 1895 1896[system.cpu3.fuPool.FUList5.opList06] 1897type=OpDesc 1898eventq_index=0 1899opClass=SimdMult 1900opLat=1 1901pipelined=true 1902 1903[system.cpu3.fuPool.FUList5.opList07] 1904type=OpDesc 1905eventq_index=0 1906opClass=SimdMultAcc 1907opLat=1 1908pipelined=true 1909 1910[system.cpu3.fuPool.FUList5.opList08] 1911type=OpDesc 1912eventq_index=0 1913opClass=SimdShift 1914opLat=1 1915pipelined=true 1916 1917[system.cpu3.fuPool.FUList5.opList09] 1918type=OpDesc 1919eventq_index=0 1920opClass=SimdShiftAcc 1921opLat=1 1922pipelined=true 1923 1924[system.cpu3.fuPool.FUList5.opList10] 1925type=OpDesc 1926eventq_index=0 1927opClass=SimdSqrt 1928opLat=1 1929pipelined=true 1930 1931[system.cpu3.fuPool.FUList5.opList11] 1932type=OpDesc 1933eventq_index=0 1934opClass=SimdFloatAdd 1935opLat=1 1936pipelined=true 1937 1938[system.cpu3.fuPool.FUList5.opList12] 1939type=OpDesc 1940eventq_index=0 1941opClass=SimdFloatAlu 1942opLat=1 1943pipelined=true 1944 1945[system.cpu3.fuPool.FUList5.opList13] 1946type=OpDesc 1947eventq_index=0 1948opClass=SimdFloatCmp 1949opLat=1 1950pipelined=true 1951 1952[system.cpu3.fuPool.FUList5.opList14] 1953type=OpDesc 1954eventq_index=0 1955opClass=SimdFloatCvt 1956opLat=1 1957pipelined=true 1958 1959[system.cpu3.fuPool.FUList5.opList15] 1960type=OpDesc 1961eventq_index=0 1962opClass=SimdFloatDiv 1963opLat=1 1964pipelined=true 1965 1966[system.cpu3.fuPool.FUList5.opList16] 1967type=OpDesc 1968eventq_index=0 1969opClass=SimdFloatMisc 1970opLat=1 1971pipelined=true 1972 1973[system.cpu3.fuPool.FUList5.opList17] 1974type=OpDesc 1975eventq_index=0 1976opClass=SimdFloatMult 1977opLat=1 1978pipelined=true 1979 1980[system.cpu3.fuPool.FUList5.opList18] 1981type=OpDesc 1982eventq_index=0 1983opClass=SimdFloatMultAcc 1984opLat=1 1985pipelined=true 1986 1987[system.cpu3.fuPool.FUList5.opList19] 1988type=OpDesc 1989eventq_index=0 1990opClass=SimdFloatSqrt 1991opLat=1 1992pipelined=true 1993 1994[system.cpu3.fuPool.FUList6] 1995type=FUDesc 1996children=opList 1997count=0 1998eventq_index=0 1999opList=system.cpu3.fuPool.FUList6.opList 2000 2001[system.cpu3.fuPool.FUList6.opList] 2002type=OpDesc 2003eventq_index=0 2004opClass=MemWrite 2005opLat=1 2006pipelined=true 2007 2008[system.cpu3.fuPool.FUList7] 2009type=FUDesc 2010children=opList0 opList1 2011count=4 2012eventq_index=0 2013opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 2014 2015[system.cpu3.fuPool.FUList7.opList0] 2016type=OpDesc 2017eventq_index=0 2018opClass=MemRead 2019opLat=1 2020pipelined=true 2021 2022[system.cpu3.fuPool.FUList7.opList1] 2023type=OpDesc 2024eventq_index=0 2025opClass=MemWrite 2026opLat=1 2027pipelined=true 2028 2029[system.cpu3.fuPool.FUList8] 2030type=FUDesc 2031children=opList 2032count=1 2033eventq_index=0 2034opList=system.cpu3.fuPool.FUList8.opList 2035 2036[system.cpu3.fuPool.FUList8.opList] 2037type=OpDesc 2038eventq_index=0 2039opClass=IprAccess 2040opLat=3 2041pipelined=false 2042 2043[system.cpu3.icache] 2044type=Cache 2045children=tags 2046addr_ranges=0:18446744073709551615 2047assoc=1 2048clk_domain=system.cpu_clk_domain 2049clusivity=mostly_incl 2050demand_mshr_reserve=1 2051eventq_index=0 2052hit_latency=2 2053is_read_only=true 2054max_miss_count=0 2055mshrs=4 2056prefetch_on_access=false 2057prefetcher=Null 2058response_latency=2 2059sequential_access=false 2060size=32768 2061system=system 2062tags=system.cpu3.icache.tags 2063tgts_per_mshr=20 2064write_buffers=8 2065writeback_clean=true 2066cpu_side=system.cpu3.icache_port 2067mem_side=system.toL2Bus.slave[6] 2068 2069[system.cpu3.icache.tags] 2070type=LRU 2071assoc=1 2072block_size=64 2073clk_domain=system.cpu_clk_domain 2074eventq_index=0 2075hit_latency=2 2076sequential_access=false 2077size=32768 2078 2079[system.cpu3.interrupts] 2080type=SparcInterrupts 2081eventq_index=0 2082 2083[system.cpu3.isa] 2084type=SparcISA 2085eventq_index=0 2086 2087[system.cpu3.itb] 2088type=SparcTLB 2089eventq_index=0 2090size=64 2091 2092[system.cpu3.tracer] 2093type=ExeTracer 2094eventq_index=0 2095 2096[system.cpu_clk_domain] 2097type=SrcClockDomain 2098clock=500 2099domain_id=-1 2100eventq_index=0 2101init_perf_level=0 2102voltage_domain=system.voltage_domain 2103 2104[system.dvfs_handler] 2105type=DVFSHandler 2106domains= 2107enable=false 2108eventq_index=0 2109sys_clk_domain=system.clk_domain 2110transition_latency=100000000 2111 2112[system.l2c] 2113type=Cache 2114children=tags 2115addr_ranges=0:18446744073709551615 2116assoc=8 2117clk_domain=system.cpu_clk_domain 2118clusivity=mostly_incl 2119demand_mshr_reserve=1 2120eventq_index=0 2121hit_latency=20 2122is_read_only=false 2123max_miss_count=0 2124mshrs=20 2125prefetch_on_access=false 2126prefetcher=Null 2127response_latency=20 2128sequential_access=false 2129size=4194304 2130system=system 2131tags=system.l2c.tags 2132tgts_per_mshr=12 2133write_buffers=8 2134writeback_clean=false 2135cpu_side=system.toL2Bus.master[0] 2136mem_side=system.membus.slave[1] 2137 2138[system.l2c.tags] 2139type=LRU 2140assoc=8 2141block_size=64 2142clk_domain=system.cpu_clk_domain 2143eventq_index=0 2144hit_latency=20 2145sequential_access=false 2146size=4194304 2147 2148[system.membus] 2149type=CoherentXBar 2150clk_domain=system.clk_domain 2151eventq_index=0 2152forward_latency=4 2153frontend_latency=3 2154point_of_coherency=true 2155response_latency=2 2156snoop_filter=Null 2157snoop_response_latency=4 2158system=system 2159use_default_range=false 2160width=16 2161master=system.physmem.port 2162slave=system.system_port system.l2c.mem_side 2163 2164[system.physmem] 2165type=DRAMCtrl 2166IDD0=0.075000 2167IDD02=0.000000 2168IDD2N=0.050000 2169IDD2N2=0.000000 2170IDD2P0=0.000000 2171IDD2P02=0.000000 2172IDD2P1=0.000000 2173IDD2P12=0.000000 2174IDD3N=0.057000 2175IDD3N2=0.000000 2176IDD3P0=0.000000 2177IDD3P02=0.000000 2178IDD3P1=0.000000 2179IDD3P12=0.000000 2180IDD4R=0.187000 2181IDD4R2=0.000000 2182IDD4W=0.165000 2183IDD4W2=0.000000 2184IDD5=0.220000 2185IDD52=0.000000 2186IDD6=0.000000 2187IDD62=0.000000 2188VDD=1.500000 2189VDD2=0.000000 2190activation_limit=4 2191addr_mapping=RoRaBaCoCh 2192bank_groups_per_rank=0 2193banks_per_rank=8 2194burst_length=8 2195channels=1 2196clk_domain=system.clk_domain 2197conf_table_reported=true 2198device_bus_width=8 2199device_rowbuffer_size=1024 2200device_size=536870912 2201devices_per_rank=8 2202dll=true 2203eventq_index=0 2204in_addr_map=true 2205max_accesses_per_row=16 2206mem_sched_policy=frfcfs 2207min_writes_per_switch=16 2208null=false 2209page_policy=open_adaptive 2210range=0:134217727 2211ranks_per_channel=2 2212read_buffer_size=32 2213static_backend_latency=10000 2214static_frontend_latency=10000 2215tBURST=5000 2216tCCD_L=0 2217tCK=1250 2218tCL=13750 2219tCS=2500 2220tRAS=35000 2221tRCD=13750 2222tREFI=7800000 2223tRFC=260000 2224tRP=13750 2225tRRD=6000 2226tRRD_L=0 2227tRTP=7500 2228tRTW=2500 2229tWR=15000 2230tWTR=7500 2231tXAW=30000 2232tXP=0 2233tXPDLL=0 2234tXS=0 2235tXSDLL=0 2236write_buffer_size=64 2237write_high_thresh_perc=85 2238write_low_thresh_perc=50 2239port=system.membus.master[0] 2240 2241[system.toL2Bus] 2242type=CoherentXBar 2243children=snoop_filter 2244clk_domain=system.cpu_clk_domain 2245eventq_index=0 2246forward_latency=0 2247frontend_latency=1 2248point_of_coherency=false 2249response_latency=1 2250snoop_filter=system.toL2Bus.snoop_filter 2251snoop_response_latency=1 2252system=system 2253use_default_range=false 2254width=32 2255master=system.l2c.cpu_side 2256slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2257 2258[system.toL2Bus.snoop_filter] 2259type=SnoopFilter 2260eventq_index=0 2261lookup_latency=0 2262max_capacity=8388608 2263system=system 2264 2265[system.voltage_domain] 2266type=VoltageDomain 2267eventq_index=0 2268voltage=1.000000 2269 2270