config.ini revision 11312:3d7a85d71bd1
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu0] 50type=DerivO3CPU 51children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 52LFSTSize=1024 53LQEntries=32 54LSQCheckLoads=true 55LSQDepCheckShift=4 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60branchPred=system.cpu0.branchPred 61cachePorts=200 62checker=Null 63clk_domain=system.cpu_clk_domain 64commitToDecodeDelay=1 65commitToFetchDelay=1 66commitToIEWDelay=1 67commitToRenameDelay=1 68commitWidth=8 69cpu_id=0 70decodeToFetchDelay=1 71decodeToRenameDelay=1 72decodeWidth=8 73dispatchWidth=8 74do_checkpoint_insts=true 75do_quiesce=true 76do_statistics_insts=true 77dtb=system.cpu0.dtb 78eventq_index=0 79fetchBufferSize=64 80fetchQueueSize=32 81fetchToDecodeDelay=1 82fetchTrapLatency=1 83fetchWidth=8 84forwardComSize=5 85fuPool=system.cpu0.fuPool 86function_trace=false 87function_trace_start=0 88iewToCommitDelay=1 89iewToDecodeDelay=1 90iewToFetchDelay=1 91iewToRenameDelay=1 92interrupts=system.cpu0.interrupts 93isa=system.cpu0.isa 94issueToExecuteDelay=1 95issueWidth=8 96itb=system.cpu0.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=false 102numIQEntries=64 103numPhysCCRegs=0 104numPhysFloatRegs=256 105numPhysIntRegs=256 106numROBEntries=192 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=2 114renameToROBDelay=1 115renameWidth=8 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu0.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu0.workload 135dcache_port=system.cpu0.dcache.cpu_side 136icache_port=system.cpu0.icache.cpu_side 137 138[system.cpu0.branchPred] 139type=TournamentBP 140BTBEntries=4096 141BTBTagSize=16 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149localCtrBits=2 150localHistoryTableSize=2048 151localPredictorSize=2048 152numThreads=1 153 154[system.cpu0.dcache] 155type=Cache 156children=tags 157addr_ranges=0:18446744073709551615 158assoc=4 159clk_domain=system.cpu_clk_domain 160clusivity=mostly_incl 161demand_mshr_reserve=1 162eventq_index=0 163forward_snoops=true 164hit_latency=2 165is_read_only=false 166max_miss_count=0 167mshrs=4 168prefetch_on_access=false 169prefetcher=Null 170response_latency=2 171sequential_access=false 172size=32768 173system=system 174tags=system.cpu0.dcache.tags 175tgts_per_mshr=20 176write_buffers=8 177writeback_clean=false 178cpu_side=system.cpu0.dcache_port 179mem_side=system.toL2Bus.slave[1] 180 181[system.cpu0.dcache.tags] 182type=LRU 183assoc=4 184block_size=64 185clk_domain=system.cpu_clk_domain 186eventq_index=0 187hit_latency=2 188sequential_access=false 189size=32768 190 191[system.cpu0.dtb] 192type=SparcTLB 193eventq_index=0 194size=64 195 196[system.cpu0.fuPool] 197type=FUPool 198children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 199FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 200eventq_index=0 201 202[system.cpu0.fuPool.FUList0] 203type=FUDesc 204children=opList 205count=6 206eventq_index=0 207opList=system.cpu0.fuPool.FUList0.opList 208 209[system.cpu0.fuPool.FUList0.opList] 210type=OpDesc 211eventq_index=0 212opClass=IntAlu 213opLat=1 214pipelined=true 215 216[system.cpu0.fuPool.FUList1] 217type=FUDesc 218children=opList0 opList1 219count=2 220eventq_index=0 221opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 222 223[system.cpu0.fuPool.FUList1.opList0] 224type=OpDesc 225eventq_index=0 226opClass=IntMult 227opLat=3 228pipelined=true 229 230[system.cpu0.fuPool.FUList1.opList1] 231type=OpDesc 232eventq_index=0 233opClass=IntDiv 234opLat=20 235pipelined=false 236 237[system.cpu0.fuPool.FUList2] 238type=FUDesc 239children=opList0 opList1 opList2 240count=4 241eventq_index=0 242opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 243 244[system.cpu0.fuPool.FUList2.opList0] 245type=OpDesc 246eventq_index=0 247opClass=FloatAdd 248opLat=2 249pipelined=true 250 251[system.cpu0.fuPool.FUList2.opList1] 252type=OpDesc 253eventq_index=0 254opClass=FloatCmp 255opLat=2 256pipelined=true 257 258[system.cpu0.fuPool.FUList2.opList2] 259type=OpDesc 260eventq_index=0 261opClass=FloatCvt 262opLat=2 263pipelined=true 264 265[system.cpu0.fuPool.FUList3] 266type=FUDesc 267children=opList0 opList1 opList2 268count=2 269eventq_index=0 270opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 271 272[system.cpu0.fuPool.FUList3.opList0] 273type=OpDesc 274eventq_index=0 275opClass=FloatMult 276opLat=4 277pipelined=true 278 279[system.cpu0.fuPool.FUList3.opList1] 280type=OpDesc 281eventq_index=0 282opClass=FloatDiv 283opLat=12 284pipelined=false 285 286[system.cpu0.fuPool.FUList3.opList2] 287type=OpDesc 288eventq_index=0 289opClass=FloatSqrt 290opLat=24 291pipelined=false 292 293[system.cpu0.fuPool.FUList4] 294type=FUDesc 295children=opList 296count=0 297eventq_index=0 298opList=system.cpu0.fuPool.FUList4.opList 299 300[system.cpu0.fuPool.FUList4.opList] 301type=OpDesc 302eventq_index=0 303opClass=MemRead 304opLat=1 305pipelined=true 306 307[system.cpu0.fuPool.FUList5] 308type=FUDesc 309children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 310count=4 311eventq_index=0 312opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 313 314[system.cpu0.fuPool.FUList5.opList00] 315type=OpDesc 316eventq_index=0 317opClass=SimdAdd 318opLat=1 319pipelined=true 320 321[system.cpu0.fuPool.FUList5.opList01] 322type=OpDesc 323eventq_index=0 324opClass=SimdAddAcc 325opLat=1 326pipelined=true 327 328[system.cpu0.fuPool.FUList5.opList02] 329type=OpDesc 330eventq_index=0 331opClass=SimdAlu 332opLat=1 333pipelined=true 334 335[system.cpu0.fuPool.FUList5.opList03] 336type=OpDesc 337eventq_index=0 338opClass=SimdCmp 339opLat=1 340pipelined=true 341 342[system.cpu0.fuPool.FUList5.opList04] 343type=OpDesc 344eventq_index=0 345opClass=SimdCvt 346opLat=1 347pipelined=true 348 349[system.cpu0.fuPool.FUList5.opList05] 350type=OpDesc 351eventq_index=0 352opClass=SimdMisc 353opLat=1 354pipelined=true 355 356[system.cpu0.fuPool.FUList5.opList06] 357type=OpDesc 358eventq_index=0 359opClass=SimdMult 360opLat=1 361pipelined=true 362 363[system.cpu0.fuPool.FUList5.opList07] 364type=OpDesc 365eventq_index=0 366opClass=SimdMultAcc 367opLat=1 368pipelined=true 369 370[system.cpu0.fuPool.FUList5.opList08] 371type=OpDesc 372eventq_index=0 373opClass=SimdShift 374opLat=1 375pipelined=true 376 377[system.cpu0.fuPool.FUList5.opList09] 378type=OpDesc 379eventq_index=0 380opClass=SimdShiftAcc 381opLat=1 382pipelined=true 383 384[system.cpu0.fuPool.FUList5.opList10] 385type=OpDesc 386eventq_index=0 387opClass=SimdSqrt 388opLat=1 389pipelined=true 390 391[system.cpu0.fuPool.FUList5.opList11] 392type=OpDesc 393eventq_index=0 394opClass=SimdFloatAdd 395opLat=1 396pipelined=true 397 398[system.cpu0.fuPool.FUList5.opList12] 399type=OpDesc 400eventq_index=0 401opClass=SimdFloatAlu 402opLat=1 403pipelined=true 404 405[system.cpu0.fuPool.FUList5.opList13] 406type=OpDesc 407eventq_index=0 408opClass=SimdFloatCmp 409opLat=1 410pipelined=true 411 412[system.cpu0.fuPool.FUList5.opList14] 413type=OpDesc 414eventq_index=0 415opClass=SimdFloatCvt 416opLat=1 417pipelined=true 418 419[system.cpu0.fuPool.FUList5.opList15] 420type=OpDesc 421eventq_index=0 422opClass=SimdFloatDiv 423opLat=1 424pipelined=true 425 426[system.cpu0.fuPool.FUList5.opList16] 427type=OpDesc 428eventq_index=0 429opClass=SimdFloatMisc 430opLat=1 431pipelined=true 432 433[system.cpu0.fuPool.FUList5.opList17] 434type=OpDesc 435eventq_index=0 436opClass=SimdFloatMult 437opLat=1 438pipelined=true 439 440[system.cpu0.fuPool.FUList5.opList18] 441type=OpDesc 442eventq_index=0 443opClass=SimdFloatMultAcc 444opLat=1 445pipelined=true 446 447[system.cpu0.fuPool.FUList5.opList19] 448type=OpDesc 449eventq_index=0 450opClass=SimdFloatSqrt 451opLat=1 452pipelined=true 453 454[system.cpu0.fuPool.FUList6] 455type=FUDesc 456children=opList 457count=0 458eventq_index=0 459opList=system.cpu0.fuPool.FUList6.opList 460 461[system.cpu0.fuPool.FUList6.opList] 462type=OpDesc 463eventq_index=0 464opClass=MemWrite 465opLat=1 466pipelined=true 467 468[system.cpu0.fuPool.FUList7] 469type=FUDesc 470children=opList0 opList1 471count=4 472eventq_index=0 473opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 474 475[system.cpu0.fuPool.FUList7.opList0] 476type=OpDesc 477eventq_index=0 478opClass=MemRead 479opLat=1 480pipelined=true 481 482[system.cpu0.fuPool.FUList7.opList1] 483type=OpDesc 484eventq_index=0 485opClass=MemWrite 486opLat=1 487pipelined=true 488 489[system.cpu0.fuPool.FUList8] 490type=FUDesc 491children=opList 492count=1 493eventq_index=0 494opList=system.cpu0.fuPool.FUList8.opList 495 496[system.cpu0.fuPool.FUList8.opList] 497type=OpDesc 498eventq_index=0 499opClass=IprAccess 500opLat=3 501pipelined=false 502 503[system.cpu0.icache] 504type=Cache 505children=tags 506addr_ranges=0:18446744073709551615 507assoc=1 508clk_domain=system.cpu_clk_domain 509clusivity=mostly_incl 510demand_mshr_reserve=1 511eventq_index=0 512forward_snoops=true 513hit_latency=2 514is_read_only=true 515max_miss_count=0 516mshrs=4 517prefetch_on_access=false 518prefetcher=Null 519response_latency=2 520sequential_access=false 521size=32768 522system=system 523tags=system.cpu0.icache.tags 524tgts_per_mshr=20 525write_buffers=8 526writeback_clean=true 527cpu_side=system.cpu0.icache_port 528mem_side=system.toL2Bus.slave[0] 529 530[system.cpu0.icache.tags] 531type=LRU 532assoc=1 533block_size=64 534clk_domain=system.cpu_clk_domain 535eventq_index=0 536hit_latency=2 537sequential_access=false 538size=32768 539 540[system.cpu0.interrupts] 541type=SparcInterrupts 542eventq_index=0 543 544[system.cpu0.isa] 545type=SparcISA 546eventq_index=0 547 548[system.cpu0.itb] 549type=SparcTLB 550eventq_index=0 551size=64 552 553[system.cpu0.tracer] 554type=ExeTracer 555eventq_index=0 556 557[system.cpu0.workload] 558type=LiveProcess 559cmd=test_atomic 4 560cwd= 561drivers= 562egid=100 563env= 564errout=cerr 565euid=100 566eventq_index=0 567executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic 568gid=100 569input=cin 570kvmInSE=false 571max_stack_size=67108864 572output=cout 573pid=100 574ppid=99 575simpoint=0 576system=system 577uid=100 578useArchPT=false 579 580[system.cpu1] 581type=DerivO3CPU 582children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 583LFSTSize=1024 584LQEntries=32 585LSQCheckLoads=true 586LSQDepCheckShift=4 587SQEntries=32 588SSITSize=1024 589activity=0 590backComSize=5 591branchPred=system.cpu1.branchPred 592cachePorts=200 593checker=Null 594clk_domain=system.cpu_clk_domain 595commitToDecodeDelay=1 596commitToFetchDelay=1 597commitToIEWDelay=1 598commitToRenameDelay=1 599commitWidth=8 600cpu_id=1 601decodeToFetchDelay=1 602decodeToRenameDelay=1 603decodeWidth=8 604dispatchWidth=8 605do_checkpoint_insts=true 606do_quiesce=true 607do_statistics_insts=true 608dtb=system.cpu1.dtb 609eventq_index=0 610fetchBufferSize=64 611fetchQueueSize=32 612fetchToDecodeDelay=1 613fetchTrapLatency=1 614fetchWidth=8 615forwardComSize=5 616fuPool=system.cpu1.fuPool 617function_trace=false 618function_trace_start=0 619iewToCommitDelay=1 620iewToDecodeDelay=1 621iewToFetchDelay=1 622iewToRenameDelay=1 623interrupts=system.cpu1.interrupts 624isa=system.cpu1.isa 625issueToExecuteDelay=1 626issueWidth=8 627itb=system.cpu1.itb 628max_insts_all_threads=0 629max_insts_any_thread=0 630max_loads_all_threads=0 631max_loads_any_thread=0 632needsTSO=false 633numIQEntries=64 634numPhysCCRegs=0 635numPhysFloatRegs=256 636numPhysIntRegs=256 637numROBEntries=192 638numRobs=1 639numThreads=1 640profile=0 641progress_interval=0 642renameToDecodeDelay=1 643renameToFetchDelay=1 644renameToIEWDelay=2 645renameToROBDelay=1 646renameWidth=8 647simpoint_start_insts= 648smtCommitPolicy=RoundRobin 649smtFetchPolicy=SingleThread 650smtIQPolicy=Partitioned 651smtIQThreshold=100 652smtLSQPolicy=Partitioned 653smtLSQThreshold=100 654smtNumFetchingThreads=1 655smtROBPolicy=Partitioned 656smtROBThreshold=100 657socket_id=0 658squashWidth=8 659store_set_clear_period=250000 660switched_out=false 661system=system 662tracer=system.cpu1.tracer 663trapLatency=13 664wbWidth=8 665workload=system.cpu0.workload 666dcache_port=system.cpu1.dcache.cpu_side 667icache_port=system.cpu1.icache.cpu_side 668 669[system.cpu1.branchPred] 670type=TournamentBP 671BTBEntries=4096 672BTBTagSize=16 673RASSize=16 674choiceCtrBits=2 675choicePredictorSize=8192 676eventq_index=0 677globalCtrBits=2 678globalPredictorSize=8192 679instShiftAmt=2 680localCtrBits=2 681localHistoryTableSize=2048 682localPredictorSize=2048 683numThreads=1 684 685[system.cpu1.dcache] 686type=Cache 687children=tags 688addr_ranges=0:18446744073709551615 689assoc=4 690clk_domain=system.cpu_clk_domain 691clusivity=mostly_incl 692demand_mshr_reserve=1 693eventq_index=0 694forward_snoops=true 695hit_latency=2 696is_read_only=false 697max_miss_count=0 698mshrs=4 699prefetch_on_access=false 700prefetcher=Null 701response_latency=2 702sequential_access=false 703size=32768 704system=system 705tags=system.cpu1.dcache.tags 706tgts_per_mshr=20 707write_buffers=8 708writeback_clean=false 709cpu_side=system.cpu1.dcache_port 710mem_side=system.toL2Bus.slave[3] 711 712[system.cpu1.dcache.tags] 713type=LRU 714assoc=4 715block_size=64 716clk_domain=system.cpu_clk_domain 717eventq_index=0 718hit_latency=2 719sequential_access=false 720size=32768 721 722[system.cpu1.dtb] 723type=SparcTLB 724eventq_index=0 725size=64 726 727[system.cpu1.fuPool] 728type=FUPool 729children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 730FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 731eventq_index=0 732 733[system.cpu1.fuPool.FUList0] 734type=FUDesc 735children=opList 736count=6 737eventq_index=0 738opList=system.cpu1.fuPool.FUList0.opList 739 740[system.cpu1.fuPool.FUList0.opList] 741type=OpDesc 742eventq_index=0 743opClass=IntAlu 744opLat=1 745pipelined=true 746 747[system.cpu1.fuPool.FUList1] 748type=FUDesc 749children=opList0 opList1 750count=2 751eventq_index=0 752opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 753 754[system.cpu1.fuPool.FUList1.opList0] 755type=OpDesc 756eventq_index=0 757opClass=IntMult 758opLat=3 759pipelined=true 760 761[system.cpu1.fuPool.FUList1.opList1] 762type=OpDesc 763eventq_index=0 764opClass=IntDiv 765opLat=20 766pipelined=false 767 768[system.cpu1.fuPool.FUList2] 769type=FUDesc 770children=opList0 opList1 opList2 771count=4 772eventq_index=0 773opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 774 775[system.cpu1.fuPool.FUList2.opList0] 776type=OpDesc 777eventq_index=0 778opClass=FloatAdd 779opLat=2 780pipelined=true 781 782[system.cpu1.fuPool.FUList2.opList1] 783type=OpDesc 784eventq_index=0 785opClass=FloatCmp 786opLat=2 787pipelined=true 788 789[system.cpu1.fuPool.FUList2.opList2] 790type=OpDesc 791eventq_index=0 792opClass=FloatCvt 793opLat=2 794pipelined=true 795 796[system.cpu1.fuPool.FUList3] 797type=FUDesc 798children=opList0 opList1 opList2 799count=2 800eventq_index=0 801opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 802 803[system.cpu1.fuPool.FUList3.opList0] 804type=OpDesc 805eventq_index=0 806opClass=FloatMult 807opLat=4 808pipelined=true 809 810[system.cpu1.fuPool.FUList3.opList1] 811type=OpDesc 812eventq_index=0 813opClass=FloatDiv 814opLat=12 815pipelined=false 816 817[system.cpu1.fuPool.FUList3.opList2] 818type=OpDesc 819eventq_index=0 820opClass=FloatSqrt 821opLat=24 822pipelined=false 823 824[system.cpu1.fuPool.FUList4] 825type=FUDesc 826children=opList 827count=0 828eventq_index=0 829opList=system.cpu1.fuPool.FUList4.opList 830 831[system.cpu1.fuPool.FUList4.opList] 832type=OpDesc 833eventq_index=0 834opClass=MemRead 835opLat=1 836pipelined=true 837 838[system.cpu1.fuPool.FUList5] 839type=FUDesc 840children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 841count=4 842eventq_index=0 843opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 844 845[system.cpu1.fuPool.FUList5.opList00] 846type=OpDesc 847eventq_index=0 848opClass=SimdAdd 849opLat=1 850pipelined=true 851 852[system.cpu1.fuPool.FUList5.opList01] 853type=OpDesc 854eventq_index=0 855opClass=SimdAddAcc 856opLat=1 857pipelined=true 858 859[system.cpu1.fuPool.FUList5.opList02] 860type=OpDesc 861eventq_index=0 862opClass=SimdAlu 863opLat=1 864pipelined=true 865 866[system.cpu1.fuPool.FUList5.opList03] 867type=OpDesc 868eventq_index=0 869opClass=SimdCmp 870opLat=1 871pipelined=true 872 873[system.cpu1.fuPool.FUList5.opList04] 874type=OpDesc 875eventq_index=0 876opClass=SimdCvt 877opLat=1 878pipelined=true 879 880[system.cpu1.fuPool.FUList5.opList05] 881type=OpDesc 882eventq_index=0 883opClass=SimdMisc 884opLat=1 885pipelined=true 886 887[system.cpu1.fuPool.FUList5.opList06] 888type=OpDesc 889eventq_index=0 890opClass=SimdMult 891opLat=1 892pipelined=true 893 894[system.cpu1.fuPool.FUList5.opList07] 895type=OpDesc 896eventq_index=0 897opClass=SimdMultAcc 898opLat=1 899pipelined=true 900 901[system.cpu1.fuPool.FUList5.opList08] 902type=OpDesc 903eventq_index=0 904opClass=SimdShift 905opLat=1 906pipelined=true 907 908[system.cpu1.fuPool.FUList5.opList09] 909type=OpDesc 910eventq_index=0 911opClass=SimdShiftAcc 912opLat=1 913pipelined=true 914 915[system.cpu1.fuPool.FUList5.opList10] 916type=OpDesc 917eventq_index=0 918opClass=SimdSqrt 919opLat=1 920pipelined=true 921 922[system.cpu1.fuPool.FUList5.opList11] 923type=OpDesc 924eventq_index=0 925opClass=SimdFloatAdd 926opLat=1 927pipelined=true 928 929[system.cpu1.fuPool.FUList5.opList12] 930type=OpDesc 931eventq_index=0 932opClass=SimdFloatAlu 933opLat=1 934pipelined=true 935 936[system.cpu1.fuPool.FUList5.opList13] 937type=OpDesc 938eventq_index=0 939opClass=SimdFloatCmp 940opLat=1 941pipelined=true 942 943[system.cpu1.fuPool.FUList5.opList14] 944type=OpDesc 945eventq_index=0 946opClass=SimdFloatCvt 947opLat=1 948pipelined=true 949 950[system.cpu1.fuPool.FUList5.opList15] 951type=OpDesc 952eventq_index=0 953opClass=SimdFloatDiv 954opLat=1 955pipelined=true 956 957[system.cpu1.fuPool.FUList5.opList16] 958type=OpDesc 959eventq_index=0 960opClass=SimdFloatMisc 961opLat=1 962pipelined=true 963 964[system.cpu1.fuPool.FUList5.opList17] 965type=OpDesc 966eventq_index=0 967opClass=SimdFloatMult 968opLat=1 969pipelined=true 970 971[system.cpu1.fuPool.FUList5.opList18] 972type=OpDesc 973eventq_index=0 974opClass=SimdFloatMultAcc 975opLat=1 976pipelined=true 977 978[system.cpu1.fuPool.FUList5.opList19] 979type=OpDesc 980eventq_index=0 981opClass=SimdFloatSqrt 982opLat=1 983pipelined=true 984 985[system.cpu1.fuPool.FUList6] 986type=FUDesc 987children=opList 988count=0 989eventq_index=0 990opList=system.cpu1.fuPool.FUList6.opList 991 992[system.cpu1.fuPool.FUList6.opList] 993type=OpDesc 994eventq_index=0 995opClass=MemWrite 996opLat=1 997pipelined=true 998 999[system.cpu1.fuPool.FUList7] 1000type=FUDesc 1001children=opList0 opList1 1002count=4 1003eventq_index=0 1004opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 1005 1006[system.cpu1.fuPool.FUList7.opList0] 1007type=OpDesc 1008eventq_index=0 1009opClass=MemRead 1010opLat=1 1011pipelined=true 1012 1013[system.cpu1.fuPool.FUList7.opList1] 1014type=OpDesc 1015eventq_index=0 1016opClass=MemWrite 1017opLat=1 1018pipelined=true 1019 1020[system.cpu1.fuPool.FUList8] 1021type=FUDesc 1022children=opList 1023count=1 1024eventq_index=0 1025opList=system.cpu1.fuPool.FUList8.opList 1026 1027[system.cpu1.fuPool.FUList8.opList] 1028type=OpDesc 1029eventq_index=0 1030opClass=IprAccess 1031opLat=3 1032pipelined=false 1033 1034[system.cpu1.icache] 1035type=Cache 1036children=tags 1037addr_ranges=0:18446744073709551615 1038assoc=1 1039clk_domain=system.cpu_clk_domain 1040clusivity=mostly_incl 1041demand_mshr_reserve=1 1042eventq_index=0 1043forward_snoops=true 1044hit_latency=2 1045is_read_only=true 1046max_miss_count=0 1047mshrs=4 1048prefetch_on_access=false 1049prefetcher=Null 1050response_latency=2 1051sequential_access=false 1052size=32768 1053system=system 1054tags=system.cpu1.icache.tags 1055tgts_per_mshr=20 1056write_buffers=8 1057writeback_clean=true 1058cpu_side=system.cpu1.icache_port 1059mem_side=system.toL2Bus.slave[2] 1060 1061[system.cpu1.icache.tags] 1062type=LRU 1063assoc=1 1064block_size=64 1065clk_domain=system.cpu_clk_domain 1066eventq_index=0 1067hit_latency=2 1068sequential_access=false 1069size=32768 1070 1071[system.cpu1.interrupts] 1072type=SparcInterrupts 1073eventq_index=0 1074 1075[system.cpu1.isa] 1076type=SparcISA 1077eventq_index=0 1078 1079[system.cpu1.itb] 1080type=SparcTLB 1081eventq_index=0 1082size=64 1083 1084[system.cpu1.tracer] 1085type=ExeTracer 1086eventq_index=0 1087 1088[system.cpu2] 1089type=DerivO3CPU 1090children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1091LFSTSize=1024 1092LQEntries=32 1093LSQCheckLoads=true 1094LSQDepCheckShift=4 1095SQEntries=32 1096SSITSize=1024 1097activity=0 1098backComSize=5 1099branchPred=system.cpu2.branchPred 1100cachePorts=200 1101checker=Null 1102clk_domain=system.cpu_clk_domain 1103commitToDecodeDelay=1 1104commitToFetchDelay=1 1105commitToIEWDelay=1 1106commitToRenameDelay=1 1107commitWidth=8 1108cpu_id=2 1109decodeToFetchDelay=1 1110decodeToRenameDelay=1 1111decodeWidth=8 1112dispatchWidth=8 1113do_checkpoint_insts=true 1114do_quiesce=true 1115do_statistics_insts=true 1116dtb=system.cpu2.dtb 1117eventq_index=0 1118fetchBufferSize=64 1119fetchQueueSize=32 1120fetchToDecodeDelay=1 1121fetchTrapLatency=1 1122fetchWidth=8 1123forwardComSize=5 1124fuPool=system.cpu2.fuPool 1125function_trace=false 1126function_trace_start=0 1127iewToCommitDelay=1 1128iewToDecodeDelay=1 1129iewToFetchDelay=1 1130iewToRenameDelay=1 1131interrupts=system.cpu2.interrupts 1132isa=system.cpu2.isa 1133issueToExecuteDelay=1 1134issueWidth=8 1135itb=system.cpu2.itb 1136max_insts_all_threads=0 1137max_insts_any_thread=0 1138max_loads_all_threads=0 1139max_loads_any_thread=0 1140needsTSO=false 1141numIQEntries=64 1142numPhysCCRegs=0 1143numPhysFloatRegs=256 1144numPhysIntRegs=256 1145numROBEntries=192 1146numRobs=1 1147numThreads=1 1148profile=0 1149progress_interval=0 1150renameToDecodeDelay=1 1151renameToFetchDelay=1 1152renameToIEWDelay=2 1153renameToROBDelay=1 1154renameWidth=8 1155simpoint_start_insts= 1156smtCommitPolicy=RoundRobin 1157smtFetchPolicy=SingleThread 1158smtIQPolicy=Partitioned 1159smtIQThreshold=100 1160smtLSQPolicy=Partitioned 1161smtLSQThreshold=100 1162smtNumFetchingThreads=1 1163smtROBPolicy=Partitioned 1164smtROBThreshold=100 1165socket_id=0 1166squashWidth=8 1167store_set_clear_period=250000 1168switched_out=false 1169system=system 1170tracer=system.cpu2.tracer 1171trapLatency=13 1172wbWidth=8 1173workload=system.cpu0.workload 1174dcache_port=system.cpu2.dcache.cpu_side 1175icache_port=system.cpu2.icache.cpu_side 1176 1177[system.cpu2.branchPred] 1178type=TournamentBP 1179BTBEntries=4096 1180BTBTagSize=16 1181RASSize=16 1182choiceCtrBits=2 1183choicePredictorSize=8192 1184eventq_index=0 1185globalCtrBits=2 1186globalPredictorSize=8192 1187instShiftAmt=2 1188localCtrBits=2 1189localHistoryTableSize=2048 1190localPredictorSize=2048 1191numThreads=1 1192 1193[system.cpu2.dcache] 1194type=Cache 1195children=tags 1196addr_ranges=0:18446744073709551615 1197assoc=4 1198clk_domain=system.cpu_clk_domain 1199clusivity=mostly_incl 1200demand_mshr_reserve=1 1201eventq_index=0 1202forward_snoops=true 1203hit_latency=2 1204is_read_only=false 1205max_miss_count=0 1206mshrs=4 1207prefetch_on_access=false 1208prefetcher=Null 1209response_latency=2 1210sequential_access=false 1211size=32768 1212system=system 1213tags=system.cpu2.dcache.tags 1214tgts_per_mshr=20 1215write_buffers=8 1216writeback_clean=false 1217cpu_side=system.cpu2.dcache_port 1218mem_side=system.toL2Bus.slave[5] 1219 1220[system.cpu2.dcache.tags] 1221type=LRU 1222assoc=4 1223block_size=64 1224clk_domain=system.cpu_clk_domain 1225eventq_index=0 1226hit_latency=2 1227sequential_access=false 1228size=32768 1229 1230[system.cpu2.dtb] 1231type=SparcTLB 1232eventq_index=0 1233size=64 1234 1235[system.cpu2.fuPool] 1236type=FUPool 1237children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1238FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1239eventq_index=0 1240 1241[system.cpu2.fuPool.FUList0] 1242type=FUDesc 1243children=opList 1244count=6 1245eventq_index=0 1246opList=system.cpu2.fuPool.FUList0.opList 1247 1248[system.cpu2.fuPool.FUList0.opList] 1249type=OpDesc 1250eventq_index=0 1251opClass=IntAlu 1252opLat=1 1253pipelined=true 1254 1255[system.cpu2.fuPool.FUList1] 1256type=FUDesc 1257children=opList0 opList1 1258count=2 1259eventq_index=0 1260opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1261 1262[system.cpu2.fuPool.FUList1.opList0] 1263type=OpDesc 1264eventq_index=0 1265opClass=IntMult 1266opLat=3 1267pipelined=true 1268 1269[system.cpu2.fuPool.FUList1.opList1] 1270type=OpDesc 1271eventq_index=0 1272opClass=IntDiv 1273opLat=20 1274pipelined=false 1275 1276[system.cpu2.fuPool.FUList2] 1277type=FUDesc 1278children=opList0 opList1 opList2 1279count=4 1280eventq_index=0 1281opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1282 1283[system.cpu2.fuPool.FUList2.opList0] 1284type=OpDesc 1285eventq_index=0 1286opClass=FloatAdd 1287opLat=2 1288pipelined=true 1289 1290[system.cpu2.fuPool.FUList2.opList1] 1291type=OpDesc 1292eventq_index=0 1293opClass=FloatCmp 1294opLat=2 1295pipelined=true 1296 1297[system.cpu2.fuPool.FUList2.opList2] 1298type=OpDesc 1299eventq_index=0 1300opClass=FloatCvt 1301opLat=2 1302pipelined=true 1303 1304[system.cpu2.fuPool.FUList3] 1305type=FUDesc 1306children=opList0 opList1 opList2 1307count=2 1308eventq_index=0 1309opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1310 1311[system.cpu2.fuPool.FUList3.opList0] 1312type=OpDesc 1313eventq_index=0 1314opClass=FloatMult 1315opLat=4 1316pipelined=true 1317 1318[system.cpu2.fuPool.FUList3.opList1] 1319type=OpDesc 1320eventq_index=0 1321opClass=FloatDiv 1322opLat=12 1323pipelined=false 1324 1325[system.cpu2.fuPool.FUList3.opList2] 1326type=OpDesc 1327eventq_index=0 1328opClass=FloatSqrt 1329opLat=24 1330pipelined=false 1331 1332[system.cpu2.fuPool.FUList4] 1333type=FUDesc 1334children=opList 1335count=0 1336eventq_index=0 1337opList=system.cpu2.fuPool.FUList4.opList 1338 1339[system.cpu2.fuPool.FUList4.opList] 1340type=OpDesc 1341eventq_index=0 1342opClass=MemRead 1343opLat=1 1344pipelined=true 1345 1346[system.cpu2.fuPool.FUList5] 1347type=FUDesc 1348children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1349count=4 1350eventq_index=0 1351opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1352 1353[system.cpu2.fuPool.FUList5.opList00] 1354type=OpDesc 1355eventq_index=0 1356opClass=SimdAdd 1357opLat=1 1358pipelined=true 1359 1360[system.cpu2.fuPool.FUList5.opList01] 1361type=OpDesc 1362eventq_index=0 1363opClass=SimdAddAcc 1364opLat=1 1365pipelined=true 1366 1367[system.cpu2.fuPool.FUList5.opList02] 1368type=OpDesc 1369eventq_index=0 1370opClass=SimdAlu 1371opLat=1 1372pipelined=true 1373 1374[system.cpu2.fuPool.FUList5.opList03] 1375type=OpDesc 1376eventq_index=0 1377opClass=SimdCmp 1378opLat=1 1379pipelined=true 1380 1381[system.cpu2.fuPool.FUList5.opList04] 1382type=OpDesc 1383eventq_index=0 1384opClass=SimdCvt 1385opLat=1 1386pipelined=true 1387 1388[system.cpu2.fuPool.FUList5.opList05] 1389type=OpDesc 1390eventq_index=0 1391opClass=SimdMisc 1392opLat=1 1393pipelined=true 1394 1395[system.cpu2.fuPool.FUList5.opList06] 1396type=OpDesc 1397eventq_index=0 1398opClass=SimdMult 1399opLat=1 1400pipelined=true 1401 1402[system.cpu2.fuPool.FUList5.opList07] 1403type=OpDesc 1404eventq_index=0 1405opClass=SimdMultAcc 1406opLat=1 1407pipelined=true 1408 1409[system.cpu2.fuPool.FUList5.opList08] 1410type=OpDesc 1411eventq_index=0 1412opClass=SimdShift 1413opLat=1 1414pipelined=true 1415 1416[system.cpu2.fuPool.FUList5.opList09] 1417type=OpDesc 1418eventq_index=0 1419opClass=SimdShiftAcc 1420opLat=1 1421pipelined=true 1422 1423[system.cpu2.fuPool.FUList5.opList10] 1424type=OpDesc 1425eventq_index=0 1426opClass=SimdSqrt 1427opLat=1 1428pipelined=true 1429 1430[system.cpu2.fuPool.FUList5.opList11] 1431type=OpDesc 1432eventq_index=0 1433opClass=SimdFloatAdd 1434opLat=1 1435pipelined=true 1436 1437[system.cpu2.fuPool.FUList5.opList12] 1438type=OpDesc 1439eventq_index=0 1440opClass=SimdFloatAlu 1441opLat=1 1442pipelined=true 1443 1444[system.cpu2.fuPool.FUList5.opList13] 1445type=OpDesc 1446eventq_index=0 1447opClass=SimdFloatCmp 1448opLat=1 1449pipelined=true 1450 1451[system.cpu2.fuPool.FUList5.opList14] 1452type=OpDesc 1453eventq_index=0 1454opClass=SimdFloatCvt 1455opLat=1 1456pipelined=true 1457 1458[system.cpu2.fuPool.FUList5.opList15] 1459type=OpDesc 1460eventq_index=0 1461opClass=SimdFloatDiv 1462opLat=1 1463pipelined=true 1464 1465[system.cpu2.fuPool.FUList5.opList16] 1466type=OpDesc 1467eventq_index=0 1468opClass=SimdFloatMisc 1469opLat=1 1470pipelined=true 1471 1472[system.cpu2.fuPool.FUList5.opList17] 1473type=OpDesc 1474eventq_index=0 1475opClass=SimdFloatMult 1476opLat=1 1477pipelined=true 1478 1479[system.cpu2.fuPool.FUList5.opList18] 1480type=OpDesc 1481eventq_index=0 1482opClass=SimdFloatMultAcc 1483opLat=1 1484pipelined=true 1485 1486[system.cpu2.fuPool.FUList5.opList19] 1487type=OpDesc 1488eventq_index=0 1489opClass=SimdFloatSqrt 1490opLat=1 1491pipelined=true 1492 1493[system.cpu2.fuPool.FUList6] 1494type=FUDesc 1495children=opList 1496count=0 1497eventq_index=0 1498opList=system.cpu2.fuPool.FUList6.opList 1499 1500[system.cpu2.fuPool.FUList6.opList] 1501type=OpDesc 1502eventq_index=0 1503opClass=MemWrite 1504opLat=1 1505pipelined=true 1506 1507[system.cpu2.fuPool.FUList7] 1508type=FUDesc 1509children=opList0 opList1 1510count=4 1511eventq_index=0 1512opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1513 1514[system.cpu2.fuPool.FUList7.opList0] 1515type=OpDesc 1516eventq_index=0 1517opClass=MemRead 1518opLat=1 1519pipelined=true 1520 1521[system.cpu2.fuPool.FUList7.opList1] 1522type=OpDesc 1523eventq_index=0 1524opClass=MemWrite 1525opLat=1 1526pipelined=true 1527 1528[system.cpu2.fuPool.FUList8] 1529type=FUDesc 1530children=opList 1531count=1 1532eventq_index=0 1533opList=system.cpu2.fuPool.FUList8.opList 1534 1535[system.cpu2.fuPool.FUList8.opList] 1536type=OpDesc 1537eventq_index=0 1538opClass=IprAccess 1539opLat=3 1540pipelined=false 1541 1542[system.cpu2.icache] 1543type=Cache 1544children=tags 1545addr_ranges=0:18446744073709551615 1546assoc=1 1547clk_domain=system.cpu_clk_domain 1548clusivity=mostly_incl 1549demand_mshr_reserve=1 1550eventq_index=0 1551forward_snoops=true 1552hit_latency=2 1553is_read_only=true 1554max_miss_count=0 1555mshrs=4 1556prefetch_on_access=false 1557prefetcher=Null 1558response_latency=2 1559sequential_access=false 1560size=32768 1561system=system 1562tags=system.cpu2.icache.tags 1563tgts_per_mshr=20 1564write_buffers=8 1565writeback_clean=true 1566cpu_side=system.cpu2.icache_port 1567mem_side=system.toL2Bus.slave[4] 1568 1569[system.cpu2.icache.tags] 1570type=LRU 1571assoc=1 1572block_size=64 1573clk_domain=system.cpu_clk_domain 1574eventq_index=0 1575hit_latency=2 1576sequential_access=false 1577size=32768 1578 1579[system.cpu2.interrupts] 1580type=SparcInterrupts 1581eventq_index=0 1582 1583[system.cpu2.isa] 1584type=SparcISA 1585eventq_index=0 1586 1587[system.cpu2.itb] 1588type=SparcTLB 1589eventq_index=0 1590size=64 1591 1592[system.cpu2.tracer] 1593type=ExeTracer 1594eventq_index=0 1595 1596[system.cpu3] 1597type=DerivO3CPU 1598children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1599LFSTSize=1024 1600LQEntries=32 1601LSQCheckLoads=true 1602LSQDepCheckShift=4 1603SQEntries=32 1604SSITSize=1024 1605activity=0 1606backComSize=5 1607branchPred=system.cpu3.branchPred 1608cachePorts=200 1609checker=Null 1610clk_domain=system.cpu_clk_domain 1611commitToDecodeDelay=1 1612commitToFetchDelay=1 1613commitToIEWDelay=1 1614commitToRenameDelay=1 1615commitWidth=8 1616cpu_id=3 1617decodeToFetchDelay=1 1618decodeToRenameDelay=1 1619decodeWidth=8 1620dispatchWidth=8 1621do_checkpoint_insts=true 1622do_quiesce=true 1623do_statistics_insts=true 1624dtb=system.cpu3.dtb 1625eventq_index=0 1626fetchBufferSize=64 1627fetchQueueSize=32 1628fetchToDecodeDelay=1 1629fetchTrapLatency=1 1630fetchWidth=8 1631forwardComSize=5 1632fuPool=system.cpu3.fuPool 1633function_trace=false 1634function_trace_start=0 1635iewToCommitDelay=1 1636iewToDecodeDelay=1 1637iewToFetchDelay=1 1638iewToRenameDelay=1 1639interrupts=system.cpu3.interrupts 1640isa=system.cpu3.isa 1641issueToExecuteDelay=1 1642issueWidth=8 1643itb=system.cpu3.itb 1644max_insts_all_threads=0 1645max_insts_any_thread=0 1646max_loads_all_threads=0 1647max_loads_any_thread=0 1648needsTSO=false 1649numIQEntries=64 1650numPhysCCRegs=0 1651numPhysFloatRegs=256 1652numPhysIntRegs=256 1653numROBEntries=192 1654numRobs=1 1655numThreads=1 1656profile=0 1657progress_interval=0 1658renameToDecodeDelay=1 1659renameToFetchDelay=1 1660renameToIEWDelay=2 1661renameToROBDelay=1 1662renameWidth=8 1663simpoint_start_insts= 1664smtCommitPolicy=RoundRobin 1665smtFetchPolicy=SingleThread 1666smtIQPolicy=Partitioned 1667smtIQThreshold=100 1668smtLSQPolicy=Partitioned 1669smtLSQThreshold=100 1670smtNumFetchingThreads=1 1671smtROBPolicy=Partitioned 1672smtROBThreshold=100 1673socket_id=0 1674squashWidth=8 1675store_set_clear_period=250000 1676switched_out=false 1677system=system 1678tracer=system.cpu3.tracer 1679trapLatency=13 1680wbWidth=8 1681workload=system.cpu0.workload 1682dcache_port=system.cpu3.dcache.cpu_side 1683icache_port=system.cpu3.icache.cpu_side 1684 1685[system.cpu3.branchPred] 1686type=TournamentBP 1687BTBEntries=4096 1688BTBTagSize=16 1689RASSize=16 1690choiceCtrBits=2 1691choicePredictorSize=8192 1692eventq_index=0 1693globalCtrBits=2 1694globalPredictorSize=8192 1695instShiftAmt=2 1696localCtrBits=2 1697localHistoryTableSize=2048 1698localPredictorSize=2048 1699numThreads=1 1700 1701[system.cpu3.dcache] 1702type=Cache 1703children=tags 1704addr_ranges=0:18446744073709551615 1705assoc=4 1706clk_domain=system.cpu_clk_domain 1707clusivity=mostly_incl 1708demand_mshr_reserve=1 1709eventq_index=0 1710forward_snoops=true 1711hit_latency=2 1712is_read_only=false 1713max_miss_count=0 1714mshrs=4 1715prefetch_on_access=false 1716prefetcher=Null 1717response_latency=2 1718sequential_access=false 1719size=32768 1720system=system 1721tags=system.cpu3.dcache.tags 1722tgts_per_mshr=20 1723write_buffers=8 1724writeback_clean=false 1725cpu_side=system.cpu3.dcache_port 1726mem_side=system.toL2Bus.slave[7] 1727 1728[system.cpu3.dcache.tags] 1729type=LRU 1730assoc=4 1731block_size=64 1732clk_domain=system.cpu_clk_domain 1733eventq_index=0 1734hit_latency=2 1735sequential_access=false 1736size=32768 1737 1738[system.cpu3.dtb] 1739type=SparcTLB 1740eventq_index=0 1741size=64 1742 1743[system.cpu3.fuPool] 1744type=FUPool 1745children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1746FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1747eventq_index=0 1748 1749[system.cpu3.fuPool.FUList0] 1750type=FUDesc 1751children=opList 1752count=6 1753eventq_index=0 1754opList=system.cpu3.fuPool.FUList0.opList 1755 1756[system.cpu3.fuPool.FUList0.opList] 1757type=OpDesc 1758eventq_index=0 1759opClass=IntAlu 1760opLat=1 1761pipelined=true 1762 1763[system.cpu3.fuPool.FUList1] 1764type=FUDesc 1765children=opList0 opList1 1766count=2 1767eventq_index=0 1768opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1769 1770[system.cpu3.fuPool.FUList1.opList0] 1771type=OpDesc 1772eventq_index=0 1773opClass=IntMult 1774opLat=3 1775pipelined=true 1776 1777[system.cpu3.fuPool.FUList1.opList1] 1778type=OpDesc 1779eventq_index=0 1780opClass=IntDiv 1781opLat=20 1782pipelined=false 1783 1784[system.cpu3.fuPool.FUList2] 1785type=FUDesc 1786children=opList0 opList1 opList2 1787count=4 1788eventq_index=0 1789opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1790 1791[system.cpu3.fuPool.FUList2.opList0] 1792type=OpDesc 1793eventq_index=0 1794opClass=FloatAdd 1795opLat=2 1796pipelined=true 1797 1798[system.cpu3.fuPool.FUList2.opList1] 1799type=OpDesc 1800eventq_index=0 1801opClass=FloatCmp 1802opLat=2 1803pipelined=true 1804 1805[system.cpu3.fuPool.FUList2.opList2] 1806type=OpDesc 1807eventq_index=0 1808opClass=FloatCvt 1809opLat=2 1810pipelined=true 1811 1812[system.cpu3.fuPool.FUList3] 1813type=FUDesc 1814children=opList0 opList1 opList2 1815count=2 1816eventq_index=0 1817opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1818 1819[system.cpu3.fuPool.FUList3.opList0] 1820type=OpDesc 1821eventq_index=0 1822opClass=FloatMult 1823opLat=4 1824pipelined=true 1825 1826[system.cpu3.fuPool.FUList3.opList1] 1827type=OpDesc 1828eventq_index=0 1829opClass=FloatDiv 1830opLat=12 1831pipelined=false 1832 1833[system.cpu3.fuPool.FUList3.opList2] 1834type=OpDesc 1835eventq_index=0 1836opClass=FloatSqrt 1837opLat=24 1838pipelined=false 1839 1840[system.cpu3.fuPool.FUList4] 1841type=FUDesc 1842children=opList 1843count=0 1844eventq_index=0 1845opList=system.cpu3.fuPool.FUList4.opList 1846 1847[system.cpu3.fuPool.FUList4.opList] 1848type=OpDesc 1849eventq_index=0 1850opClass=MemRead 1851opLat=1 1852pipelined=true 1853 1854[system.cpu3.fuPool.FUList5] 1855type=FUDesc 1856children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1857count=4 1858eventq_index=0 1859opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1860 1861[system.cpu3.fuPool.FUList5.opList00] 1862type=OpDesc 1863eventq_index=0 1864opClass=SimdAdd 1865opLat=1 1866pipelined=true 1867 1868[system.cpu3.fuPool.FUList5.opList01] 1869type=OpDesc 1870eventq_index=0 1871opClass=SimdAddAcc 1872opLat=1 1873pipelined=true 1874 1875[system.cpu3.fuPool.FUList5.opList02] 1876type=OpDesc 1877eventq_index=0 1878opClass=SimdAlu 1879opLat=1 1880pipelined=true 1881 1882[system.cpu3.fuPool.FUList5.opList03] 1883type=OpDesc 1884eventq_index=0 1885opClass=SimdCmp 1886opLat=1 1887pipelined=true 1888 1889[system.cpu3.fuPool.FUList5.opList04] 1890type=OpDesc 1891eventq_index=0 1892opClass=SimdCvt 1893opLat=1 1894pipelined=true 1895 1896[system.cpu3.fuPool.FUList5.opList05] 1897type=OpDesc 1898eventq_index=0 1899opClass=SimdMisc 1900opLat=1 1901pipelined=true 1902 1903[system.cpu3.fuPool.FUList5.opList06] 1904type=OpDesc 1905eventq_index=0 1906opClass=SimdMult 1907opLat=1 1908pipelined=true 1909 1910[system.cpu3.fuPool.FUList5.opList07] 1911type=OpDesc 1912eventq_index=0 1913opClass=SimdMultAcc 1914opLat=1 1915pipelined=true 1916 1917[system.cpu3.fuPool.FUList5.opList08] 1918type=OpDesc 1919eventq_index=0 1920opClass=SimdShift 1921opLat=1 1922pipelined=true 1923 1924[system.cpu3.fuPool.FUList5.opList09] 1925type=OpDesc 1926eventq_index=0 1927opClass=SimdShiftAcc 1928opLat=1 1929pipelined=true 1930 1931[system.cpu3.fuPool.FUList5.opList10] 1932type=OpDesc 1933eventq_index=0 1934opClass=SimdSqrt 1935opLat=1 1936pipelined=true 1937 1938[system.cpu3.fuPool.FUList5.opList11] 1939type=OpDesc 1940eventq_index=0 1941opClass=SimdFloatAdd 1942opLat=1 1943pipelined=true 1944 1945[system.cpu3.fuPool.FUList5.opList12] 1946type=OpDesc 1947eventq_index=0 1948opClass=SimdFloatAlu 1949opLat=1 1950pipelined=true 1951 1952[system.cpu3.fuPool.FUList5.opList13] 1953type=OpDesc 1954eventq_index=0 1955opClass=SimdFloatCmp 1956opLat=1 1957pipelined=true 1958 1959[system.cpu3.fuPool.FUList5.opList14] 1960type=OpDesc 1961eventq_index=0 1962opClass=SimdFloatCvt 1963opLat=1 1964pipelined=true 1965 1966[system.cpu3.fuPool.FUList5.opList15] 1967type=OpDesc 1968eventq_index=0 1969opClass=SimdFloatDiv 1970opLat=1 1971pipelined=true 1972 1973[system.cpu3.fuPool.FUList5.opList16] 1974type=OpDesc 1975eventq_index=0 1976opClass=SimdFloatMisc 1977opLat=1 1978pipelined=true 1979 1980[system.cpu3.fuPool.FUList5.opList17] 1981type=OpDesc 1982eventq_index=0 1983opClass=SimdFloatMult 1984opLat=1 1985pipelined=true 1986 1987[system.cpu3.fuPool.FUList5.opList18] 1988type=OpDesc 1989eventq_index=0 1990opClass=SimdFloatMultAcc 1991opLat=1 1992pipelined=true 1993 1994[system.cpu3.fuPool.FUList5.opList19] 1995type=OpDesc 1996eventq_index=0 1997opClass=SimdFloatSqrt 1998opLat=1 1999pipelined=true 2000 2001[system.cpu3.fuPool.FUList6] 2002type=FUDesc 2003children=opList 2004count=0 2005eventq_index=0 2006opList=system.cpu3.fuPool.FUList6.opList 2007 2008[system.cpu3.fuPool.FUList6.opList] 2009type=OpDesc 2010eventq_index=0 2011opClass=MemWrite 2012opLat=1 2013pipelined=true 2014 2015[system.cpu3.fuPool.FUList7] 2016type=FUDesc 2017children=opList0 opList1 2018count=4 2019eventq_index=0 2020opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 2021 2022[system.cpu3.fuPool.FUList7.opList0] 2023type=OpDesc 2024eventq_index=0 2025opClass=MemRead 2026opLat=1 2027pipelined=true 2028 2029[system.cpu3.fuPool.FUList7.opList1] 2030type=OpDesc 2031eventq_index=0 2032opClass=MemWrite 2033opLat=1 2034pipelined=true 2035 2036[system.cpu3.fuPool.FUList8] 2037type=FUDesc 2038children=opList 2039count=1 2040eventq_index=0 2041opList=system.cpu3.fuPool.FUList8.opList 2042 2043[system.cpu3.fuPool.FUList8.opList] 2044type=OpDesc 2045eventq_index=0 2046opClass=IprAccess 2047opLat=3 2048pipelined=false 2049 2050[system.cpu3.icache] 2051type=Cache 2052children=tags 2053addr_ranges=0:18446744073709551615 2054assoc=1 2055clk_domain=system.cpu_clk_domain 2056clusivity=mostly_incl 2057demand_mshr_reserve=1 2058eventq_index=0 2059forward_snoops=true 2060hit_latency=2 2061is_read_only=true 2062max_miss_count=0 2063mshrs=4 2064prefetch_on_access=false 2065prefetcher=Null 2066response_latency=2 2067sequential_access=false 2068size=32768 2069system=system 2070tags=system.cpu3.icache.tags 2071tgts_per_mshr=20 2072write_buffers=8 2073writeback_clean=true 2074cpu_side=system.cpu3.icache_port 2075mem_side=system.toL2Bus.slave[6] 2076 2077[system.cpu3.icache.tags] 2078type=LRU 2079assoc=1 2080block_size=64 2081clk_domain=system.cpu_clk_domain 2082eventq_index=0 2083hit_latency=2 2084sequential_access=false 2085size=32768 2086 2087[system.cpu3.interrupts] 2088type=SparcInterrupts 2089eventq_index=0 2090 2091[system.cpu3.isa] 2092type=SparcISA 2093eventq_index=0 2094 2095[system.cpu3.itb] 2096type=SparcTLB 2097eventq_index=0 2098size=64 2099 2100[system.cpu3.tracer] 2101type=ExeTracer 2102eventq_index=0 2103 2104[system.cpu_clk_domain] 2105type=SrcClockDomain 2106clock=500 2107domain_id=-1 2108eventq_index=0 2109init_perf_level=0 2110voltage_domain=system.voltage_domain 2111 2112[system.dvfs_handler] 2113type=DVFSHandler 2114domains= 2115enable=false 2116eventq_index=0 2117sys_clk_domain=system.clk_domain 2118transition_latency=100000000 2119 2120[system.l2c] 2121type=Cache 2122children=tags 2123addr_ranges=0:18446744073709551615 2124assoc=8 2125clk_domain=system.cpu_clk_domain 2126clusivity=mostly_incl 2127demand_mshr_reserve=1 2128eventq_index=0 2129forward_snoops=true 2130hit_latency=20 2131is_read_only=false 2132max_miss_count=0 2133mshrs=20 2134prefetch_on_access=false 2135prefetcher=Null 2136response_latency=20 2137sequential_access=false 2138size=4194304 2139system=system 2140tags=system.l2c.tags 2141tgts_per_mshr=12 2142write_buffers=8 2143writeback_clean=false 2144cpu_side=system.toL2Bus.master[0] 2145mem_side=system.membus.slave[1] 2146 2147[system.l2c.tags] 2148type=LRU 2149assoc=8 2150block_size=64 2151clk_domain=system.cpu_clk_domain 2152eventq_index=0 2153hit_latency=20 2154sequential_access=false 2155size=4194304 2156 2157[system.membus] 2158type=CoherentXBar 2159clk_domain=system.clk_domain 2160eventq_index=0 2161forward_latency=4 2162frontend_latency=3 2163response_latency=2 2164snoop_filter=Null 2165snoop_response_latency=4 2166system=system 2167use_default_range=false 2168width=16 2169master=system.physmem.port 2170slave=system.system_port system.l2c.mem_side 2171 2172[system.physmem] 2173type=DRAMCtrl 2174IDD0=0.075000 2175IDD02=0.000000 2176IDD2N=0.050000 2177IDD2N2=0.000000 2178IDD2P0=0.000000 2179IDD2P02=0.000000 2180IDD2P1=0.000000 2181IDD2P12=0.000000 2182IDD3N=0.057000 2183IDD3N2=0.000000 2184IDD3P0=0.000000 2185IDD3P02=0.000000 2186IDD3P1=0.000000 2187IDD3P12=0.000000 2188IDD4R=0.187000 2189IDD4R2=0.000000 2190IDD4W=0.165000 2191IDD4W2=0.000000 2192IDD5=0.220000 2193IDD52=0.000000 2194IDD6=0.000000 2195IDD62=0.000000 2196VDD=1.500000 2197VDD2=0.000000 2198activation_limit=4 2199addr_mapping=RoRaBaCoCh 2200bank_groups_per_rank=0 2201banks_per_rank=8 2202burst_length=8 2203channels=1 2204clk_domain=system.clk_domain 2205conf_table_reported=true 2206device_bus_width=8 2207device_rowbuffer_size=1024 2208device_size=536870912 2209devices_per_rank=8 2210dll=true 2211eventq_index=0 2212in_addr_map=true 2213max_accesses_per_row=16 2214mem_sched_policy=frfcfs 2215min_writes_per_switch=16 2216null=false 2217page_policy=open_adaptive 2218range=0:134217727 2219ranks_per_channel=2 2220read_buffer_size=32 2221static_backend_latency=10000 2222static_frontend_latency=10000 2223tBURST=5000 2224tCCD_L=0 2225tCK=1250 2226tCL=13750 2227tCS=2500 2228tRAS=35000 2229tRCD=13750 2230tREFI=7800000 2231tRFC=260000 2232tRP=13750 2233tRRD=6000 2234tRRD_L=0 2235tRTP=7500 2236tRTW=2500 2237tWR=15000 2238tWTR=7500 2239tXAW=30000 2240tXP=0 2241tXPDLL=0 2242tXS=0 2243tXSDLL=0 2244write_buffer_size=64 2245write_high_thresh_perc=85 2246write_low_thresh_perc=50 2247port=system.membus.master[0] 2248 2249[system.toL2Bus] 2250type=CoherentXBar 2251children=snoop_filter 2252clk_domain=system.cpu_clk_domain 2253eventq_index=0 2254forward_latency=0 2255frontend_latency=1 2256response_latency=1 2257snoop_filter=system.toL2Bus.snoop_filter 2258snoop_response_latency=1 2259system=system 2260use_default_range=false 2261width=32 2262master=system.l2c.cpu_side 2263slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2264 2265[system.toL2Bus.snoop_filter] 2266type=SnoopFilter 2267eventq_index=0 2268lookup_latency=0 2269max_capacity=8388608 2270system=system 2271 2272[system.voltage_domain] 2273type=VoltageDomain 2274eventq_index=0 2275voltage=1.000000 2276 2277