config.ini revision 11219
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27multi_thread=false 28num_work_ids=16 29readfile= 30symbolfile= 31work_begin_ckpt_count=0 32work_begin_cpu_id_exit=-1 33work_begin_exit_count=0 34work_cpus_ckpt_count=0 35work_end_ckpt_count=0 36work_end_exit_count=0 37work_item_id=-1 38system_port=system.membus.slave[0] 39 40[system.clk_domain] 41type=SrcClockDomain 42clock=1000 43domain_id=-1 44eventq_index=0 45init_perf_level=0 46voltage_domain=system.voltage_domain 47 48[system.cpu0] 49type=DerivO3CPU 50children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55SQEntries=32 56SSITSize=1024 57activity=0 58backComSize=5 59branchPred=system.cpu0.branchPred 60cachePorts=200 61checker=Null 62clk_domain=system.cpu_clk_domain 63commitToDecodeDelay=1 64commitToFetchDelay=1 65commitToIEWDelay=1 66commitToRenameDelay=1 67commitWidth=8 68cpu_id=0 69decodeToFetchDelay=1 70decodeToRenameDelay=1 71decodeWidth=8 72dispatchWidth=8 73do_checkpoint_insts=true 74do_quiesce=true 75do_statistics_insts=true 76dtb=system.cpu0.dtb 77eventq_index=0 78fetchBufferSize=64 79fetchQueueSize=32 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu0.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu0.interrupts 92isa=system.cpu0.isa 93issueToExecuteDelay=1 94issueWidth=8 95itb=system.cpu0.itb 96max_insts_all_threads=0 97max_insts_any_thread=0 98max_loads_all_threads=0 99max_loads_any_thread=0 100needsTSO=false 101numIQEntries=64 102numPhysCCRegs=0 103numPhysFloatRegs=256 104numPhysIntRegs=256 105numROBEntries=192 106numRobs=1 107numThreads=1 108profile=0 109progress_interval=0 110renameToDecodeDelay=1 111renameToFetchDelay=1 112renameToIEWDelay=2 113renameToROBDelay=1 114renameWidth=8 115simpoint_start_insts= 116smtCommitPolicy=RoundRobin 117smtFetchPolicy=SingleThread 118smtIQPolicy=Partitioned 119smtIQThreshold=100 120smtLSQPolicy=Partitioned 121smtLSQThreshold=100 122smtNumFetchingThreads=1 123smtROBPolicy=Partitioned 124smtROBThreshold=100 125socket_id=0 126squashWidth=8 127store_set_clear_period=250000 128switched_out=false 129system=system 130tracer=system.cpu0.tracer 131trapLatency=13 132wbWidth=8 133workload=system.cpu0.workload 134dcache_port=system.cpu0.dcache.cpu_side 135icache_port=system.cpu0.icache.cpu_side 136 137[system.cpu0.branchPred] 138type=TournamentBP 139BTBEntries=4096 140BTBTagSize=16 141RASSize=16 142choiceCtrBits=2 143choicePredictorSize=8192 144eventq_index=0 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 151numThreads=1 152 153[system.cpu0.dcache] 154type=Cache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=4 158clk_domain=system.cpu_clk_domain 159clusivity=mostly_incl 160demand_mshr_reserve=1 161eventq_index=0 162forward_snoops=true 163hit_latency=2 164is_read_only=false 165max_miss_count=0 166mshrs=4 167prefetch_on_access=false 168prefetcher=Null 169response_latency=2 170sequential_access=false 171size=32768 172system=system 173tags=system.cpu0.dcache.tags 174tgts_per_mshr=20 175write_buffers=8 176writeback_clean=false 177cpu_side=system.cpu0.dcache_port 178mem_side=system.toL2Bus.slave[1] 179 180[system.cpu0.dcache.tags] 181type=LRU 182assoc=4 183block_size=64 184clk_domain=system.cpu_clk_domain 185eventq_index=0 186hit_latency=2 187sequential_access=false 188size=32768 189 190[system.cpu0.dtb] 191type=SparcTLB 192eventq_index=0 193size=64 194 195[system.cpu0.fuPool] 196type=FUPool 197children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 198FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 199eventq_index=0 200 201[system.cpu0.fuPool.FUList0] 202type=FUDesc 203children=opList 204count=6 205eventq_index=0 206opList=system.cpu0.fuPool.FUList0.opList 207 208[system.cpu0.fuPool.FUList0.opList] 209type=OpDesc 210eventq_index=0 211opClass=IntAlu 212opLat=1 213pipelined=true 214 215[system.cpu0.fuPool.FUList1] 216type=FUDesc 217children=opList0 opList1 218count=2 219eventq_index=0 220opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 221 222[system.cpu0.fuPool.FUList1.opList0] 223type=OpDesc 224eventq_index=0 225opClass=IntMult 226opLat=3 227pipelined=true 228 229[system.cpu0.fuPool.FUList1.opList1] 230type=OpDesc 231eventq_index=0 232opClass=IntDiv 233opLat=20 234pipelined=false 235 236[system.cpu0.fuPool.FUList2] 237type=FUDesc 238children=opList0 opList1 opList2 239count=4 240eventq_index=0 241opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 242 243[system.cpu0.fuPool.FUList2.opList0] 244type=OpDesc 245eventq_index=0 246opClass=FloatAdd 247opLat=2 248pipelined=true 249 250[system.cpu0.fuPool.FUList2.opList1] 251type=OpDesc 252eventq_index=0 253opClass=FloatCmp 254opLat=2 255pipelined=true 256 257[system.cpu0.fuPool.FUList2.opList2] 258type=OpDesc 259eventq_index=0 260opClass=FloatCvt 261opLat=2 262pipelined=true 263 264[system.cpu0.fuPool.FUList3] 265type=FUDesc 266children=opList0 opList1 opList2 267count=2 268eventq_index=0 269opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 270 271[system.cpu0.fuPool.FUList3.opList0] 272type=OpDesc 273eventq_index=0 274opClass=FloatMult 275opLat=4 276pipelined=true 277 278[system.cpu0.fuPool.FUList3.opList1] 279type=OpDesc 280eventq_index=0 281opClass=FloatDiv 282opLat=12 283pipelined=false 284 285[system.cpu0.fuPool.FUList3.opList2] 286type=OpDesc 287eventq_index=0 288opClass=FloatSqrt 289opLat=24 290pipelined=false 291 292[system.cpu0.fuPool.FUList4] 293type=FUDesc 294children=opList 295count=0 296eventq_index=0 297opList=system.cpu0.fuPool.FUList4.opList 298 299[system.cpu0.fuPool.FUList4.opList] 300type=OpDesc 301eventq_index=0 302opClass=MemRead 303opLat=1 304pipelined=true 305 306[system.cpu0.fuPool.FUList5] 307type=FUDesc 308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 309count=4 310eventq_index=0 311opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 312 313[system.cpu0.fuPool.FUList5.opList00] 314type=OpDesc 315eventq_index=0 316opClass=SimdAdd 317opLat=1 318pipelined=true 319 320[system.cpu0.fuPool.FUList5.opList01] 321type=OpDesc 322eventq_index=0 323opClass=SimdAddAcc 324opLat=1 325pipelined=true 326 327[system.cpu0.fuPool.FUList5.opList02] 328type=OpDesc 329eventq_index=0 330opClass=SimdAlu 331opLat=1 332pipelined=true 333 334[system.cpu0.fuPool.FUList5.opList03] 335type=OpDesc 336eventq_index=0 337opClass=SimdCmp 338opLat=1 339pipelined=true 340 341[system.cpu0.fuPool.FUList5.opList04] 342type=OpDesc 343eventq_index=0 344opClass=SimdCvt 345opLat=1 346pipelined=true 347 348[system.cpu0.fuPool.FUList5.opList05] 349type=OpDesc 350eventq_index=0 351opClass=SimdMisc 352opLat=1 353pipelined=true 354 355[system.cpu0.fuPool.FUList5.opList06] 356type=OpDesc 357eventq_index=0 358opClass=SimdMult 359opLat=1 360pipelined=true 361 362[system.cpu0.fuPool.FUList5.opList07] 363type=OpDesc 364eventq_index=0 365opClass=SimdMultAcc 366opLat=1 367pipelined=true 368 369[system.cpu0.fuPool.FUList5.opList08] 370type=OpDesc 371eventq_index=0 372opClass=SimdShift 373opLat=1 374pipelined=true 375 376[system.cpu0.fuPool.FUList5.opList09] 377type=OpDesc 378eventq_index=0 379opClass=SimdShiftAcc 380opLat=1 381pipelined=true 382 383[system.cpu0.fuPool.FUList5.opList10] 384type=OpDesc 385eventq_index=0 386opClass=SimdSqrt 387opLat=1 388pipelined=true 389 390[system.cpu0.fuPool.FUList5.opList11] 391type=OpDesc 392eventq_index=0 393opClass=SimdFloatAdd 394opLat=1 395pipelined=true 396 397[system.cpu0.fuPool.FUList5.opList12] 398type=OpDesc 399eventq_index=0 400opClass=SimdFloatAlu 401opLat=1 402pipelined=true 403 404[system.cpu0.fuPool.FUList5.opList13] 405type=OpDesc 406eventq_index=0 407opClass=SimdFloatCmp 408opLat=1 409pipelined=true 410 411[system.cpu0.fuPool.FUList5.opList14] 412type=OpDesc 413eventq_index=0 414opClass=SimdFloatCvt 415opLat=1 416pipelined=true 417 418[system.cpu0.fuPool.FUList5.opList15] 419type=OpDesc 420eventq_index=0 421opClass=SimdFloatDiv 422opLat=1 423pipelined=true 424 425[system.cpu0.fuPool.FUList5.opList16] 426type=OpDesc 427eventq_index=0 428opClass=SimdFloatMisc 429opLat=1 430pipelined=true 431 432[system.cpu0.fuPool.FUList5.opList17] 433type=OpDesc 434eventq_index=0 435opClass=SimdFloatMult 436opLat=1 437pipelined=true 438 439[system.cpu0.fuPool.FUList5.opList18] 440type=OpDesc 441eventq_index=0 442opClass=SimdFloatMultAcc 443opLat=1 444pipelined=true 445 446[system.cpu0.fuPool.FUList5.opList19] 447type=OpDesc 448eventq_index=0 449opClass=SimdFloatSqrt 450opLat=1 451pipelined=true 452 453[system.cpu0.fuPool.FUList6] 454type=FUDesc 455children=opList 456count=0 457eventq_index=0 458opList=system.cpu0.fuPool.FUList6.opList 459 460[system.cpu0.fuPool.FUList6.opList] 461type=OpDesc 462eventq_index=0 463opClass=MemWrite 464opLat=1 465pipelined=true 466 467[system.cpu0.fuPool.FUList7] 468type=FUDesc 469children=opList0 opList1 470count=4 471eventq_index=0 472opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 473 474[system.cpu0.fuPool.FUList7.opList0] 475type=OpDesc 476eventq_index=0 477opClass=MemRead 478opLat=1 479pipelined=true 480 481[system.cpu0.fuPool.FUList7.opList1] 482type=OpDesc 483eventq_index=0 484opClass=MemWrite 485opLat=1 486pipelined=true 487 488[system.cpu0.fuPool.FUList8] 489type=FUDesc 490children=opList 491count=1 492eventq_index=0 493opList=system.cpu0.fuPool.FUList8.opList 494 495[system.cpu0.fuPool.FUList8.opList] 496type=OpDesc 497eventq_index=0 498opClass=IprAccess 499opLat=3 500pipelined=false 501 502[system.cpu0.icache] 503type=Cache 504children=tags 505addr_ranges=0:18446744073709551615 506assoc=1 507clk_domain=system.cpu_clk_domain 508clusivity=mostly_incl 509demand_mshr_reserve=1 510eventq_index=0 511forward_snoops=true 512hit_latency=2 513is_read_only=true 514max_miss_count=0 515mshrs=4 516prefetch_on_access=false 517prefetcher=Null 518response_latency=2 519sequential_access=false 520size=32768 521system=system 522tags=system.cpu0.icache.tags 523tgts_per_mshr=20 524write_buffers=8 525writeback_clean=true 526cpu_side=system.cpu0.icache_port 527mem_side=system.toL2Bus.slave[0] 528 529[system.cpu0.icache.tags] 530type=LRU 531assoc=1 532block_size=64 533clk_domain=system.cpu_clk_domain 534eventq_index=0 535hit_latency=2 536sequential_access=false 537size=32768 538 539[system.cpu0.interrupts] 540type=SparcInterrupts 541eventq_index=0 542 543[system.cpu0.isa] 544type=SparcISA 545eventq_index=0 546 547[system.cpu0.itb] 548type=SparcTLB 549eventq_index=0 550size=64 551 552[system.cpu0.tracer] 553type=ExeTracer 554eventq_index=0 555 556[system.cpu0.workload] 557type=LiveProcess 558cmd=test_atomic 4 559cwd= 560drivers= 561egid=100 562env= 563errout=cerr 564euid=100 565eventq_index=0 566executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic 567gid=100 568input=cin 569kvmInSE=false 570max_stack_size=67108864 571output=cout 572pid=100 573ppid=99 574simpoint=0 575system=system 576uid=100 577useArchPT=false 578 579[system.cpu1] 580type=DerivO3CPU 581children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 582LFSTSize=1024 583LQEntries=32 584LSQCheckLoads=true 585LSQDepCheckShift=4 586SQEntries=32 587SSITSize=1024 588activity=0 589backComSize=5 590branchPred=system.cpu1.branchPred 591cachePorts=200 592checker=Null 593clk_domain=system.cpu_clk_domain 594commitToDecodeDelay=1 595commitToFetchDelay=1 596commitToIEWDelay=1 597commitToRenameDelay=1 598commitWidth=8 599cpu_id=1 600decodeToFetchDelay=1 601decodeToRenameDelay=1 602decodeWidth=8 603dispatchWidth=8 604do_checkpoint_insts=true 605do_quiesce=true 606do_statistics_insts=true 607dtb=system.cpu1.dtb 608eventq_index=0 609fetchBufferSize=64 610fetchQueueSize=32 611fetchToDecodeDelay=1 612fetchTrapLatency=1 613fetchWidth=8 614forwardComSize=5 615fuPool=system.cpu1.fuPool 616function_trace=false 617function_trace_start=0 618iewToCommitDelay=1 619iewToDecodeDelay=1 620iewToFetchDelay=1 621iewToRenameDelay=1 622interrupts=system.cpu1.interrupts 623isa=system.cpu1.isa 624issueToExecuteDelay=1 625issueWidth=8 626itb=system.cpu1.itb 627max_insts_all_threads=0 628max_insts_any_thread=0 629max_loads_all_threads=0 630max_loads_any_thread=0 631needsTSO=false 632numIQEntries=64 633numPhysCCRegs=0 634numPhysFloatRegs=256 635numPhysIntRegs=256 636numROBEntries=192 637numRobs=1 638numThreads=1 639profile=0 640progress_interval=0 641renameToDecodeDelay=1 642renameToFetchDelay=1 643renameToIEWDelay=2 644renameToROBDelay=1 645renameWidth=8 646simpoint_start_insts= 647smtCommitPolicy=RoundRobin 648smtFetchPolicy=SingleThread 649smtIQPolicy=Partitioned 650smtIQThreshold=100 651smtLSQPolicy=Partitioned 652smtLSQThreshold=100 653smtNumFetchingThreads=1 654smtROBPolicy=Partitioned 655smtROBThreshold=100 656socket_id=0 657squashWidth=8 658store_set_clear_period=250000 659switched_out=false 660system=system 661tracer=system.cpu1.tracer 662trapLatency=13 663wbWidth=8 664workload=system.cpu0.workload 665dcache_port=system.cpu1.dcache.cpu_side 666icache_port=system.cpu1.icache.cpu_side 667 668[system.cpu1.branchPred] 669type=TournamentBP 670BTBEntries=4096 671BTBTagSize=16 672RASSize=16 673choiceCtrBits=2 674choicePredictorSize=8192 675eventq_index=0 676globalCtrBits=2 677globalPredictorSize=8192 678instShiftAmt=2 679localCtrBits=2 680localHistoryTableSize=2048 681localPredictorSize=2048 682numThreads=1 683 684[system.cpu1.dcache] 685type=Cache 686children=tags 687addr_ranges=0:18446744073709551615 688assoc=4 689clk_domain=system.cpu_clk_domain 690clusivity=mostly_incl 691demand_mshr_reserve=1 692eventq_index=0 693forward_snoops=true 694hit_latency=2 695is_read_only=false 696max_miss_count=0 697mshrs=4 698prefetch_on_access=false 699prefetcher=Null 700response_latency=2 701sequential_access=false 702size=32768 703system=system 704tags=system.cpu1.dcache.tags 705tgts_per_mshr=20 706write_buffers=8 707writeback_clean=false 708cpu_side=system.cpu1.dcache_port 709mem_side=system.toL2Bus.slave[3] 710 711[system.cpu1.dcache.tags] 712type=LRU 713assoc=4 714block_size=64 715clk_domain=system.cpu_clk_domain 716eventq_index=0 717hit_latency=2 718sequential_access=false 719size=32768 720 721[system.cpu1.dtb] 722type=SparcTLB 723eventq_index=0 724size=64 725 726[system.cpu1.fuPool] 727type=FUPool 728children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 729FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 730eventq_index=0 731 732[system.cpu1.fuPool.FUList0] 733type=FUDesc 734children=opList 735count=6 736eventq_index=0 737opList=system.cpu1.fuPool.FUList0.opList 738 739[system.cpu1.fuPool.FUList0.opList] 740type=OpDesc 741eventq_index=0 742opClass=IntAlu 743opLat=1 744pipelined=true 745 746[system.cpu1.fuPool.FUList1] 747type=FUDesc 748children=opList0 opList1 749count=2 750eventq_index=0 751opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 752 753[system.cpu1.fuPool.FUList1.opList0] 754type=OpDesc 755eventq_index=0 756opClass=IntMult 757opLat=3 758pipelined=true 759 760[system.cpu1.fuPool.FUList1.opList1] 761type=OpDesc 762eventq_index=0 763opClass=IntDiv 764opLat=20 765pipelined=false 766 767[system.cpu1.fuPool.FUList2] 768type=FUDesc 769children=opList0 opList1 opList2 770count=4 771eventq_index=0 772opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 773 774[system.cpu1.fuPool.FUList2.opList0] 775type=OpDesc 776eventq_index=0 777opClass=FloatAdd 778opLat=2 779pipelined=true 780 781[system.cpu1.fuPool.FUList2.opList1] 782type=OpDesc 783eventq_index=0 784opClass=FloatCmp 785opLat=2 786pipelined=true 787 788[system.cpu1.fuPool.FUList2.opList2] 789type=OpDesc 790eventq_index=0 791opClass=FloatCvt 792opLat=2 793pipelined=true 794 795[system.cpu1.fuPool.FUList3] 796type=FUDesc 797children=opList0 opList1 opList2 798count=2 799eventq_index=0 800opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 801 802[system.cpu1.fuPool.FUList3.opList0] 803type=OpDesc 804eventq_index=0 805opClass=FloatMult 806opLat=4 807pipelined=true 808 809[system.cpu1.fuPool.FUList3.opList1] 810type=OpDesc 811eventq_index=0 812opClass=FloatDiv 813opLat=12 814pipelined=false 815 816[system.cpu1.fuPool.FUList3.opList2] 817type=OpDesc 818eventq_index=0 819opClass=FloatSqrt 820opLat=24 821pipelined=false 822 823[system.cpu1.fuPool.FUList4] 824type=FUDesc 825children=opList 826count=0 827eventq_index=0 828opList=system.cpu1.fuPool.FUList4.opList 829 830[system.cpu1.fuPool.FUList4.opList] 831type=OpDesc 832eventq_index=0 833opClass=MemRead 834opLat=1 835pipelined=true 836 837[system.cpu1.fuPool.FUList5] 838type=FUDesc 839children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 840count=4 841eventq_index=0 842opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 843 844[system.cpu1.fuPool.FUList5.opList00] 845type=OpDesc 846eventq_index=0 847opClass=SimdAdd 848opLat=1 849pipelined=true 850 851[system.cpu1.fuPool.FUList5.opList01] 852type=OpDesc 853eventq_index=0 854opClass=SimdAddAcc 855opLat=1 856pipelined=true 857 858[system.cpu1.fuPool.FUList5.opList02] 859type=OpDesc 860eventq_index=0 861opClass=SimdAlu 862opLat=1 863pipelined=true 864 865[system.cpu1.fuPool.FUList5.opList03] 866type=OpDesc 867eventq_index=0 868opClass=SimdCmp 869opLat=1 870pipelined=true 871 872[system.cpu1.fuPool.FUList5.opList04] 873type=OpDesc 874eventq_index=0 875opClass=SimdCvt 876opLat=1 877pipelined=true 878 879[system.cpu1.fuPool.FUList5.opList05] 880type=OpDesc 881eventq_index=0 882opClass=SimdMisc 883opLat=1 884pipelined=true 885 886[system.cpu1.fuPool.FUList5.opList06] 887type=OpDesc 888eventq_index=0 889opClass=SimdMult 890opLat=1 891pipelined=true 892 893[system.cpu1.fuPool.FUList5.opList07] 894type=OpDesc 895eventq_index=0 896opClass=SimdMultAcc 897opLat=1 898pipelined=true 899 900[system.cpu1.fuPool.FUList5.opList08] 901type=OpDesc 902eventq_index=0 903opClass=SimdShift 904opLat=1 905pipelined=true 906 907[system.cpu1.fuPool.FUList5.opList09] 908type=OpDesc 909eventq_index=0 910opClass=SimdShiftAcc 911opLat=1 912pipelined=true 913 914[system.cpu1.fuPool.FUList5.opList10] 915type=OpDesc 916eventq_index=0 917opClass=SimdSqrt 918opLat=1 919pipelined=true 920 921[system.cpu1.fuPool.FUList5.opList11] 922type=OpDesc 923eventq_index=0 924opClass=SimdFloatAdd 925opLat=1 926pipelined=true 927 928[system.cpu1.fuPool.FUList5.opList12] 929type=OpDesc 930eventq_index=0 931opClass=SimdFloatAlu 932opLat=1 933pipelined=true 934 935[system.cpu1.fuPool.FUList5.opList13] 936type=OpDesc 937eventq_index=0 938opClass=SimdFloatCmp 939opLat=1 940pipelined=true 941 942[system.cpu1.fuPool.FUList5.opList14] 943type=OpDesc 944eventq_index=0 945opClass=SimdFloatCvt 946opLat=1 947pipelined=true 948 949[system.cpu1.fuPool.FUList5.opList15] 950type=OpDesc 951eventq_index=0 952opClass=SimdFloatDiv 953opLat=1 954pipelined=true 955 956[system.cpu1.fuPool.FUList5.opList16] 957type=OpDesc 958eventq_index=0 959opClass=SimdFloatMisc 960opLat=1 961pipelined=true 962 963[system.cpu1.fuPool.FUList5.opList17] 964type=OpDesc 965eventq_index=0 966opClass=SimdFloatMult 967opLat=1 968pipelined=true 969 970[system.cpu1.fuPool.FUList5.opList18] 971type=OpDesc 972eventq_index=0 973opClass=SimdFloatMultAcc 974opLat=1 975pipelined=true 976 977[system.cpu1.fuPool.FUList5.opList19] 978type=OpDesc 979eventq_index=0 980opClass=SimdFloatSqrt 981opLat=1 982pipelined=true 983 984[system.cpu1.fuPool.FUList6] 985type=FUDesc 986children=opList 987count=0 988eventq_index=0 989opList=system.cpu1.fuPool.FUList6.opList 990 991[system.cpu1.fuPool.FUList6.opList] 992type=OpDesc 993eventq_index=0 994opClass=MemWrite 995opLat=1 996pipelined=true 997 998[system.cpu1.fuPool.FUList7] 999type=FUDesc 1000children=opList0 opList1 1001count=4 1002eventq_index=0 1003opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 1004 1005[system.cpu1.fuPool.FUList7.opList0] 1006type=OpDesc 1007eventq_index=0 1008opClass=MemRead 1009opLat=1 1010pipelined=true 1011 1012[system.cpu1.fuPool.FUList7.opList1] 1013type=OpDesc 1014eventq_index=0 1015opClass=MemWrite 1016opLat=1 1017pipelined=true 1018 1019[system.cpu1.fuPool.FUList8] 1020type=FUDesc 1021children=opList 1022count=1 1023eventq_index=0 1024opList=system.cpu1.fuPool.FUList8.opList 1025 1026[system.cpu1.fuPool.FUList8.opList] 1027type=OpDesc 1028eventq_index=0 1029opClass=IprAccess 1030opLat=3 1031pipelined=false 1032 1033[system.cpu1.icache] 1034type=Cache 1035children=tags 1036addr_ranges=0:18446744073709551615 1037assoc=1 1038clk_domain=system.cpu_clk_domain 1039clusivity=mostly_incl 1040demand_mshr_reserve=1 1041eventq_index=0 1042forward_snoops=true 1043hit_latency=2 1044is_read_only=true 1045max_miss_count=0 1046mshrs=4 1047prefetch_on_access=false 1048prefetcher=Null 1049response_latency=2 1050sequential_access=false 1051size=32768 1052system=system 1053tags=system.cpu1.icache.tags 1054tgts_per_mshr=20 1055write_buffers=8 1056writeback_clean=true 1057cpu_side=system.cpu1.icache_port 1058mem_side=system.toL2Bus.slave[2] 1059 1060[system.cpu1.icache.tags] 1061type=LRU 1062assoc=1 1063block_size=64 1064clk_domain=system.cpu_clk_domain 1065eventq_index=0 1066hit_latency=2 1067sequential_access=false 1068size=32768 1069 1070[system.cpu1.interrupts] 1071type=SparcInterrupts 1072eventq_index=0 1073 1074[system.cpu1.isa] 1075type=SparcISA 1076eventq_index=0 1077 1078[system.cpu1.itb] 1079type=SparcTLB 1080eventq_index=0 1081size=64 1082 1083[system.cpu1.tracer] 1084type=ExeTracer 1085eventq_index=0 1086 1087[system.cpu2] 1088type=DerivO3CPU 1089children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1090LFSTSize=1024 1091LQEntries=32 1092LSQCheckLoads=true 1093LSQDepCheckShift=4 1094SQEntries=32 1095SSITSize=1024 1096activity=0 1097backComSize=5 1098branchPred=system.cpu2.branchPred 1099cachePorts=200 1100checker=Null 1101clk_domain=system.cpu_clk_domain 1102commitToDecodeDelay=1 1103commitToFetchDelay=1 1104commitToIEWDelay=1 1105commitToRenameDelay=1 1106commitWidth=8 1107cpu_id=2 1108decodeToFetchDelay=1 1109decodeToRenameDelay=1 1110decodeWidth=8 1111dispatchWidth=8 1112do_checkpoint_insts=true 1113do_quiesce=true 1114do_statistics_insts=true 1115dtb=system.cpu2.dtb 1116eventq_index=0 1117fetchBufferSize=64 1118fetchQueueSize=32 1119fetchToDecodeDelay=1 1120fetchTrapLatency=1 1121fetchWidth=8 1122forwardComSize=5 1123fuPool=system.cpu2.fuPool 1124function_trace=false 1125function_trace_start=0 1126iewToCommitDelay=1 1127iewToDecodeDelay=1 1128iewToFetchDelay=1 1129iewToRenameDelay=1 1130interrupts=system.cpu2.interrupts 1131isa=system.cpu2.isa 1132issueToExecuteDelay=1 1133issueWidth=8 1134itb=system.cpu2.itb 1135max_insts_all_threads=0 1136max_insts_any_thread=0 1137max_loads_all_threads=0 1138max_loads_any_thread=0 1139needsTSO=false 1140numIQEntries=64 1141numPhysCCRegs=0 1142numPhysFloatRegs=256 1143numPhysIntRegs=256 1144numROBEntries=192 1145numRobs=1 1146numThreads=1 1147profile=0 1148progress_interval=0 1149renameToDecodeDelay=1 1150renameToFetchDelay=1 1151renameToIEWDelay=2 1152renameToROBDelay=1 1153renameWidth=8 1154simpoint_start_insts= 1155smtCommitPolicy=RoundRobin 1156smtFetchPolicy=SingleThread 1157smtIQPolicy=Partitioned 1158smtIQThreshold=100 1159smtLSQPolicy=Partitioned 1160smtLSQThreshold=100 1161smtNumFetchingThreads=1 1162smtROBPolicy=Partitioned 1163smtROBThreshold=100 1164socket_id=0 1165squashWidth=8 1166store_set_clear_period=250000 1167switched_out=false 1168system=system 1169tracer=system.cpu2.tracer 1170trapLatency=13 1171wbWidth=8 1172workload=system.cpu0.workload 1173dcache_port=system.cpu2.dcache.cpu_side 1174icache_port=system.cpu2.icache.cpu_side 1175 1176[system.cpu2.branchPred] 1177type=TournamentBP 1178BTBEntries=4096 1179BTBTagSize=16 1180RASSize=16 1181choiceCtrBits=2 1182choicePredictorSize=8192 1183eventq_index=0 1184globalCtrBits=2 1185globalPredictorSize=8192 1186instShiftAmt=2 1187localCtrBits=2 1188localHistoryTableSize=2048 1189localPredictorSize=2048 1190numThreads=1 1191 1192[system.cpu2.dcache] 1193type=Cache 1194children=tags 1195addr_ranges=0:18446744073709551615 1196assoc=4 1197clk_domain=system.cpu_clk_domain 1198clusivity=mostly_incl 1199demand_mshr_reserve=1 1200eventq_index=0 1201forward_snoops=true 1202hit_latency=2 1203is_read_only=false 1204max_miss_count=0 1205mshrs=4 1206prefetch_on_access=false 1207prefetcher=Null 1208response_latency=2 1209sequential_access=false 1210size=32768 1211system=system 1212tags=system.cpu2.dcache.tags 1213tgts_per_mshr=20 1214write_buffers=8 1215writeback_clean=false 1216cpu_side=system.cpu2.dcache_port 1217mem_side=system.toL2Bus.slave[5] 1218 1219[system.cpu2.dcache.tags] 1220type=LRU 1221assoc=4 1222block_size=64 1223clk_domain=system.cpu_clk_domain 1224eventq_index=0 1225hit_latency=2 1226sequential_access=false 1227size=32768 1228 1229[system.cpu2.dtb] 1230type=SparcTLB 1231eventq_index=0 1232size=64 1233 1234[system.cpu2.fuPool] 1235type=FUPool 1236children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1237FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 1238eventq_index=0 1239 1240[system.cpu2.fuPool.FUList0] 1241type=FUDesc 1242children=opList 1243count=6 1244eventq_index=0 1245opList=system.cpu2.fuPool.FUList0.opList 1246 1247[system.cpu2.fuPool.FUList0.opList] 1248type=OpDesc 1249eventq_index=0 1250opClass=IntAlu 1251opLat=1 1252pipelined=true 1253 1254[system.cpu2.fuPool.FUList1] 1255type=FUDesc 1256children=opList0 opList1 1257count=2 1258eventq_index=0 1259opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 1260 1261[system.cpu2.fuPool.FUList1.opList0] 1262type=OpDesc 1263eventq_index=0 1264opClass=IntMult 1265opLat=3 1266pipelined=true 1267 1268[system.cpu2.fuPool.FUList1.opList1] 1269type=OpDesc 1270eventq_index=0 1271opClass=IntDiv 1272opLat=20 1273pipelined=false 1274 1275[system.cpu2.fuPool.FUList2] 1276type=FUDesc 1277children=opList0 opList1 opList2 1278count=4 1279eventq_index=0 1280opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 1281 1282[system.cpu2.fuPool.FUList2.opList0] 1283type=OpDesc 1284eventq_index=0 1285opClass=FloatAdd 1286opLat=2 1287pipelined=true 1288 1289[system.cpu2.fuPool.FUList2.opList1] 1290type=OpDesc 1291eventq_index=0 1292opClass=FloatCmp 1293opLat=2 1294pipelined=true 1295 1296[system.cpu2.fuPool.FUList2.opList2] 1297type=OpDesc 1298eventq_index=0 1299opClass=FloatCvt 1300opLat=2 1301pipelined=true 1302 1303[system.cpu2.fuPool.FUList3] 1304type=FUDesc 1305children=opList0 opList1 opList2 1306count=2 1307eventq_index=0 1308opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 1309 1310[system.cpu2.fuPool.FUList3.opList0] 1311type=OpDesc 1312eventq_index=0 1313opClass=FloatMult 1314opLat=4 1315pipelined=true 1316 1317[system.cpu2.fuPool.FUList3.opList1] 1318type=OpDesc 1319eventq_index=0 1320opClass=FloatDiv 1321opLat=12 1322pipelined=false 1323 1324[system.cpu2.fuPool.FUList3.opList2] 1325type=OpDesc 1326eventq_index=0 1327opClass=FloatSqrt 1328opLat=24 1329pipelined=false 1330 1331[system.cpu2.fuPool.FUList4] 1332type=FUDesc 1333children=opList 1334count=0 1335eventq_index=0 1336opList=system.cpu2.fuPool.FUList4.opList 1337 1338[system.cpu2.fuPool.FUList4.opList] 1339type=OpDesc 1340eventq_index=0 1341opClass=MemRead 1342opLat=1 1343pipelined=true 1344 1345[system.cpu2.fuPool.FUList5] 1346type=FUDesc 1347children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1348count=4 1349eventq_index=0 1350opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 1351 1352[system.cpu2.fuPool.FUList5.opList00] 1353type=OpDesc 1354eventq_index=0 1355opClass=SimdAdd 1356opLat=1 1357pipelined=true 1358 1359[system.cpu2.fuPool.FUList5.opList01] 1360type=OpDesc 1361eventq_index=0 1362opClass=SimdAddAcc 1363opLat=1 1364pipelined=true 1365 1366[system.cpu2.fuPool.FUList5.opList02] 1367type=OpDesc 1368eventq_index=0 1369opClass=SimdAlu 1370opLat=1 1371pipelined=true 1372 1373[system.cpu2.fuPool.FUList5.opList03] 1374type=OpDesc 1375eventq_index=0 1376opClass=SimdCmp 1377opLat=1 1378pipelined=true 1379 1380[system.cpu2.fuPool.FUList5.opList04] 1381type=OpDesc 1382eventq_index=0 1383opClass=SimdCvt 1384opLat=1 1385pipelined=true 1386 1387[system.cpu2.fuPool.FUList5.opList05] 1388type=OpDesc 1389eventq_index=0 1390opClass=SimdMisc 1391opLat=1 1392pipelined=true 1393 1394[system.cpu2.fuPool.FUList5.opList06] 1395type=OpDesc 1396eventq_index=0 1397opClass=SimdMult 1398opLat=1 1399pipelined=true 1400 1401[system.cpu2.fuPool.FUList5.opList07] 1402type=OpDesc 1403eventq_index=0 1404opClass=SimdMultAcc 1405opLat=1 1406pipelined=true 1407 1408[system.cpu2.fuPool.FUList5.opList08] 1409type=OpDesc 1410eventq_index=0 1411opClass=SimdShift 1412opLat=1 1413pipelined=true 1414 1415[system.cpu2.fuPool.FUList5.opList09] 1416type=OpDesc 1417eventq_index=0 1418opClass=SimdShiftAcc 1419opLat=1 1420pipelined=true 1421 1422[system.cpu2.fuPool.FUList5.opList10] 1423type=OpDesc 1424eventq_index=0 1425opClass=SimdSqrt 1426opLat=1 1427pipelined=true 1428 1429[system.cpu2.fuPool.FUList5.opList11] 1430type=OpDesc 1431eventq_index=0 1432opClass=SimdFloatAdd 1433opLat=1 1434pipelined=true 1435 1436[system.cpu2.fuPool.FUList5.opList12] 1437type=OpDesc 1438eventq_index=0 1439opClass=SimdFloatAlu 1440opLat=1 1441pipelined=true 1442 1443[system.cpu2.fuPool.FUList5.opList13] 1444type=OpDesc 1445eventq_index=0 1446opClass=SimdFloatCmp 1447opLat=1 1448pipelined=true 1449 1450[system.cpu2.fuPool.FUList5.opList14] 1451type=OpDesc 1452eventq_index=0 1453opClass=SimdFloatCvt 1454opLat=1 1455pipelined=true 1456 1457[system.cpu2.fuPool.FUList5.opList15] 1458type=OpDesc 1459eventq_index=0 1460opClass=SimdFloatDiv 1461opLat=1 1462pipelined=true 1463 1464[system.cpu2.fuPool.FUList5.opList16] 1465type=OpDesc 1466eventq_index=0 1467opClass=SimdFloatMisc 1468opLat=1 1469pipelined=true 1470 1471[system.cpu2.fuPool.FUList5.opList17] 1472type=OpDesc 1473eventq_index=0 1474opClass=SimdFloatMult 1475opLat=1 1476pipelined=true 1477 1478[system.cpu2.fuPool.FUList5.opList18] 1479type=OpDesc 1480eventq_index=0 1481opClass=SimdFloatMultAcc 1482opLat=1 1483pipelined=true 1484 1485[system.cpu2.fuPool.FUList5.opList19] 1486type=OpDesc 1487eventq_index=0 1488opClass=SimdFloatSqrt 1489opLat=1 1490pipelined=true 1491 1492[system.cpu2.fuPool.FUList6] 1493type=FUDesc 1494children=opList 1495count=0 1496eventq_index=0 1497opList=system.cpu2.fuPool.FUList6.opList 1498 1499[system.cpu2.fuPool.FUList6.opList] 1500type=OpDesc 1501eventq_index=0 1502opClass=MemWrite 1503opLat=1 1504pipelined=true 1505 1506[system.cpu2.fuPool.FUList7] 1507type=FUDesc 1508children=opList0 opList1 1509count=4 1510eventq_index=0 1511opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 1512 1513[system.cpu2.fuPool.FUList7.opList0] 1514type=OpDesc 1515eventq_index=0 1516opClass=MemRead 1517opLat=1 1518pipelined=true 1519 1520[system.cpu2.fuPool.FUList7.opList1] 1521type=OpDesc 1522eventq_index=0 1523opClass=MemWrite 1524opLat=1 1525pipelined=true 1526 1527[system.cpu2.fuPool.FUList8] 1528type=FUDesc 1529children=opList 1530count=1 1531eventq_index=0 1532opList=system.cpu2.fuPool.FUList8.opList 1533 1534[system.cpu2.fuPool.FUList8.opList] 1535type=OpDesc 1536eventq_index=0 1537opClass=IprAccess 1538opLat=3 1539pipelined=false 1540 1541[system.cpu2.icache] 1542type=Cache 1543children=tags 1544addr_ranges=0:18446744073709551615 1545assoc=1 1546clk_domain=system.cpu_clk_domain 1547clusivity=mostly_incl 1548demand_mshr_reserve=1 1549eventq_index=0 1550forward_snoops=true 1551hit_latency=2 1552is_read_only=true 1553max_miss_count=0 1554mshrs=4 1555prefetch_on_access=false 1556prefetcher=Null 1557response_latency=2 1558sequential_access=false 1559size=32768 1560system=system 1561tags=system.cpu2.icache.tags 1562tgts_per_mshr=20 1563write_buffers=8 1564writeback_clean=true 1565cpu_side=system.cpu2.icache_port 1566mem_side=system.toL2Bus.slave[4] 1567 1568[system.cpu2.icache.tags] 1569type=LRU 1570assoc=1 1571block_size=64 1572clk_domain=system.cpu_clk_domain 1573eventq_index=0 1574hit_latency=2 1575sequential_access=false 1576size=32768 1577 1578[system.cpu2.interrupts] 1579type=SparcInterrupts 1580eventq_index=0 1581 1582[system.cpu2.isa] 1583type=SparcISA 1584eventq_index=0 1585 1586[system.cpu2.itb] 1587type=SparcTLB 1588eventq_index=0 1589size=64 1590 1591[system.cpu2.tracer] 1592type=ExeTracer 1593eventq_index=0 1594 1595[system.cpu3] 1596type=DerivO3CPU 1597children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 1598LFSTSize=1024 1599LQEntries=32 1600LSQCheckLoads=true 1601LSQDepCheckShift=4 1602SQEntries=32 1603SSITSize=1024 1604activity=0 1605backComSize=5 1606branchPred=system.cpu3.branchPred 1607cachePorts=200 1608checker=Null 1609clk_domain=system.cpu_clk_domain 1610commitToDecodeDelay=1 1611commitToFetchDelay=1 1612commitToIEWDelay=1 1613commitToRenameDelay=1 1614commitWidth=8 1615cpu_id=3 1616decodeToFetchDelay=1 1617decodeToRenameDelay=1 1618decodeWidth=8 1619dispatchWidth=8 1620do_checkpoint_insts=true 1621do_quiesce=true 1622do_statistics_insts=true 1623dtb=system.cpu3.dtb 1624eventq_index=0 1625fetchBufferSize=64 1626fetchQueueSize=32 1627fetchToDecodeDelay=1 1628fetchTrapLatency=1 1629fetchWidth=8 1630forwardComSize=5 1631fuPool=system.cpu3.fuPool 1632function_trace=false 1633function_trace_start=0 1634iewToCommitDelay=1 1635iewToDecodeDelay=1 1636iewToFetchDelay=1 1637iewToRenameDelay=1 1638interrupts=system.cpu3.interrupts 1639isa=system.cpu3.isa 1640issueToExecuteDelay=1 1641issueWidth=8 1642itb=system.cpu3.itb 1643max_insts_all_threads=0 1644max_insts_any_thread=0 1645max_loads_all_threads=0 1646max_loads_any_thread=0 1647needsTSO=false 1648numIQEntries=64 1649numPhysCCRegs=0 1650numPhysFloatRegs=256 1651numPhysIntRegs=256 1652numROBEntries=192 1653numRobs=1 1654numThreads=1 1655profile=0 1656progress_interval=0 1657renameToDecodeDelay=1 1658renameToFetchDelay=1 1659renameToIEWDelay=2 1660renameToROBDelay=1 1661renameWidth=8 1662simpoint_start_insts= 1663smtCommitPolicy=RoundRobin 1664smtFetchPolicy=SingleThread 1665smtIQPolicy=Partitioned 1666smtIQThreshold=100 1667smtLSQPolicy=Partitioned 1668smtLSQThreshold=100 1669smtNumFetchingThreads=1 1670smtROBPolicy=Partitioned 1671smtROBThreshold=100 1672socket_id=0 1673squashWidth=8 1674store_set_clear_period=250000 1675switched_out=false 1676system=system 1677tracer=system.cpu3.tracer 1678trapLatency=13 1679wbWidth=8 1680workload=system.cpu0.workload 1681dcache_port=system.cpu3.dcache.cpu_side 1682icache_port=system.cpu3.icache.cpu_side 1683 1684[system.cpu3.branchPred] 1685type=TournamentBP 1686BTBEntries=4096 1687BTBTagSize=16 1688RASSize=16 1689choiceCtrBits=2 1690choicePredictorSize=8192 1691eventq_index=0 1692globalCtrBits=2 1693globalPredictorSize=8192 1694instShiftAmt=2 1695localCtrBits=2 1696localHistoryTableSize=2048 1697localPredictorSize=2048 1698numThreads=1 1699 1700[system.cpu3.dcache] 1701type=Cache 1702children=tags 1703addr_ranges=0:18446744073709551615 1704assoc=4 1705clk_domain=system.cpu_clk_domain 1706clusivity=mostly_incl 1707demand_mshr_reserve=1 1708eventq_index=0 1709forward_snoops=true 1710hit_latency=2 1711is_read_only=false 1712max_miss_count=0 1713mshrs=4 1714prefetch_on_access=false 1715prefetcher=Null 1716response_latency=2 1717sequential_access=false 1718size=32768 1719system=system 1720tags=system.cpu3.dcache.tags 1721tgts_per_mshr=20 1722write_buffers=8 1723writeback_clean=false 1724cpu_side=system.cpu3.dcache_port 1725mem_side=system.toL2Bus.slave[7] 1726 1727[system.cpu3.dcache.tags] 1728type=LRU 1729assoc=4 1730block_size=64 1731clk_domain=system.cpu_clk_domain 1732eventq_index=0 1733hit_latency=2 1734sequential_access=false 1735size=32768 1736 1737[system.cpu3.dtb] 1738type=SparcTLB 1739eventq_index=0 1740size=64 1741 1742[system.cpu3.fuPool] 1743type=FUPool 1744children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1745FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 1746eventq_index=0 1747 1748[system.cpu3.fuPool.FUList0] 1749type=FUDesc 1750children=opList 1751count=6 1752eventq_index=0 1753opList=system.cpu3.fuPool.FUList0.opList 1754 1755[system.cpu3.fuPool.FUList0.opList] 1756type=OpDesc 1757eventq_index=0 1758opClass=IntAlu 1759opLat=1 1760pipelined=true 1761 1762[system.cpu3.fuPool.FUList1] 1763type=FUDesc 1764children=opList0 opList1 1765count=2 1766eventq_index=0 1767opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 1768 1769[system.cpu3.fuPool.FUList1.opList0] 1770type=OpDesc 1771eventq_index=0 1772opClass=IntMult 1773opLat=3 1774pipelined=true 1775 1776[system.cpu3.fuPool.FUList1.opList1] 1777type=OpDesc 1778eventq_index=0 1779opClass=IntDiv 1780opLat=20 1781pipelined=false 1782 1783[system.cpu3.fuPool.FUList2] 1784type=FUDesc 1785children=opList0 opList1 opList2 1786count=4 1787eventq_index=0 1788opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 1789 1790[system.cpu3.fuPool.FUList2.opList0] 1791type=OpDesc 1792eventq_index=0 1793opClass=FloatAdd 1794opLat=2 1795pipelined=true 1796 1797[system.cpu3.fuPool.FUList2.opList1] 1798type=OpDesc 1799eventq_index=0 1800opClass=FloatCmp 1801opLat=2 1802pipelined=true 1803 1804[system.cpu3.fuPool.FUList2.opList2] 1805type=OpDesc 1806eventq_index=0 1807opClass=FloatCvt 1808opLat=2 1809pipelined=true 1810 1811[system.cpu3.fuPool.FUList3] 1812type=FUDesc 1813children=opList0 opList1 opList2 1814count=2 1815eventq_index=0 1816opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 1817 1818[system.cpu3.fuPool.FUList3.opList0] 1819type=OpDesc 1820eventq_index=0 1821opClass=FloatMult 1822opLat=4 1823pipelined=true 1824 1825[system.cpu3.fuPool.FUList3.opList1] 1826type=OpDesc 1827eventq_index=0 1828opClass=FloatDiv 1829opLat=12 1830pipelined=false 1831 1832[system.cpu3.fuPool.FUList3.opList2] 1833type=OpDesc 1834eventq_index=0 1835opClass=FloatSqrt 1836opLat=24 1837pipelined=false 1838 1839[system.cpu3.fuPool.FUList4] 1840type=FUDesc 1841children=opList 1842count=0 1843eventq_index=0 1844opList=system.cpu3.fuPool.FUList4.opList 1845 1846[system.cpu3.fuPool.FUList4.opList] 1847type=OpDesc 1848eventq_index=0 1849opClass=MemRead 1850opLat=1 1851pipelined=true 1852 1853[system.cpu3.fuPool.FUList5] 1854type=FUDesc 1855children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 1856count=4 1857eventq_index=0 1858opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 1859 1860[system.cpu3.fuPool.FUList5.opList00] 1861type=OpDesc 1862eventq_index=0 1863opClass=SimdAdd 1864opLat=1 1865pipelined=true 1866 1867[system.cpu3.fuPool.FUList5.opList01] 1868type=OpDesc 1869eventq_index=0 1870opClass=SimdAddAcc 1871opLat=1 1872pipelined=true 1873 1874[system.cpu3.fuPool.FUList5.opList02] 1875type=OpDesc 1876eventq_index=0 1877opClass=SimdAlu 1878opLat=1 1879pipelined=true 1880 1881[system.cpu3.fuPool.FUList5.opList03] 1882type=OpDesc 1883eventq_index=0 1884opClass=SimdCmp 1885opLat=1 1886pipelined=true 1887 1888[system.cpu3.fuPool.FUList5.opList04] 1889type=OpDesc 1890eventq_index=0 1891opClass=SimdCvt 1892opLat=1 1893pipelined=true 1894 1895[system.cpu3.fuPool.FUList5.opList05] 1896type=OpDesc 1897eventq_index=0 1898opClass=SimdMisc 1899opLat=1 1900pipelined=true 1901 1902[system.cpu3.fuPool.FUList5.opList06] 1903type=OpDesc 1904eventq_index=0 1905opClass=SimdMult 1906opLat=1 1907pipelined=true 1908 1909[system.cpu3.fuPool.FUList5.opList07] 1910type=OpDesc 1911eventq_index=0 1912opClass=SimdMultAcc 1913opLat=1 1914pipelined=true 1915 1916[system.cpu3.fuPool.FUList5.opList08] 1917type=OpDesc 1918eventq_index=0 1919opClass=SimdShift 1920opLat=1 1921pipelined=true 1922 1923[system.cpu3.fuPool.FUList5.opList09] 1924type=OpDesc 1925eventq_index=0 1926opClass=SimdShiftAcc 1927opLat=1 1928pipelined=true 1929 1930[system.cpu3.fuPool.FUList5.opList10] 1931type=OpDesc 1932eventq_index=0 1933opClass=SimdSqrt 1934opLat=1 1935pipelined=true 1936 1937[system.cpu3.fuPool.FUList5.opList11] 1938type=OpDesc 1939eventq_index=0 1940opClass=SimdFloatAdd 1941opLat=1 1942pipelined=true 1943 1944[system.cpu3.fuPool.FUList5.opList12] 1945type=OpDesc 1946eventq_index=0 1947opClass=SimdFloatAlu 1948opLat=1 1949pipelined=true 1950 1951[system.cpu3.fuPool.FUList5.opList13] 1952type=OpDesc 1953eventq_index=0 1954opClass=SimdFloatCmp 1955opLat=1 1956pipelined=true 1957 1958[system.cpu3.fuPool.FUList5.opList14] 1959type=OpDesc 1960eventq_index=0 1961opClass=SimdFloatCvt 1962opLat=1 1963pipelined=true 1964 1965[system.cpu3.fuPool.FUList5.opList15] 1966type=OpDesc 1967eventq_index=0 1968opClass=SimdFloatDiv 1969opLat=1 1970pipelined=true 1971 1972[system.cpu3.fuPool.FUList5.opList16] 1973type=OpDesc 1974eventq_index=0 1975opClass=SimdFloatMisc 1976opLat=1 1977pipelined=true 1978 1979[system.cpu3.fuPool.FUList5.opList17] 1980type=OpDesc 1981eventq_index=0 1982opClass=SimdFloatMult 1983opLat=1 1984pipelined=true 1985 1986[system.cpu3.fuPool.FUList5.opList18] 1987type=OpDesc 1988eventq_index=0 1989opClass=SimdFloatMultAcc 1990opLat=1 1991pipelined=true 1992 1993[system.cpu3.fuPool.FUList5.opList19] 1994type=OpDesc 1995eventq_index=0 1996opClass=SimdFloatSqrt 1997opLat=1 1998pipelined=true 1999 2000[system.cpu3.fuPool.FUList6] 2001type=FUDesc 2002children=opList 2003count=0 2004eventq_index=0 2005opList=system.cpu3.fuPool.FUList6.opList 2006 2007[system.cpu3.fuPool.FUList6.opList] 2008type=OpDesc 2009eventq_index=0 2010opClass=MemWrite 2011opLat=1 2012pipelined=true 2013 2014[system.cpu3.fuPool.FUList7] 2015type=FUDesc 2016children=opList0 opList1 2017count=4 2018eventq_index=0 2019opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 2020 2021[system.cpu3.fuPool.FUList7.opList0] 2022type=OpDesc 2023eventq_index=0 2024opClass=MemRead 2025opLat=1 2026pipelined=true 2027 2028[system.cpu3.fuPool.FUList7.opList1] 2029type=OpDesc 2030eventq_index=0 2031opClass=MemWrite 2032opLat=1 2033pipelined=true 2034 2035[system.cpu3.fuPool.FUList8] 2036type=FUDesc 2037children=opList 2038count=1 2039eventq_index=0 2040opList=system.cpu3.fuPool.FUList8.opList 2041 2042[system.cpu3.fuPool.FUList8.opList] 2043type=OpDesc 2044eventq_index=0 2045opClass=IprAccess 2046opLat=3 2047pipelined=false 2048 2049[system.cpu3.icache] 2050type=Cache 2051children=tags 2052addr_ranges=0:18446744073709551615 2053assoc=1 2054clk_domain=system.cpu_clk_domain 2055clusivity=mostly_incl 2056demand_mshr_reserve=1 2057eventq_index=0 2058forward_snoops=true 2059hit_latency=2 2060is_read_only=true 2061max_miss_count=0 2062mshrs=4 2063prefetch_on_access=false 2064prefetcher=Null 2065response_latency=2 2066sequential_access=false 2067size=32768 2068system=system 2069tags=system.cpu3.icache.tags 2070tgts_per_mshr=20 2071write_buffers=8 2072writeback_clean=true 2073cpu_side=system.cpu3.icache_port 2074mem_side=system.toL2Bus.slave[6] 2075 2076[system.cpu3.icache.tags] 2077type=LRU 2078assoc=1 2079block_size=64 2080clk_domain=system.cpu_clk_domain 2081eventq_index=0 2082hit_latency=2 2083sequential_access=false 2084size=32768 2085 2086[system.cpu3.interrupts] 2087type=SparcInterrupts 2088eventq_index=0 2089 2090[system.cpu3.isa] 2091type=SparcISA 2092eventq_index=0 2093 2094[system.cpu3.itb] 2095type=SparcTLB 2096eventq_index=0 2097size=64 2098 2099[system.cpu3.tracer] 2100type=ExeTracer 2101eventq_index=0 2102 2103[system.cpu_clk_domain] 2104type=SrcClockDomain 2105clock=500 2106domain_id=-1 2107eventq_index=0 2108init_perf_level=0 2109voltage_domain=system.voltage_domain 2110 2111[system.dvfs_handler] 2112type=DVFSHandler 2113domains= 2114enable=false 2115eventq_index=0 2116sys_clk_domain=system.clk_domain 2117transition_latency=100000000 2118 2119[system.l2c] 2120type=Cache 2121children=tags 2122addr_ranges=0:18446744073709551615 2123assoc=8 2124clk_domain=system.cpu_clk_domain 2125clusivity=mostly_incl 2126demand_mshr_reserve=1 2127eventq_index=0 2128forward_snoops=true 2129hit_latency=20 2130is_read_only=false 2131max_miss_count=0 2132mshrs=20 2133prefetch_on_access=false 2134prefetcher=Null 2135response_latency=20 2136sequential_access=false 2137size=4194304 2138system=system 2139tags=system.l2c.tags 2140tgts_per_mshr=12 2141write_buffers=8 2142writeback_clean=false 2143cpu_side=system.toL2Bus.master[0] 2144mem_side=system.membus.slave[1] 2145 2146[system.l2c.tags] 2147type=LRU 2148assoc=8 2149block_size=64 2150clk_domain=system.cpu_clk_domain 2151eventq_index=0 2152hit_latency=20 2153sequential_access=false 2154size=4194304 2155 2156[system.membus] 2157type=CoherentXBar 2158clk_domain=system.clk_domain 2159eventq_index=0 2160forward_latency=4 2161frontend_latency=3 2162response_latency=2 2163snoop_filter=Null 2164snoop_response_latency=4 2165system=system 2166use_default_range=false 2167width=16 2168master=system.physmem.port 2169slave=system.system_port system.l2c.mem_side 2170 2171[system.physmem] 2172type=DRAMCtrl 2173IDD0=0.075000 2174IDD02=0.000000 2175IDD2N=0.050000 2176IDD2N2=0.000000 2177IDD2P0=0.000000 2178IDD2P02=0.000000 2179IDD2P1=0.000000 2180IDD2P12=0.000000 2181IDD3N=0.057000 2182IDD3N2=0.000000 2183IDD3P0=0.000000 2184IDD3P02=0.000000 2185IDD3P1=0.000000 2186IDD3P12=0.000000 2187IDD4R=0.187000 2188IDD4R2=0.000000 2189IDD4W=0.165000 2190IDD4W2=0.000000 2191IDD5=0.220000 2192IDD52=0.000000 2193IDD6=0.000000 2194IDD62=0.000000 2195VDD=1.500000 2196VDD2=0.000000 2197activation_limit=4 2198addr_mapping=RoRaBaCoCh 2199bank_groups_per_rank=0 2200banks_per_rank=8 2201burst_length=8 2202channels=1 2203clk_domain=system.clk_domain 2204conf_table_reported=true 2205device_bus_width=8 2206device_rowbuffer_size=1024 2207device_size=536870912 2208devices_per_rank=8 2209dll=true 2210eventq_index=0 2211in_addr_map=true 2212max_accesses_per_row=16 2213mem_sched_policy=frfcfs 2214min_writes_per_switch=16 2215null=false 2216page_policy=open_adaptive 2217range=0:134217727 2218ranks_per_channel=2 2219read_buffer_size=32 2220static_backend_latency=10000 2221static_frontend_latency=10000 2222tBURST=5000 2223tCCD_L=0 2224tCK=1250 2225tCL=13750 2226tCS=2500 2227tRAS=35000 2228tRCD=13750 2229tREFI=7800000 2230tRFC=260000 2231tRP=13750 2232tRRD=6000 2233tRRD_L=0 2234tRTP=7500 2235tRTW=2500 2236tWR=15000 2237tWTR=7500 2238tXAW=30000 2239tXP=0 2240tXPDLL=0 2241tXS=0 2242tXSDLL=0 2243write_buffer_size=64 2244write_high_thresh_perc=85 2245write_low_thresh_perc=50 2246port=system.membus.master[0] 2247 2248[system.toL2Bus] 2249type=CoherentXBar 2250children=snoop_filter 2251clk_domain=system.cpu_clk_domain 2252eventq_index=0 2253forward_latency=0 2254frontend_latency=1 2255response_latency=1 2256snoop_filter=system.toL2Bus.snoop_filter 2257snoop_response_latency=1 2258system=system 2259use_default_range=false 2260width=32 2261master=system.l2c.cpu_side 2262slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side 2263 2264[system.toL2Bus.snoop_filter] 2265type=SnoopFilter 2266eventq_index=0 2267lookup_latency=0 2268max_capacity=8388608 2269system=system 2270 2271[system.voltage_domain] 2272type=VoltageDomain 2273eventq_index=0 2274voltage=1.000000 2275 2276