xref: /gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000469                       # Number of seconds simulated
sim_ticks                                   468854500                       # Number of ticks simulated
final_tick                                  468854500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  67943                       # Simulator instruction rate (inst/s)
host_op_rate                                   139717                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              475693968                       # Simulator tick rate (ticks/s)
host_mem_usage                                1301796                       # Number of bytes of host memory used
host_seconds                                     0.99                       # Real time elapsed on the host
sim_insts                                       66963                       # Number of instructions simulated
sim_ops                                        137705                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.mem_ctrls.bytes_read::dir_cntrl0        100032                       # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total             100032                       # Number of bytes read from this memory
system.mem_ctrls.num_reads::dir_cntrl0           1563                       # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total                1563                       # Number of read requests responded to by this memory
system.mem_ctrls.bw_read::dir_cntrl0        213354036                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total             213354036                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::dir_cntrl0       213354036                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total            213354036                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs                        1563                       # Number of read requests accepted
system.mem_ctrls.writeReqs                          0                       # Number of write requests accepted
system.mem_ctrls.readBursts                      1563                       # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts                        0                       # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM                 100032                       # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ                       0                       # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten                       0                       # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys                  100032                       # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys                    0                       # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ                      0                       # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts                     0                       # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0               122                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1               192                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2                93                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3                44                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4                61                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5                79                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6                52                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7                42                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8                54                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9                56                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10              183                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11               90                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12              225                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13              125                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14               51                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15               94                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
system.mem_ctrls.totGap                     468627000                       # Total gap between requests
system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::6                  1563                       # Read request sizes (log2)
system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::6                    0                       # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0                    1548                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1                       4                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2                       2                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3                       2                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4                       2                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5                       2                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6                       2                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7                       1                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples          450                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean    221.297778                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean   151.217299                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev   224.192300                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127          165     36.67%     36.67% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255          148     32.89%     69.56% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383           55     12.22%     81.78% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511           28      6.22%     88.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639           19      4.22%     92.22% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767           11      2.44%     94.67% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895            8      1.78%     96.44% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023            6      1.33%     97.78% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151           10      2.22%    100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total          450                       # Bytes accessed per row activation
system.mem_ctrls.totQLat                     14130749                       # Total ticks spent queuing
system.mem_ctrls.totMemAccLat                43436999                       # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat                    7815000                       # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat                      9040.79                       # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat                27790.79                       # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW                       213.35                       # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW                         0.00                       # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys                    213.35                       # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys                      0.00                       # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil                         1.67                       # Data bus utilization in percentage
system.mem_ctrls.busUtilRead                     1.67                       # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite                    0.00                       # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen                       1.01                       # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen                       0.00                       # Average write queue length when enqueuing
system.mem_ctrls.readRowHits                     1109                       # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits                       0                       # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate                 70.95                       # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate                  nan                       # Row buffer hit rate for writes
system.mem_ctrls.avgGap                     299825.34                       # Average gap between requests
system.mem_ctrls.pageHitRate                    70.95                       # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy                  1300320                       # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy                   709500                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy                 5335200                       # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy             30513600                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy            265391145                       # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy             47661750                       # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy              350911515                       # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower            750.717244                       # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE     79008000                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF      15600000                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT     374147000                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.mem_ctrls_1.actEnergy                  2101680                       # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy                  1146750                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy                 6801600                       # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy             30513600                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy            276170130                       # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy             38206500                       # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy              354940260                       # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower            759.336079                       # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE     61948750                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF      15600000                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT     389900000                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.ruby.clk_domain.clock                      500                       # Clock period in ticks
system.ruby.phys_mem.bytes_read::cpu0.inst       696760                       # Number of bytes read from this memory
system.ruby.phys_mem.bytes_read::cpu0.data       119832                       # Number of bytes read from this memory
system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit         3280                       # Number of bytes read from this memory
system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit         3280                       # Number of bytes read from this memory
system.ruby.phys_mem.bytes_read::total         823152                       # Number of bytes read from this memory
system.ruby.phys_mem.bytes_inst_read::cpu0.inst       696760                       # Number of instructions bytes read from this memory
system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit         2000                       # Number of instructions bytes read from this memory
system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit         2000                       # Number of instructions bytes read from this memory
system.ruby.phys_mem.bytes_inst_read::total       700760                       # Number of instructions bytes read from this memory
system.ruby.phys_mem.bytes_written::cpu0.data        72767                       # Number of bytes written to this memory
system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit          256                       # Number of bytes written to this memory
system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit          256                       # Number of bytes written to this memory
system.ruby.phys_mem.bytes_written::total        73279                       # Number of bytes written to this memory
system.ruby.phys_mem.num_reads::cpu0.inst        87095                       # Number of read requests responded to by this memory
system.ruby.phys_mem.num_reads::cpu0.data        16686                       # Number of read requests responded to by this memory
system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit          555                       # Number of read requests responded to by this memory
system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit          555                       # Number of read requests responded to by this memory
system.ruby.phys_mem.num_reads::total          104891                       # Number of read requests responded to by this memory
system.ruby.phys_mem.num_writes::cpu0.data        10422                       # Number of write requests responded to by this memory
system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit          256                       # Number of write requests responded to by this memory
system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit          256                       # Number of write requests responded to by this memory
system.ruby.phys_mem.num_writes::total          10934                       # Number of write requests responded to by this memory
system.ruby.phys_mem.bw_read::cpu0.inst    1486090034                       # Total read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_read::cpu0.data     255584622                       # Total read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit      6995774                       # Total read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit      6995774                       # Total read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_read::total        1755666203                       # Total read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_inst_read::cpu0.inst   1486090034                       # Instruction read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit      4265716                       # Instruction read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit      4265716                       # Instruction read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_inst_read::total   1494621466                       # Instruction read bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_write::cpu0.data    155201667                       # Write bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit       546012                       # Write bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit       546012                       # Write bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_write::total        156293690                       # Write bandwidth from this memory (bytes/s)
system.ruby.phys_mem.bw_total::cpu0.inst   1486090034                       # Total bandwidth to/from this memory (bytes/s)
system.ruby.phys_mem.bw_total::cpu0.data    410786289                       # Total bandwidth to/from this memory (bytes/s)
system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit      7541785                       # Total bandwidth to/from this memory (bytes/s)
system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit      7541785                       # Total bandwidth to/from this memory (bytes/s)
system.ruby.phys_mem.bw_total::total       1911959894                       # Total bandwidth to/from this memory (bytes/s)
system.ruby.outstanding_req_hist::bucket_size            1                      
system.ruby.outstanding_req_hist::max_bucket            9                      
system.ruby.outstanding_req_hist::samples       114203                      
system.ruby.outstanding_req_hist::mean       1.000035                      
system.ruby.outstanding_req_hist::gmean      1.000024                      
system.ruby.outstanding_req_hist::stdev      0.005918                      
system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |      114199    100.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.outstanding_req_hist::total        114203                      
system.ruby.latency_hist::bucket_size              64                      
system.ruby.latency_hist::max_bucket              639                      
system.ruby.latency_hist::samples              114203                      
system.ruby.latency_hist::mean               3.070988                      
system.ruby.latency_hist::gmean              1.072272                      
system.ruby.latency_hist::stdev             18.192328                      
system.ruby.latency_hist                 |      112654     98.64%     98.64% |          11      0.01%     98.65% |        1238      1.08%     99.74% |         266      0.23%     99.97% |          14      0.01%     99.98% |          12      0.01%     99.99% |           7      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.latency_hist::total                114203                      
system.ruby.hit_latency_hist::bucket_size           64                      
system.ruby.hit_latency_hist::max_bucket          639                      
system.ruby.hit_latency_hist::samples            1549                      
system.ruby.hit_latency_hist::mean         152.827631                      
system.ruby.hit_latency_hist::gmean        149.009432                      
system.ruby.hit_latency_hist::stdev         40.628532                      
system.ruby.hit_latency_hist             |           0      0.00%      0.00% |          11      0.71%      0.71% |        1238     79.92%     80.63% |         266     17.17%     97.81% |          14      0.90%     98.71% |          12      0.77%     99.48% |           7      0.45%     99.94% |           1      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.hit_latency_hist::total              1549                      
system.ruby.miss_latency_hist::bucket_size            2                      
system.ruby.miss_latency_hist::max_bucket           19                      
system.ruby.miss_latency_hist::samples         112654                      
system.ruby.miss_latency_hist::mean          1.011824                      
system.ruby.miss_latency_hist::gmean         1.001936                      
system.ruby.miss_latency_hist::stdev         0.461184                      
system.ruby.miss_latency_hist            |      112580     99.93%     99.93% |           0      0.00%     99.93% |           0      0.00%     99.93% |           0      0.00%     99.93% |           0      0.00%     99.93% |           0      0.00%     99.93% |           0      0.00%     99.93% |           0      0.00%     99.93% |           0      0.00%     99.93% |          74      0.07%    100.00%
system.ruby.miss_latency_hist::total           112654                      
system.ruby.L1Cache.incomplete_times           112580                      
system.ruby.L2Cache.incomplete_times               74                      
system.cp_cntrl0.L1D0cache.demand_hits              0                       # Number of cache demand hits
system.cp_cntrl0.L1D0cache.demand_misses         1556                       # Number of cache demand misses
system.cp_cntrl0.L1D0cache.demand_accesses         1556                       # Number of cache demand accesses
system.cp_cntrl0.L1D0cache.num_data_array_reads        16142                       # number of data array reads
system.cp_cntrl0.L1D0cache.num_data_array_writes        11998                       # number of data array writes
system.cp_cntrl0.L1D0cache.num_tag_array_reads        27136                       # number of tag array reads
system.cp_cntrl0.L1D0cache.num_tag_array_writes         1431                       # number of tag array writes
system.cp_cntrl0.L1D1cache.demand_hits              0                       # Number of cache demand hits
system.cp_cntrl0.L1D1cache.demand_misses            0                       # Number of cache demand misses
system.cp_cntrl0.L1D1cache.demand_accesses            0                       # Number of cache demand accesses
system.cp_cntrl0.L1Icache.demand_hits               0                       # Number of cache demand hits
system.cp_cntrl0.L1Icache.demand_misses          1287                       # Number of cache demand misses
system.cp_cntrl0.L1Icache.demand_accesses         1287                       # Number of cache demand accesses
system.cp_cntrl0.L1Icache.num_data_array_reads        85994                       # number of data array reads
system.cp_cntrl0.L1Icache.num_data_array_writes           67                       # number of data array writes
system.cp_cntrl0.L1Icache.num_tag_array_reads        87697                       # number of tag array reads
system.cp_cntrl0.L1Icache.num_tag_array_writes           67                       # number of tag array writes
system.cp_cntrl0.L2cache.demand_hits                0                       # Number of cache demand hits
system.cp_cntrl0.L2cache.demand_misses           1549                       # Number of cache demand misses
system.cp_cntrl0.L2cache.demand_accesses         1549                       # Number of cache demand accesses
system.cp_cntrl0.L2cache.num_data_array_reads          167                       # number of data array reads
system.cp_cntrl0.L2cache.num_data_array_writes        11993                       # number of data array writes
system.cp_cntrl0.L2cache.num_tag_array_reads        12092                       # number of tag array reads
system.cp_cntrl0.L2cache.num_tag_array_writes         1694                       # number of tag array writes
system.cpu0.clk_domain.clock                      500                       # Clock period in ticks
system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
system.cpu0.workload.numSyscalls                   21                       # Number of system calls
system.cpu0.numCycles                          937709                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                      66963                       # Number of instructions committed
system.cpu0.committedOps                       137705                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses               136380                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  1279                       # Number of float alu accesses
system.cpu0.num_func_calls                       3196                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts        12151                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                      136380                       # number of integer instructions
system.cpu0.num_fp_insts                         1279                       # number of float instructions
system.cpu0.num_int_register_reads             257490                       # number of times the integer registers were read
system.cpu0.num_int_register_writes            110039                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                1981                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                981                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads               78262                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes              42183                       # number of times the CC registers were written
system.cpu0.num_mem_refs                        27198                       # number of memory refs
system.cpu0.num_load_insts                      16684                       # Number of load instructions
system.cpu0.num_store_insts                     10514                       # Number of store instructions
system.cpu0.num_idle_cycles               7323.003984                       # Number of idle cycles
system.cpu0.num_busy_cycles              930385.996016                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.992191                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.007809                       # Percentage of idle cycles
system.cpu0.Branches                            16199                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                  615      0.45%      0.45% # Class of executed instruction
system.cpu0.op_class::IntAlu                   108791     79.00%     79.45% # Class of executed instruction
system.cpu0.op_class::IntMult                      13      0.01%     79.46% # Class of executed instruction
system.cpu0.op_class::IntDiv                      138      0.10%     79.56% # Class of executed instruction
system.cpu0.op_class::FloatAdd                    950      0.69%     80.25% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     80.25% # Class of executed instruction
system.cpu0.op_class::MemRead                   16684     12.12%     92.36% # Class of executed instruction
system.cpu0.op_class::MemWrite                  10514      7.64%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                    137705                       # Class of executed instruction
system.cpu1.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.cpu1.clk_domain.clock                     1000                       # Clock period in ticks
system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies          271                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples           39                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean     0.794872                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev     0.863880                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1           28     71.79%     71.79% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3           11     28.21%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total           39                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples           39                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean     0.589744                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev     0.498310                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1           39    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total           39                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies          252                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1           24     70.59%     70.59% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3           10     29.41%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total           34                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean     0.617647                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev     0.493270                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1           34    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies          243                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1           24     70.59%     70.59% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3           10     29.41%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total           34                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean     0.617647                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev     0.493270                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1           34    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies          228                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1           24     70.59%     70.59% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3           10     29.41%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total           34                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean     0.617647                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev     0.493270                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1           34    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples           43                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean     5.813953                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev     2.683777                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows            0      0.00%      0.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1            0      0.00%      0.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2            8     18.60%     18.60% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3            8     18.60%     37.21% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4            1      2.33%     39.53% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5            0      0.00%     39.53% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6            1      2.33%     41.86% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7            0      0.00%     41.86% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8           25     58.14%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value            2                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value            8                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total           43                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue         4103                       # number of cycles the CU issues nothing
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued          133                       # number of cycles the CU issued at least one instruction
system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0           30                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1           29                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2           29                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3           29                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM           18                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM            6                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0         1359                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1          382                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2          338                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3          302                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM          373                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM           26                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs0.ExecStage.spc::samples          4236                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::mean         0.033286                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::stdev        0.190882                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::underflows            0      0.00%      0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::0                4103     96.86%     96.86% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::1                 126      2.97%     99.83% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::2                   6      0.14%     99.98% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::3                   1      0.02%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::4                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::5                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::6                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::overflows            0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::min_value            0                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::max_value            3                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.spc::total            4236                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle           68                       # number of CU transitions from active to idle
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples           68                       # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean    53.455882                       # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev   203.558231                       # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows            0      0.00%      0.00% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4           48     70.59%     70.59% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9            8     11.76%     82.35% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14            1      1.47%     83.82% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19            1      1.47%     85.29% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24            2      2.94%     88.24% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29            1      1.47%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75            0      0.00%     89.71% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows            7     10.29%    100.00% # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value            1                       # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value         1317                       # duration of idle periods in cycles
system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total           68                       # duration of idle periods in cycles
system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles            0                       # total number of cycles GM data are delayed before updating the VRF
system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles            0                       # total number of cycles LDS data are delayed before updating the VRF
system.cpu1.CUs0.tlb_requests                     769                       # number of uncoalesced requests
system.cpu1.CUs0.tlb_cycles              -318202403000                       # total number of cycles for all uncoalesced requests
system.cpu1.CUs0.avg_translation_latency -413787260.078023                       # Avg. translation latency for data translations
system.cpu1.CUs0.TLB_hits_distribution::page_table          769                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs0.TLB_hits_distribution::L1_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs0.TLB_hits_distribution::L2_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs0.TLB_hits_distribution::L3_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs0.lds_bank_access_cnt               54                       # Total number of LDS bank accesses
system.cpu1.CUs0.lds_bank_conflicts::samples            6                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::mean            8                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::stdev     6.196773                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::underflows            0      0.00%      0.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::0-1            2     33.33%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::2-3            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::4-5            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::6-7            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::8-9            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::10-11            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::12-13            4     66.67%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::14-15            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::16-17            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::18-19            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::20-21            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::22-23            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::24-25            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::26-27            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::28-29            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::30-31            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::32-33            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::34-35            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::36-37            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::38-39            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::40-41            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::42-43            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::44-45            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::46-47            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::48-49            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::50-51            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::52-53            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::54-55            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::56-57            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::58-59            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::60-61            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::62-63            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::64             0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::overflows            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::min_value            0                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::max_value           12                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.lds_bank_conflicts::total            6                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs0.page_divergence_dist::samples           17                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::mean            1                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::stdev            0                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::underflows            0      0.00%      0.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::1-4           17    100.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::5-8            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::9-12            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::13-16            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::17-20            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::21-24            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::25-28            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::29-32            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::33-36            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::37-40            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::41-44            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::45-48            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::49-52            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::53-56            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::57-60            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::61-64            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::overflows            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::min_value            1                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::max_value            1                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.page_divergence_dist::total           17                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs0.global_mem_instr_cnt              17                       # dynamic global memory instructions count
system.cpu1.CUs0.local_mem_instr_cnt                6                       # dynamic local memory intruction count
system.cpu1.CUs0.wg_blocked_due_lds_alloc            0                       # Workgroup blocked due to LDS capacity
system.cpu1.CUs0.num_instr_executed               141                       # number of instructions executed
system.cpu1.CUs0.inst_exec_rate::samples          141                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::mean       84.978723                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::stdev     240.114362                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::underflows            0      0.00%      0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::0-1                1      0.71%      0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::2-3               12      8.51%      9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::4-5               53     37.59%     46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::6-7               31     21.99%     68.79% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::8-9                3      2.13%     70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::10                 1      0.71%     71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::overflows           40     28.37%    100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::min_value            1                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::max_value         1320                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.inst_exec_rate::total            141                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs0.num_vec_ops_executed            6769                       # number of vec ops executed (e.g. VSZ/inst)
system.cpu1.CUs0.num_total_cycles                4236                       # number of cycles the CU ran for
system.cpu1.CUs0.vpc                         1.597970                       # Vector Operations per cycle (this CU only)
system.cpu1.CUs0.ipc                         0.033286                       # Instructions per cycle (this CU only)
system.cpu1.CUs0.warp_execution_dist::samples          141                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::mean    48.007092                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::stdev    23.719942                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::underflows            0      0.00%      0.00% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::1-4            5      3.55%      3.55% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::5-8            0      0.00%      3.55% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::9-12            0      0.00%      3.55% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::13-16           36     25.53%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::17-20            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::21-24            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::25-28            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::29-32            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::33-36            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::37-40            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::41-44            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::45-48            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::49-52            8      5.67%     34.75% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::53-56            0      0.00%     34.75% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::57-60            0      0.00%     34.75% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::61-64           92     65.25%    100.00% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::overflows            0      0.00%    100.00% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::min_value            1                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::max_value           64                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.warp_execution_dist::total          141                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs0.gmem_lanes_execution_dist::samples           18                       # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::mean    37.833333                       # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::stdev    27.064737                       # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::underflows            0      0.00%      0.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::1-4            1      5.56%      5.56% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::5-8            0      0.00%      5.56% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::9-12            0      0.00%      5.56% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::13-16            8     44.44%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::17-20            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::21-24            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::25-28            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::29-32            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::33-36            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::37-40            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::41-44            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::45-48            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::49-52            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::53-56            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::57-60            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::61-64            9     50.00%    100.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::overflows            0      0.00%    100.00% # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::min_value            1                       # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::max_value           64                       # number of active lanes per global memory instruction
system.cpu1.CUs0.gmem_lanes_execution_dist::total           18                       # number of active lanes per global memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::samples            6                       # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::mean    19.500000                       # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::stdev    22.322634                       # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::underflows            0      0.00%      0.00% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::1-4            1     16.67%     16.67% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::5-8            0      0.00%     16.67% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::9-12            0      0.00%     16.67% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::13-16            4     66.67%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::17-20            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::21-24            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::25-28            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::29-32            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::33-36            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::37-40            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::41-44            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::45-48            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::49-52            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::53-56            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::57-60            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::61-64            1     16.67%    100.00% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::overflows            0      0.00%    100.00% # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::min_value            1                       # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::max_value           64                       # number of active lanes per local memory instruction
system.cpu1.CUs0.lmem_lanes_execution_dist::total            6                       # number of active lanes per local memory instruction
system.cpu1.CUs0.num_alu_insts_executed           118                       # Number of dynamic non-GM memory insts executed
system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc            0                       # Number of times WGs are blocked due to VGPR allocation per SIMD
system.cpu1.CUs0.num_CAS_ops                        0                       # number of compare and swap operations
system.cpu1.CUs0.num_failed_CAS_ops                 0                       # number of compare and swap operations that failed
system.cpu1.CUs0.num_completed_wfs                  4                       # number of completed wavefronts
system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies          276                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples           39                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean     0.794872                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev     0.863880                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1           28     71.79%     71.79% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3           11     28.21%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total           39                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples           39                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean     0.589744                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev     0.498310                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1           39    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total           39                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies          254                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1           24     70.59%     70.59% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3           10     29.41%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total           34                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean     0.617647                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev     0.493270                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1           34    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies          251                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1           24     70.59%     70.59% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3           10     29.41%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total           34                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean     0.617647                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev     0.493270                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1           34    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies          236                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples           34                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean     0.852941                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev     0.857493                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1           24     70.59%     70.59% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3           10     29.41%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value            2                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total           34                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean     0.617647                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev     0.493270                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows            0      0.00%      0.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1           34    100.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows            0      0.00%    100.00% # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value            1                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total           34                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail            0                       # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies            0                       # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies            0                       # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev          nan                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total            0                       # number of executed instructions with N source register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev          nan                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total            0                       # number of executed instructions with N destination register operands
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples           43                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean     5.813953                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev     2.683777                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows            0      0.00%      0.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1            0      0.00%      0.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2            8     18.60%     18.60% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3            8     18.60%     37.21% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4            1      2.33%     39.53% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5            0      0.00%     39.53% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6            1      2.33%     41.86% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7            0      0.00%     41.86% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8           25     58.14%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows            0      0.00%    100.00% # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value            2                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value            8                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total           43                       # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue         4105                       # number of cycles the CU issues nothing
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued          131                       # number of cycles the CU issued at least one instruction
system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0           30                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1           29                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2           29                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3           29                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM           18                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM            6                       # Number of cycles at least one instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0         1525                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1          346                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2          363                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3          363                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM          363                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM           33                       # Number of cycles no instruction of specific type issued
system.cpu1.CUs1.ExecStage.spc::samples          4236                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::mean         0.033286                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::stdev        0.194558                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::underflows            0      0.00%      0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::0                4105     96.91%     96.91% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::1                 123      2.90%     99.81% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::2                   6      0.14%     99.95% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::3                   2      0.05%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::4                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::5                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::6                   0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::overflows            0      0.00%    100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::min_value            0                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::max_value            3                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.spc::total            4236                       # Execution units active per cycle (Exec unit=SIMD,MemPipe)
system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle           74                       # number of CU transitions from active to idle
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples           74                       # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean    51.891892                       # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev   210.095188                       # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows            0      0.00%      0.00% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4           56     75.68%     75.68% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9            7      9.46%     85.14% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14            0      0.00%     85.14% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19            2      2.70%     87.84% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24            1      1.35%     89.19% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29            1      1.35%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75            0      0.00%     90.54% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows            7      9.46%    100.00% # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value            1                       # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value         1321                       # duration of idle periods in cycles
system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total           74                       # duration of idle periods in cycles
system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles            0                       # total number of cycles GM data are delayed before updating the VRF
system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles            0                       # total number of cycles LDS data are delayed before updating the VRF
system.cpu1.CUs1.tlb_requests                     769                       # number of uncoalesced requests
system.cpu1.CUs1.tlb_cycles              -318199598000                       # total number of cycles for all uncoalesced requests
system.cpu1.CUs1.avg_translation_latency -413783612.483745                       # Avg. translation latency for data translations
system.cpu1.CUs1.TLB_hits_distribution::page_table          769                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs1.TLB_hits_distribution::L1_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs1.TLB_hits_distribution::L2_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs1.TLB_hits_distribution::L3_TLB            0                       # TLB hits distribution (0 for page table, x for Lx-TLB
system.cpu1.CUs1.lds_bank_access_cnt               53                       # Total number of LDS bank accesses
system.cpu1.CUs1.lds_bank_conflicts::samples            6                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::mean     7.833333                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::stdev     6.080022                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::underflows            0      0.00%      0.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::0-1            2     33.33%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::2-3            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::4-5            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::6-7            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::8-9            0      0.00%     33.33% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::10-11            1     16.67%     50.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::12-13            3     50.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::14-15            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::16-17            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::18-19            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::20-21            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::22-23            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::24-25            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::26-27            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::28-29            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::30-31            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::32-33            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::34-35            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::36-37            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::38-39            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::40-41            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::42-43            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::44-45            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::46-47            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::48-49            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::50-51            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::52-53            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::54-55            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::56-57            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::58-59            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::60-61            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::62-63            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::64             0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::overflows            0      0.00%    100.00% # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::min_value            0                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::max_value           12                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.lds_bank_conflicts::total            6                       # Number of bank conflicts per LDS memory packet
system.cpu1.CUs1.page_divergence_dist::samples           17                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::mean            1                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::stdev            0                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::underflows            0      0.00%      0.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::1-4           17    100.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::5-8            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::9-12            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::13-16            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::17-20            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::21-24            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::25-28            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::29-32            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::33-36            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::37-40            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::41-44            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::45-48            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::49-52            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::53-56            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::57-60            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::61-64            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::overflows            0      0.00%    100.00% # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::min_value            1                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::max_value            1                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.page_divergence_dist::total           17                       # pages touched per wf (over all mem. instr.)
system.cpu1.CUs1.global_mem_instr_cnt              17                       # dynamic global memory instructions count
system.cpu1.CUs1.local_mem_instr_cnt                6                       # dynamic local memory intruction count
system.cpu1.CUs1.wg_blocked_due_lds_alloc            0                       # Workgroup blocked due to LDS capacity
system.cpu1.CUs1.num_instr_executed               141                       # number of instructions executed
system.cpu1.CUs1.inst_exec_rate::samples          141                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::mean       86.326241                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::stdev     246.713874                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::underflows            0      0.00%      0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::0-1                1      0.71%      0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::2-3               12      8.51%      9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::4-5               53     37.59%     46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::6-7               29     20.57%     67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::8-9                5      3.55%     70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::10                 1      0.71%     71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::overflows           40     28.37%    100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::min_value            1                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::max_value         1324                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.inst_exec_rate::total            141                       # Instruction Execution Rate: Number of executed vector instructions per cycle
system.cpu1.CUs1.num_vec_ops_executed            6762                       # number of vec ops executed (e.g. VSZ/inst)
system.cpu1.CUs1.num_total_cycles                4236                       # number of cycles the CU ran for
system.cpu1.CUs1.vpc                         1.596317                       # Vector Operations per cycle (this CU only)
system.cpu1.CUs1.ipc                         0.033286                       # Instructions per cycle (this CU only)
system.cpu1.CUs1.warp_execution_dist::samples          141                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::mean    47.957447                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::stdev    23.818022                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::underflows            0      0.00%      0.00% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::1-4            5      3.55%      3.55% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::5-8            0      0.00%      3.55% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::9-12            9      6.38%      9.93% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::13-16           27     19.15%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::17-20            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::21-24            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::25-28            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::29-32            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::33-36            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::37-40            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::41-44            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::45-48            0      0.00%     29.08% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::49-52            8      5.67%     34.75% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::53-56            0      0.00%     34.75% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::57-60            0      0.00%     34.75% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::61-64           92     65.25%    100.00% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::overflows            0      0.00%    100.00% # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::min_value            1                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::max_value           64                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.warp_execution_dist::total          141                       # number of lanes active per instruction (oval all instructions)
system.cpu1.CUs1.gmem_lanes_execution_dist::samples           18                       # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::mean    37.722222                       # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::stdev    27.174394                       # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::underflows            0      0.00%      0.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::1-4            1      5.56%      5.56% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::5-8            0      0.00%      5.56% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::9-12            2     11.11%     16.67% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::13-16            6     33.33%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::17-20            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::21-24            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::25-28            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::29-32            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::33-36            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::37-40            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::41-44            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::45-48            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::49-52            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::53-56            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::57-60            0      0.00%     50.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::61-64            9     50.00%    100.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::overflows            0      0.00%    100.00% # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::min_value            1                       # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::max_value           64                       # number of active lanes per global memory instruction
system.cpu1.CUs1.gmem_lanes_execution_dist::total           18                       # number of active lanes per global memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::samples            6                       # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::mean    19.333333                       # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::stdev    22.384518                       # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::underflows            0      0.00%      0.00% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::1-4            1     16.67%     16.67% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::5-8            0      0.00%     16.67% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::9-12            1     16.67%     33.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::13-16            3     50.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::17-20            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::21-24            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::25-28            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::29-32            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::33-36            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::37-40            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::41-44            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::45-48            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::49-52            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::53-56            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::57-60            0      0.00%     83.33% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::61-64            1     16.67%    100.00% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::overflows            0      0.00%    100.00% # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::min_value            1                       # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::max_value           64                       # number of active lanes per local memory instruction
system.cpu1.CUs1.lmem_lanes_execution_dist::total            6                       # number of active lanes per local memory instruction
system.cpu1.CUs1.num_alu_insts_executed           118                       # Number of dynamic non-GM memory insts executed
system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc            0                       # Number of times WGs are blocked due to VGPR allocation per SIMD
system.cpu1.CUs1.num_CAS_ops                        0                       # number of compare and swap operations
system.cpu1.CUs1.num_failed_CAS_ops                 0                       # number of compare and swap operations that failed
system.cpu1.CUs1.num_completed_wfs                  4                       # number of completed wavefronts
system.cpu2.num_kernel_launched                     1                       # number of kernel launched
system.dir_cntrl0.L3CacheMemory.demand_hits            0                       # Number of cache demand hits
system.dir_cntrl0.L3CacheMemory.demand_misses            0                       # Number of cache demand misses
system.dir_cntrl0.L3CacheMemory.demand_accesses            0                       # Number of cache demand accesses
system.dir_cntrl0.L3CacheMemory.num_data_array_writes         1600                       # number of data array writes
system.dir_cntrl0.L3CacheMemory.num_tag_array_reads         1602                       # number of tag array reads
system.dir_cntrl0.L3CacheMemory.num_tag_array_writes         1572                       # number of tag array writes
system.dispatcher_coalescer.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.dispatcher_coalescer.clk_domain.clock         1000                       # Clock period in ticks
system.dispatcher_coalescer.uncoalesced_accesses            0                       # Number of uncoalesced TLB accesses
system.dispatcher_coalescer.coalesced_accesses            0                       # Number of coalesced TLB accesses
system.dispatcher_coalescer.queuing_cycles            0                       # Number of cycles spent in queue
system.dispatcher_coalescer.local_queuing_cycles            0                       # Number of cycles spent in queue for all incoming reqs
system.dispatcher_coalescer.local_latency          nan                       # Avg. latency over all incoming pkts
system.dispatcher_tlb.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.dispatcher_tlb.clk_domain.clock           1000                       # Clock period in ticks
system.dispatcher_tlb.local_TLB_accesses            0                       # Number of TLB accesses
system.dispatcher_tlb.local_TLB_hits                0                       # Number of TLB hits
system.dispatcher_tlb.local_TLB_misses              0                       # Number of TLB misses
system.dispatcher_tlb.local_TLB_miss_rate          nan                       # TLB miss rate
system.dispatcher_tlb.global_TLB_accesses            0                       # Number of TLB accesses
system.dispatcher_tlb.global_TLB_hits               0                       # Number of TLB hits
system.dispatcher_tlb.global_TLB_misses             0                       # Number of TLB misses
system.dispatcher_tlb.global_TLB_miss_rate          nan                       # TLB miss rate
system.dispatcher_tlb.access_cycles                 0                       # Cycles spent accessing this TLB level
system.dispatcher_tlb.page_table_cycles             0                       # Cycles spent accessing the page table
system.dispatcher_tlb.unique_pages                  0                       # Number of unique pages touched
system.dispatcher_tlb.local_cycles                  0                       # Number of cycles spent in queue for all incoming reqs
system.dispatcher_tlb.local_latency               nan                       # Avg. latency over incoming coalesced reqs
system.dispatcher_tlb.avg_reuse_distance            0                       # avg. reuse distance over all pages (in ticks)
system.l1_coalescer0.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l1_coalescer0.clk_domain.clock            1000                       # Clock period in ticks
system.l1_coalescer0.uncoalesced_accesses          778                       # Number of uncoalesced TLB accesses
system.l1_coalescer0.coalesced_accesses             0                       # Number of coalesced TLB accesses
system.l1_coalescer0.queuing_cycles                 0                       # Number of cycles spent in queue
system.l1_coalescer0.local_queuing_cycles            0                       # Number of cycles spent in queue for all incoming reqs
system.l1_coalescer0.local_latency                  0                       # Avg. latency over all incoming pkts
system.l1_coalescer1.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l1_coalescer1.clk_domain.clock            1000                       # Clock period in ticks
system.l1_coalescer1.uncoalesced_accesses          769                       # Number of uncoalesced TLB accesses
system.l1_coalescer1.coalesced_accesses             0                       # Number of coalesced TLB accesses
system.l1_coalescer1.queuing_cycles                 0                       # Number of cycles spent in queue
system.l1_coalescer1.local_queuing_cycles            0                       # Number of cycles spent in queue for all incoming reqs
system.l1_coalescer1.local_latency                  0                       # Avg. latency over all incoming pkts
system.l1_tlb0.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l1_tlb0.clk_domain.clock                  1000                       # Clock period in ticks
system.l1_tlb0.local_TLB_accesses                 778                       # Number of TLB accesses
system.l1_tlb0.local_TLB_hits                     774                       # Number of TLB hits
system.l1_tlb0.local_TLB_misses                     4                       # Number of TLB misses
system.l1_tlb0.local_TLB_miss_rate           0.514139                       # TLB miss rate
system.l1_tlb0.global_TLB_accesses                778                       # Number of TLB accesses
system.l1_tlb0.global_TLB_hits                    774                       # Number of TLB hits
system.l1_tlb0.global_TLB_misses                    4                       # Number of TLB misses
system.l1_tlb0.global_TLB_miss_rate          0.514139                       # TLB miss rate
system.l1_tlb0.access_cycles                        0                       # Cycles spent accessing this TLB level
system.l1_tlb0.page_table_cycles                    0                       # Cycles spent accessing the page table
system.l1_tlb0.unique_pages                         4                       # Number of unique pages touched
system.l1_tlb0.local_cycles                         0                       # Number of cycles spent in queue for all incoming reqs
system.l1_tlb0.local_latency                        0                       # Avg. latency over incoming coalesced reqs
system.l1_tlb0.avg_reuse_distance                   0                       # avg. reuse distance over all pages (in ticks)
system.l1_tlb1.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l1_tlb1.clk_domain.clock                  1000                       # Clock period in ticks
system.l1_tlb1.local_TLB_accesses                 769                       # Number of TLB accesses
system.l1_tlb1.local_TLB_hits                     766                       # Number of TLB hits
system.l1_tlb1.local_TLB_misses                     3                       # Number of TLB misses
system.l1_tlb1.local_TLB_miss_rate           0.390117                       # TLB miss rate
system.l1_tlb1.global_TLB_accesses                769                       # Number of TLB accesses
system.l1_tlb1.global_TLB_hits                    766                       # Number of TLB hits
system.l1_tlb1.global_TLB_misses                    3                       # Number of TLB misses
system.l1_tlb1.global_TLB_miss_rate          0.390117                       # TLB miss rate
system.l1_tlb1.access_cycles                        0                       # Cycles spent accessing this TLB level
system.l1_tlb1.page_table_cycles                    0                       # Cycles spent accessing the page table
system.l1_tlb1.unique_pages                         3                       # Number of unique pages touched
system.l1_tlb1.local_cycles                         0                       # Number of cycles spent in queue for all incoming reqs
system.l1_tlb1.local_latency                        0                       # Avg. latency over incoming coalesced reqs
system.l1_tlb1.avg_reuse_distance                   0                       # avg. reuse distance over all pages (in ticks)
system.l2_coalescer.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l2_coalescer.clk_domain.clock             1000                       # Clock period in ticks
system.l2_coalescer.uncoalesced_accesses            8                       # Number of uncoalesced TLB accesses
system.l2_coalescer.coalesced_accesses              1                       # Number of coalesced TLB accesses
system.l2_coalescer.queuing_cycles               8000                       # Number of cycles spent in queue
system.l2_coalescer.local_queuing_cycles         1000                       # Number of cycles spent in queue for all incoming reqs
system.l2_coalescer.local_latency                 125                       # Avg. latency over all incoming pkts
system.l2_tlb.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l2_tlb.clk_domain.clock                   1000                       # Clock period in ticks
system.l2_tlb.local_TLB_accesses                    8                       # Number of TLB accesses
system.l2_tlb.local_TLB_hits                        3                       # Number of TLB hits
system.l2_tlb.local_TLB_misses                      5                       # Number of TLB misses
system.l2_tlb.local_TLB_miss_rate           62.500000                       # TLB miss rate
system.l2_tlb.global_TLB_accesses                  15                       # Number of TLB accesses
system.l2_tlb.global_TLB_hits                       3                       # Number of TLB hits
system.l2_tlb.global_TLB_misses                    12                       # Number of TLB misses
system.l2_tlb.global_TLB_miss_rate                 80                       # TLB miss rate
system.l2_tlb.access_cycles                    552008                       # Cycles spent accessing this TLB level
system.l2_tlb.page_table_cycles                     0                       # Cycles spent accessing the page table
system.l2_tlb.unique_pages                          5                       # Number of unique pages touched
system.l2_tlb.local_cycles                      69001                       # Number of cycles spent in queue for all incoming reqs
system.l2_tlb.local_latency               8625.125000                       # Avg. latency over incoming coalesced reqs
system.l2_tlb.avg_reuse_distance                    0                       # avg. reuse distance over all pages (in ticks)
system.l3_coalescer.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l3_coalescer.clk_domain.clock             1000                       # Clock period in ticks
system.l3_coalescer.uncoalesced_accesses            5                       # Number of uncoalesced TLB accesses
system.l3_coalescer.coalesced_accesses              1                       # Number of coalesced TLB accesses
system.l3_coalescer.queuing_cycles               8000                       # Number of cycles spent in queue
system.l3_coalescer.local_queuing_cycles         1000                       # Number of cycles spent in queue for all incoming reqs
system.l3_coalescer.local_latency                 200                       # Avg. latency over all incoming pkts
system.l3_tlb.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.l3_tlb.clk_domain.clock                   1000                       # Clock period in ticks
system.l3_tlb.local_TLB_accesses                    5                       # Number of TLB accesses
system.l3_tlb.local_TLB_hits                        0                       # Number of TLB hits
system.l3_tlb.local_TLB_misses                      5                       # Number of TLB misses
system.l3_tlb.local_TLB_miss_rate                 100                       # TLB miss rate
system.l3_tlb.global_TLB_accesses                  12                       # Number of TLB accesses
system.l3_tlb.global_TLB_hits                       0                       # Number of TLB hits
system.l3_tlb.global_TLB_misses                    12                       # Number of TLB misses
system.l3_tlb.global_TLB_miss_rate                100                       # TLB miss rate
system.l3_tlb.access_cycles                   1200000                       # Cycles spent accessing this TLB level
system.l3_tlb.page_table_cycles               6000000                       # Cycles spent accessing the page table
system.l3_tlb.unique_pages                          5                       # Number of unique pages touched
system.l3_tlb.local_cycles                     150000                       # Number of cycles spent in queue for all incoming reqs
system.l3_tlb.local_latency                     30000                       # Avg. latency over incoming coalesced reqs
system.l3_tlb.avg_reuse_distance                    0                       # avg. reuse distance over all pages (in ticks)
system.piobus.trans_dist::WriteReq                 94                       # Transaction distribution
system.piobus.trans_dist::WriteResp                94                       # Transaction distribution
system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio          188                       # Packet count per connected master and slave (bytes)
system.piobus.pkt_count::total                    188                       # Packet count per connected master and slave (bytes)
system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio          748                       # Cumulative packet size per connected master and slave (bytes)
system.piobus.pkt_size::total                     748                       # Cumulative packet size per connected master and slave (bytes)
system.piobus.reqLayer0.occupancy              188000                       # Layer occupancy (ticks)
system.piobus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.piobus.respLayer0.occupancy              94000                       # Layer occupancy (ticks)
system.piobus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.rb_cntrl0.cacheMemory.demand_hits            0                       # Number of cache demand hits
system.rb_cntrl0.cacheMemory.demand_misses            0                       # Number of cache demand misses
system.rb_cntrl0.cacheMemory.demand_accesses            0                       # Number of cache demand accesses
system.rb_cntrl0.cacheMemory.num_tag_array_reads         1553                       # number of tag array reads
system.rb_cntrl0.cacheMemory.num_tag_array_writes         3123                       # number of tag array writes
system.reg_cntrl0.cacheMemory.demand_hits            0                       # Number of cache demand hits
system.reg_cntrl0.cacheMemory.demand_misses            0                       # Number of cache demand misses
system.reg_cntrl0.cacheMemory.demand_accesses            0                       # Number of cache demand accesses
system.reg_cntrl0.cacheMemory.num_tag_array_reads          279                       # number of tag array reads
system.reg_cntrl0.cacheMemory.num_tag_array_writes          279                       # number of tag array writes
system.ruby.network.ext_links0.int_node.percent_links_utilized     0.122493                      
system.ruby.network.ext_links0.int_node.msg_count.Data::0           16                      
system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0         1558                      
system.ruby.network.ext_links0.int_node.msg_count.Request_Control::5          279                      
system.ruby.network.ext_links0.int_node.msg_count.Request_Control::7          279                      
system.ruby.network.ext_links0.int_node.msg_count.Request_Control::8            8                      
system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2         1577                      
system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2          303                      
system.ruby.network.ext_links0.int_node.msg_count.Response_Control::4           34                      
system.ruby.network.ext_links0.int_node.msg_count.Writeback_Control::2           24                      
system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4         1556                      
system.ruby.network.ext_links0.int_node.msg_bytes.Data::0         1152                      
system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0        12464                      
system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::5         2232                      
system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::7         2232                      
system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::8           64                      
system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2       113544                      
system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2         2424                      
system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::4          272                      
system.ruby.network.ext_links0.int_node.msg_bytes.Writeback_Control::2          192                      
system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4        12448                      
system.ruby.network.ext_links2.int_node.percent_links_utilized     0.185852                      
system.ruby.network.ext_links2.int_node.msg_count.Control::0           23                      
system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0         3098                      
system.ruby.network.ext_links2.int_node.msg_count.Request_Control::7          274                      
system.ruby.network.ext_links2.int_node.msg_count.Request_Control::8            4                      
system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2         1568                      
system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2          281                      
system.ruby.network.ext_links2.int_node.msg_count.Response_Control::4           23                      
system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4         3098                      
system.ruby.network.ext_links2.int_node.msg_bytes.Control::0          184                      
system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0        24784                      
system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::7         2192                      
system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::8           32                      
system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2       112896                      
system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2         2248                      
system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::4          184                      
system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4        24784                      
system.tcp_cntrl0.L1cache.demand_hits               0                       # Number of cache demand hits
system.tcp_cntrl0.L1cache.demand_misses             0                       # Number of cache demand misses
system.tcp_cntrl0.L1cache.demand_accesses            0                       # Number of cache demand accesses
system.tcp_cntrl0.L1cache.num_data_array_reads            6                       # number of data array reads
system.tcp_cntrl0.L1cache.num_data_array_writes           11                       # number of data array writes
system.tcp_cntrl0.L1cache.num_tag_array_reads         1297                       # number of tag array reads
system.tcp_cntrl0.L1cache.num_tag_array_writes           11                       # number of tag array writes
system.tcp_cntrl0.L1cache.num_tag_array_stalls         1271                       # number of stalls caused by tag array
system.tcp_cntrl0.L1cache.num_data_array_stalls            2                       # number of stalls caused by data array
system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits            0                       # loads that hit in the TCP
system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers            0                       # TCP to TCP load transfers
system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
system.tcp_cntrl0.coalescer.gpu_ld_misses            5                       # loads that miss in the GPU
system.tcp_cntrl0.coalescer.gpu_tcp_st_hits            0                       # stores that hit in the TCP
system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers            0                       # TCP to TCP store transfers
system.tcp_cntrl0.coalescer.gpu_tcc_st_hits            0                       # stores that hit in the TCC
system.tcp_cntrl0.coalescer.gpu_st_misses            9                       # stores that miss in the GPU
system.tcp_cntrl0.coalescer.cp_tcp_ld_hits            0                       # loads that hit in the TCP
system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers            0                       # TCP to TCP load transfers
system.tcp_cntrl0.coalescer.cp_tcc_ld_hits            0                       # loads that hit in the TCC
system.tcp_cntrl0.coalescer.cp_ld_misses            0                       # loads that miss in the GPU
system.tcp_cntrl0.coalescer.cp_tcp_st_hits            0                       # stores that hit in the TCP
system.tcp_cntrl0.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
system.tcp_cntrl0.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
system.tcp_cntrl0.coalescer.cp_st_misses            0                       # stores that miss in the GPU
system.ruby.network.ext_links4.int_node.percent_links_utilized     0.003510                      
system.ruby.network.ext_links4.int_node.msg_count.Control::0           11                      
system.ruby.network.ext_links4.int_node.msg_count.Data::0           34                      
system.ruby.network.ext_links4.int_node.msg_count.Data::1           18                      
system.ruby.network.ext_links4.int_node.msg_count.Request_Control::0           16                      
system.ruby.network.ext_links4.int_node.msg_count.Request_Control::1            9                      
system.ruby.network.ext_links4.int_node.msg_count.Request_Control::7            5                      
system.ruby.network.ext_links4.int_node.msg_count.Request_Control::8            4                      
system.ruby.network.ext_links4.int_node.msg_count.Response_Data::2            9                      
system.ruby.network.ext_links4.int_node.msg_count.Response_Data::3           11                      
system.ruby.network.ext_links4.int_node.msg_count.Response_Control::2           22                      
system.ruby.network.ext_links4.int_node.msg_count.Response_Control::4           11                      
system.ruby.network.ext_links4.int_node.msg_count.Writeback_Control::2           16                      
system.ruby.network.ext_links4.int_node.msg_count.Writeback_Control::3           16                      
system.ruby.network.ext_links4.int_node.msg_count.Unblock_Control::4           32                      
system.ruby.network.ext_links4.int_node.msg_bytes.Control::0           88                      
system.ruby.network.ext_links4.int_node.msg_bytes.Data::0         2448                      
system.ruby.network.ext_links4.int_node.msg_bytes.Data::1         1296                      
system.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::0          128                      
system.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::1           72                      
system.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::7           40                      
system.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::8           32                      
system.ruby.network.ext_links4.int_node.msg_bytes.Response_Data::2          648                      
system.ruby.network.ext_links4.int_node.msg_bytes.Response_Data::3          792                      
system.ruby.network.ext_links4.int_node.msg_bytes.Response_Control::2          176                      
system.ruby.network.ext_links4.int_node.msg_bytes.Response_Control::4           88                      
system.ruby.network.ext_links4.int_node.msg_bytes.Writeback_Control::2          128                      
system.ruby.network.ext_links4.int_node.msg_bytes.Writeback_Control::3          128                      
system.ruby.network.ext_links4.int_node.msg_bytes.Unblock_Control::4          256                      
system.tcp_cntrl1.L1cache.demand_hits               0                       # Number of cache demand hits
system.tcp_cntrl1.L1cache.demand_misses             0                       # Number of cache demand misses
system.tcp_cntrl1.L1cache.demand_accesses            0                       # Number of cache demand accesses
system.tcp_cntrl1.L1cache.num_data_array_reads            6                       # number of data array reads
system.tcp_cntrl1.L1cache.num_data_array_writes           11                       # number of data array writes
system.tcp_cntrl1.L1cache.num_tag_array_reads         1297                       # number of tag array reads
system.tcp_cntrl1.L1cache.num_tag_array_writes           11                       # number of tag array writes
system.tcp_cntrl1.L1cache.num_tag_array_stalls         1271                       # number of stalls caused by tag array
system.tcp_cntrl1.L1cache.num_data_array_stalls            2                       # number of stalls caused by data array
system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits            0                       # loads that hit in the TCP
system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers            0                       # TCP to TCP load transfers
system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits            0                       # loads that hit in the TCC
system.tcp_cntrl1.coalescer.gpu_ld_misses            5                       # loads that miss in the GPU
system.tcp_cntrl1.coalescer.gpu_tcp_st_hits            0                       # stores that hit in the TCP
system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers            0                       # TCP to TCP store transfers
system.tcp_cntrl1.coalescer.gpu_tcc_st_hits            0                       # stores that hit in the TCC
system.tcp_cntrl1.coalescer.gpu_st_misses            9                       # stores that miss in the GPU
system.tcp_cntrl1.coalescer.cp_tcp_ld_hits            0                       # loads that hit in the TCP
system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers            0                       # TCP to TCP load transfers
system.tcp_cntrl1.coalescer.cp_tcc_ld_hits            0                       # loads that hit in the TCC
system.tcp_cntrl1.coalescer.cp_ld_misses            0                       # loads that miss in the GPU
system.tcp_cntrl1.coalescer.cp_tcp_st_hits            0                       # stores that hit in the TCP
system.tcp_cntrl1.coalescer.cp_tcp_st_transfers            0                       # TCP to TCP store transfers
system.tcp_cntrl1.coalescer.cp_tcc_st_hits            0                       # stores that hit in the TCC
system.tcp_cntrl1.coalescer.cp_st_misses            0                       # stores that miss in the GPU
system.sqc_cntrl0.L1cache.demand_hits               0                       # Number of cache demand hits
system.sqc_cntrl0.L1cache.demand_misses             0                       # Number of cache demand misses
system.sqc_cntrl0.L1cache.demand_accesses            0                       # Number of cache demand accesses
system.sqc_cntrl0.L1cache.num_data_array_reads           86                       # number of data array reads
system.sqc_cntrl0.L1cache.num_tag_array_reads           91                       # number of tag array reads
system.sqc_cntrl0.L1cache.num_tag_array_writes           10                       # number of tag array writes
system.sqc_cntrl0.sequencer.load_waiting_on_load           98                       # Number of times a load aliased with a pending load
system.tcc_cntrl0.L2cache.demand_hits               0                       # Number of cache demand hits
system.tcc_cntrl0.L2cache.demand_misses             0                       # Number of cache demand misses
system.tcc_cntrl0.L2cache.demand_accesses            0                       # Number of cache demand accesses
system.tcc_cntrl0.L2cache.num_data_array_writes            9                       # number of data array writes
system.tcc_cntrl0.L2cache.num_tag_array_reads           45                       # number of tag array reads
system.tcc_cntrl0.L2cache.num_tag_array_writes           21                       # number of tag array writes
system.tcc_rb_cntrl0.cacheMemory.demand_hits            0                       # Number of cache demand hits
system.tcc_rb_cntrl0.cacheMemory.demand_misses            0                       # Number of cache demand misses
system.tcc_rb_cntrl0.cacheMemory.demand_accesses            0                       # Number of cache demand accesses
system.tcc_rb_cntrl0.cacheMemory.num_tag_array_reads           29                       # number of tag array reads
system.tcc_rb_cntrl0.cacheMemory.num_tag_array_writes           89                       # number of tag array writes
system.tcc_rb_cntrl0.cacheMemory.num_tag_array_stalls           20                       # number of stalls caused by tag array
system.ruby.network.msg_count.Control              34                      
system.ruby.network.msg_count.Data                 68                      
system.ruby.network.msg_count.Request_Control         5534                      
system.ruby.network.msg_count.Response_Data         3165                      
system.ruby.network.msg_count.Response_Control          674                      
system.ruby.network.msg_count.Writeback_Control           56                      
system.ruby.network.msg_count.Unblock_Control         4686                      
system.ruby.network.msg_byte.Control              272                      
system.ruby.network.msg_byte.Data                4896                      
system.ruby.network.msg_byte.Request_Control        44272                      
system.ruby.network.msg_byte.Response_Data       227880                      
system.ruby.network.msg_byte.Response_Control         5392                      
system.ruby.network.msg_byte.Writeback_Control          448                      
system.ruby.network.msg_byte.Unblock_Control        37488                      
system.sqc_coalescer.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.sqc_coalescer.clk_domain.clock            1000                       # Clock period in ticks
system.sqc_coalescer.uncoalesced_accesses           86                       # Number of uncoalesced TLB accesses
system.sqc_coalescer.coalesced_accesses            66                       # Number of coalesced TLB accesses
system.sqc_coalescer.queuing_cycles            288000                       # Number of cycles spent in queue
system.sqc_coalescer.local_queuing_cycles       288000                       # Number of cycles spent in queue for all incoming reqs
system.sqc_coalescer.local_latency        3348.837209                       # Avg. latency over all incoming pkts
system.sqc_tlb.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.sqc_tlb.clk_domain.clock                  1000                       # Clock period in ticks
system.sqc_tlb.local_TLB_accesses                  66                       # Number of TLB accesses
system.sqc_tlb.local_TLB_hits                      65                       # Number of TLB hits
system.sqc_tlb.local_TLB_misses                     1                       # Number of TLB misses
system.sqc_tlb.local_TLB_miss_rate           1.515152                       # TLB miss rate
system.sqc_tlb.global_TLB_accesses                 86                       # Number of TLB accesses
system.sqc_tlb.global_TLB_hits                     78                       # Number of TLB hits
system.sqc_tlb.global_TLB_misses                    8                       # Number of TLB misses
system.sqc_tlb.global_TLB_miss_rate          9.302326                       # TLB miss rate
system.sqc_tlb.access_cycles                    86008                       # Cycles spent accessing this TLB level
system.sqc_tlb.page_table_cycles                    0                       # Cycles spent accessing the page table
system.sqc_tlb.unique_pages                         1                       # Number of unique pages touched
system.sqc_tlb.local_cycles                     66001                       # Number of cycles spent in queue for all incoming reqs
system.sqc_tlb.local_latency              1000.015152                       # Avg. latency over incoming coalesced reqs
system.sqc_tlb.avg_reuse_distance                   0                       # avg. reuse distance over all pages (in ticks)
system.ruby.network.ext_links0.int_node.throttle0.link_utilization     0.091873                      
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Data::0           16                      
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0         1279                      
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::5          279                      
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2           19                      
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2           17                      
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4         1556                      
system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Data::0         1152                      
system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0        10232                      
system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::5         2232                      
system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2         1368                      
system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2          136                      
system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4        12448                      
system.ruby.network.ext_links0.int_node.throttle1.link_utilization     0.015277                      
system.ruby.network.ext_links0.int_node.throttle1.msg_count.Request_Control::0          279                      
system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Control::2          286                      
system.ruby.network.ext_links0.int_node.throttle1.msg_count.Writeback_Control::2            8                      
system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Request_Control::0         2232                      
system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Control::2         2288                      
system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Writeback_Control::2           64                      
system.ruby.network.ext_links0.int_node.throttle2.link_utilization     0.379702                      
system.ruby.network.ext_links0.int_node.throttle2.msg_count.Request_Control::7          274                      
system.ruby.network.ext_links0.int_node.throttle2.msg_count.Request_Control::8            4                      
system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2         1549                      
system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Control::4           23                      
system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Request_Control::7         2192                      
system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Request_Control::8           32                      
system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2       111528                      
system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Control::4          184                      
system.ruby.network.ext_links0.int_node.throttle3.link_utilization     0.003119                      
system.ruby.network.ext_links0.int_node.throttle3.msg_count.Request_Control::7            5                      
system.ruby.network.ext_links0.int_node.throttle3.msg_count.Request_Control::8            4                      
system.ruby.network.ext_links0.int_node.throttle3.msg_count.Response_Data::2            9                      
system.ruby.network.ext_links0.int_node.throttle3.msg_count.Response_Control::4           11                      
system.ruby.network.ext_links0.int_node.throttle3.msg_count.Writeback_Control::2           16                      
system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Request_Control::7           40                      
system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Request_Control::8           32                      
system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Response_Data::2          648                      
system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Response_Control::4           88                      
system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Writeback_Control::2          128                      
system.ruby.network.ext_links2.int_node.throttle0.link_utilization     0.372290                      
system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::0           23                      
system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::2         1549                      
system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::0          184                      
system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::2       111528                      
system.ruby.network.ext_links2.int_node.throttle1.link_utilization     0.090620                      
system.ruby.network.ext_links2.int_node.throttle1.msg_count.Request_Control::0         1549                      
system.ruby.network.ext_links2.int_node.throttle1.msg_count.Request_Control::7          274                      
system.ruby.network.ext_links2.int_node.throttle1.msg_count.Request_Control::8            4                      
system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Control::4           23                      
system.ruby.network.ext_links2.int_node.throttle1.msg_count.Unblock_Control::4         1549                      
system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Request_Control::0        12392                      
system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Request_Control::7         2192                      
system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Request_Control::8           32                      
system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Control::4          184                      
system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Unblock_Control::4        12392                      
system.ruby.network.ext_links2.int_node.throttle2.link_utilization     0.094646                      
system.ruby.network.ext_links2.int_node.throttle2.msg_count.Request_Control::0         1549                      
system.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Data::2           19                      
system.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Control::2          281                      
system.ruby.network.ext_links2.int_node.throttle2.msg_count.Unblock_Control::4         1549                      
system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Request_Control::0        12392                      
system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Data::2         1368                      
system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Control::2         2248                      
system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Unblock_Control::4        12392                      
system.ruby.network.ext_links4.int_node.throttle0.link_utilization     0.000933                      
system.ruby.network.ext_links4.int_node.throttle0.msg_count.Response_Data::3            3                      
system.ruby.network.ext_links4.int_node.throttle0.msg_count.Writeback_Control::3            8                      
system.ruby.network.ext_links4.int_node.throttle0.msg_bytes.Response_Data::3          216                      
system.ruby.network.ext_links4.int_node.throttle0.msg_bytes.Writeback_Control::3           64                      
system.ruby.network.ext_links4.int_node.throttle1.link_utilization     0.000933                      
system.ruby.network.ext_links4.int_node.throttle1.msg_count.Response_Data::3            3                      
system.ruby.network.ext_links4.int_node.throttle1.msg_count.Writeback_Control::3            8                      
system.ruby.network.ext_links4.int_node.throttle1.msg_bytes.Response_Data::3          216                      
system.ruby.network.ext_links4.int_node.throttle1.msg_bytes.Writeback_Control::3           64                      
system.ruby.network.ext_links4.int_node.throttle2.link_utilization     0.007438                      
system.ruby.network.ext_links4.int_node.throttle2.msg_count.Control::0           11                      
system.ruby.network.ext_links4.int_node.throttle2.msg_count.Data::1           18                      
system.ruby.network.ext_links4.int_node.throttle2.msg_count.Request_Control::1            9                      
system.ruby.network.ext_links4.int_node.throttle2.msg_count.Response_Data::2            9                      
system.ruby.network.ext_links4.int_node.throttle2.msg_count.Writeback_Control::2           16                      
system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Control::0           88                      
system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Data::1         1296                      
system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Request_Control::1           72                      
system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Response_Data::2          648                      
system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Writeback_Control::2          128                      
system.ruby.network.ext_links4.int_node.throttle3.link_utilization     0.001200                      
system.ruby.network.ext_links4.int_node.throttle3.msg_count.Response_Data::3            5                      
system.ruby.network.ext_links4.int_node.throttle3.msg_bytes.Response_Data::3          360                      
system.ruby.network.ext_links4.int_node.throttle4.link_utilization     0.005705                      
system.ruby.network.ext_links4.int_node.throttle4.msg_count.Data::0           18                      
system.ruby.network.ext_links4.int_node.throttle4.msg_count.Request_Control::0            7                      
system.ruby.network.ext_links4.int_node.throttle4.msg_count.Request_Control::7            5                      
system.ruby.network.ext_links4.int_node.throttle4.msg_count.Request_Control::8            4                      
system.ruby.network.ext_links4.int_node.throttle4.msg_count.Response_Control::4           11                      
system.ruby.network.ext_links4.int_node.throttle4.msg_count.Unblock_Control::4           25                      
system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Data::0         1296                      
system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Request_Control::0           56                      
system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Request_Control::7           40                      
system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Request_Control::8           32                      
system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Response_Control::4           88                      
system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Unblock_Control::4          200                      
system.ruby.network.ext_links4.int_node.throttle5.link_utilization     0.004852                      
system.ruby.network.ext_links4.int_node.throttle5.msg_count.Data::0           16                      
system.ruby.network.ext_links4.int_node.throttle5.msg_count.Request_Control::0            9                      
system.ruby.network.ext_links4.int_node.throttle5.msg_count.Response_Control::2           22                      
system.ruby.network.ext_links4.int_node.throttle5.msg_count.Unblock_Control::4            7                      
system.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Data::0         1152                      
system.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Request_Control::0           72                      
system.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Response_Control::2          176                      
system.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Unblock_Control::4           56                      
system.ruby.CorePair_Controller.C0_Load_L1miss          193      0.00%      0.00%
system.ruby.CorePair_Controller.C0_Load_L1hit        16142      0.00%      0.00%
system.ruby.CorePair_Controller.Ifetch0_L1hit        85994      0.00%      0.00%
system.ruby.CorePair_Controller.Ifetch0_L1miss         1101      0.00%      0.00%
system.ruby.CorePair_Controller.C0_Store_L1miss          327      0.00%      0.00%
system.ruby.CorePair_Controller.C0_Store_L1hit        10446      0.00%      0.00%
system.ruby.CorePair_Controller.NB_AckS          1047      0.00%      0.00%
system.ruby.CorePair_Controller.NB_AckM           329      0.00%      0.00%
system.ruby.CorePair_Controller.NB_AckE           173      0.00%      0.00%
system.ruby.CorePair_Controller.L1I_Repl          602      0.00%      0.00%
system.ruby.CorePair_Controller.L1D0_Repl           28      0.00%      0.00%
system.ruby.CorePair_Controller.L2_to_L1D0            7      0.00%      0.00%
system.ruby.CorePair_Controller.L2_to_L1I           67      0.00%      0.00%
system.ruby.CorePair_Controller.PrbInvData           15      0.00%      0.00%
system.ruby.CorePair_Controller.PrbInvDataDemand            2      0.00%      0.00%
system.ruby.CorePair_Controller.PrbShrData            4      0.00%      0.00%
system.ruby.CorePair_Controller.PrbShrDataDemand            2      0.00%      0.00%
system.ruby.CorePair_Controller.I.C0_Load_L1miss          186      0.00%      0.00%
system.ruby.CorePair_Controller.I.Ifetch0_L1miss         1034      0.00%      0.00%
system.ruby.CorePair_Controller.I.C0_Store_L1miss          325      0.00%      0.00%
system.ruby.CorePair_Controller.I.PrbInvDataDemand            1      0.00%      0.00%
system.ruby.CorePair_Controller.S.C0_Load_L1hit          643      0.00%      0.00%
system.ruby.CorePair_Controller.S.Ifetch0_L1hit        85994      0.00%      0.00%
system.ruby.CorePair_Controller.S.Ifetch0_L1miss           67      0.00%      0.00%
system.ruby.CorePair_Controller.S.C0_Store_L1hit            4      0.00%      0.00%
system.ruby.CorePair_Controller.S.L1I_Repl          602      0.00%      0.00%
system.ruby.CorePair_Controller.E0.C0_Load_L1miss            2      0.00%      0.00%
system.ruby.CorePair_Controller.E0.C0_Load_L1hit         2728      0.00%      0.00%
system.ruby.CorePair_Controller.E0.C0_Store_L1hit           50      0.00%      0.00%
system.ruby.CorePair_Controller.E0.L1D0_Repl           16      0.00%      0.00%
system.ruby.CorePair_Controller.E0.PrbInvData            1      0.00%      0.00%
system.ruby.CorePair_Controller.E0.PrbShrData            1      0.00%      0.00%
system.ruby.CorePair_Controller.E0.PrbShrDataDemand            1      0.00%      0.00%
system.ruby.CorePair_Controller.O.PrbInvData            4      0.00%      0.00%
system.ruby.CorePair_Controller.M0.C0_Load_L1miss            5      0.00%      0.00%
system.ruby.CorePair_Controller.M0.C0_Load_L1hit        12771      0.00%      0.00%
system.ruby.CorePair_Controller.M0.C0_Store_L1miss            2      0.00%      0.00%
system.ruby.CorePair_Controller.M0.C0_Store_L1hit        10392      0.00%      0.00%
system.ruby.CorePair_Controller.M0.L1D0_Repl           12      0.00%      0.00%
system.ruby.CorePair_Controller.M0.PrbInvData           10      0.00%      0.00%
system.ruby.CorePair_Controller.M0.PrbInvDataDemand            1      0.00%      0.00%
system.ruby.CorePair_Controller.M0.PrbShrData            3      0.00%      0.00%
system.ruby.CorePair_Controller.M0.PrbShrDataDemand            1      0.00%      0.00%
system.ruby.CorePair_Controller.I_M0.NB_AckM          325      0.00%      0.00%
system.ruby.CorePair_Controller.I_E0S.NB_AckS           13      0.00%      0.00%
system.ruby.CorePair_Controller.I_E0S.NB_AckE          173      0.00%      0.00%
system.ruby.CorePair_Controller.Si_F0.L2_to_L1I           67      0.00%      0.00%
system.ruby.CorePair_Controller.S_M0.NB_AckM            4      0.00%      0.00%
system.ruby.CorePair_Controller.S0.NB_AckS         1034      0.00%      0.00%
system.ruby.CorePair_Controller.E0_F.L2_to_L1D0            2      0.00%      0.00%
system.ruby.CorePair_Controller.M0_F.L2_to_L1D0            5      0.00%      0.00%
system.ruby.Directory_Controller.RdBlkS           190      0.00%      0.00%
system.ruby.Directory_Controller.RdBlkM            31      0.00%      0.00%
system.ruby.Directory_Controller.RdBlk             56      0.00%      0.00%
system.ruby.Directory_Controller.WriteThrough            1      0.00%      0.00%
system.ruby.Directory_Controller.Atomic             1      0.00%      0.00%
system.ruby.Directory_Controller.RdBlkSP          844      0.00%      0.00%
system.ruby.Directory_Controller.RdBlkMP          298      0.00%      0.00%
system.ruby.Directory_Controller.RdBlkP           137      0.00%      0.00%
system.ruby.Directory_Controller.WriteThroughP           15      0.00%      0.00%
system.ruby.Directory_Controller.AtomicP            1      0.00%      0.00%
system.ruby.Directory_Controller.CPUPrbResp           28      0.00%      0.00%
system.ruby.Directory_Controller.LastCPUPrbResp            8      0.00%      0.00%
system.ruby.Directory_Controller.ProbeAcksComplete          271      0.00%      0.00%
system.ruby.Directory_Controller.L3Hit             11      0.00%      0.00%
system.ruby.Directory_Controller.MemData         1563      0.00%      0.00%
system.ruby.Directory_Controller.CoreUnblock         1556      0.00%      0.00%
system.ruby.Directory_Controller.UnblockWriteThrough           18      0.00%      0.00%
system.ruby.Directory_Controller.U.RdBlkS          190      0.00%      0.00%
system.ruby.Directory_Controller.U.RdBlkM           31      0.00%      0.00%
system.ruby.Directory_Controller.U.RdBlk           56      0.00%      0.00%
system.ruby.Directory_Controller.U.WriteThrough            1      0.00%      0.00%
system.ruby.Directory_Controller.U.Atomic            1      0.00%      0.00%
system.ruby.Directory_Controller.U.RdBlkSP          844      0.00%      0.00%
system.ruby.Directory_Controller.U.RdBlkMP          298      0.00%      0.00%
system.ruby.Directory_Controller.U.RdBlkP          137      0.00%      0.00%
system.ruby.Directory_Controller.U.WriteThroughP           15      0.00%      0.00%
system.ruby.Directory_Controller.U.AtomicP            1      0.00%      0.00%
system.ruby.Directory_Controller.U.CPUPrbResp           28      0.00%      0.00%
system.ruby.Directory_Controller.BS_M.MemData         1034      0.00%      0.00%
system.ruby.Directory_Controller.BM_M.MemData          347      0.00%      0.00%
system.ruby.Directory_Controller.B_M.L3Hit           11      0.00%      0.00%
system.ruby.Directory_Controller.B_M.MemData          180      0.00%      0.00%
system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete          190      0.00%      0.00%
system.ruby.Directory_Controller.BM_PM.LastCPUPrbResp            4      0.00%      0.00%
system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete           29      0.00%      0.00%
system.ruby.Directory_Controller.B_PM.LastCPUPrbResp            2      0.00%      0.00%
system.ruby.Directory_Controller.B_PM.ProbeAcksComplete           52      0.00%      0.00%
system.ruby.Directory_Controller.B_PM.MemData            2      0.00%      0.00%
system.ruby.Directory_Controller.B_Pm.LastCPUPrbResp            2      0.00%      0.00%
system.ruby.Directory_Controller.B.CoreUnblock         1556      0.00%      0.00%
system.ruby.Directory_Controller.B.UnblockWriteThrough           18      0.00%      0.00%
system.ruby.RegionBuffer_Controller.CPURead |        1220     99.43%     99.43% |           7      0.57%    100.00%
system.ruby.RegionBuffer_Controller.CPURead::total         1227                      
system.ruby.RegionBuffer_Controller.CPUWrite |         331     89.95%     89.95% |          37     10.05%    100.00%
system.ruby.RegionBuffer_Controller.CPUWrite::total          368                      
system.ruby.RegionBuffer_Controller.PrivateNotify |         272     98.91%     98.91% |           3      1.09%    100.00%
system.ruby.RegionBuffer_Controller.PrivateNotify::total          275                      
system.ruby.RegionBuffer_Controller.SharedNotify |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.RegionBuffer_Controller.SharedNotify::total            4                      
system.ruby.RegionBuffer_Controller.InvRegion |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.RegionBuffer_Controller.InvRegion::total            4                      
system.ruby.RegionBuffer_Controller.DowngradeRegion |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.RegionBuffer_Controller.DowngradeRegion::total            4                      
system.ruby.RegionBuffer_Controller.InvAck |          23     67.65%     67.65% |          11     32.35%    100.00%
system.ruby.RegionBuffer_Controller.InvAck::total           34                      
system.ruby.RegionBuffer_Controller.DoneAck |        1572     96.26%     96.26% |          61      3.74%    100.00%
system.ruby.RegionBuffer_Controller.DoneAck::total         1633                      
system.ruby.RegionBuffer_Controller.AllOutstanding |           6     54.55%     54.55% |           5     45.45%    100.00%
system.ruby.RegionBuffer_Controller.AllOutstanding::total           11                      
system.ruby.RegionBuffer_Controller.Evict |          64     66.67%     66.67% |          32     33.33%    100.00%
system.ruby.RegionBuffer_Controller.Evict::total           96                      
system.ruby.RegionBuffer_Controller.LastAck_PrbResp |           4     50.00%     50.00% |           4     50.00%    100.00%
system.ruby.RegionBuffer_Controller.LastAck_PrbResp::total            8                      
system.ruby.RegionBuffer_Controller.StallAccess |           0      0.00%      0.00% |          16    100.00%    100.00%
system.ruby.RegionBuffer_Controller.StallAccess::total           16                      
system.ruby.RegionBuffer_Controller.NP.CPURead |         243     98.78%     98.78% |           3      1.22%    100.00%
system.ruby.RegionBuffer_Controller.NP.CPURead::total          246                      
system.ruby.RegionBuffer_Controller.NP.CPUWrite |          29     96.67%     96.67% |           1      3.33%    100.00%
system.ruby.RegionBuffer_Controller.NP.CPUWrite::total           30                      
system.ruby.RegionBuffer_Controller.P.CPURead |         965     99.59%     99.59% |           4      0.41%    100.00%
system.ruby.RegionBuffer_Controller.P.CPURead::total          969                      
system.ruby.RegionBuffer_Controller.P.CPUWrite |         298     94.90%     94.90% |          16      5.10%    100.00%
system.ruby.RegionBuffer_Controller.P.CPUWrite::total          314                      
system.ruby.RegionBuffer_Controller.P.InvRegion |           1    100.00%    100.00% |           0      0.00%    100.00%
system.ruby.RegionBuffer_Controller.P.InvRegion::total            1                      
system.ruby.RegionBuffer_Controller.P.DowngradeRegion |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.RegionBuffer_Controller.P.DowngradeRegion::total            4                      
system.ruby.RegionBuffer_Controller.P.DoneAck |        1535     98.52%     98.52% |          23      1.48%    100.00%
system.ruby.RegionBuffer_Controller.P.DoneAck::total         1558                      
system.ruby.RegionBuffer_Controller.P.StallAccess |           0      0.00%      0.00% |          15    100.00%    100.00%
system.ruby.RegionBuffer_Controller.P.StallAccess::total           15                      
system.ruby.RegionBuffer_Controller.S.CPURead |          12    100.00%    100.00% |           0      0.00%    100.00%
system.ruby.RegionBuffer_Controller.S.CPURead::total           12                      
system.ruby.RegionBuffer_Controller.S.CPUWrite |           2     66.67%     66.67% |           1     33.33%    100.00%
system.ruby.RegionBuffer_Controller.S.CPUWrite::total            3                      
system.ruby.RegionBuffer_Controller.S.InvRegion |           1     33.33%     33.33% |           2     66.67%    100.00%
system.ruby.RegionBuffer_Controller.S.InvRegion::total            3                      
system.ruby.RegionBuffer_Controller.S.DoneAck |          14     87.50%     87.50% |           2     12.50%    100.00%
system.ruby.RegionBuffer_Controller.S.DoneAck::total           16                      
system.ruby.RegionBuffer_Controller.NP_PS.PrivateNotify |         270     99.26%     99.26% |           2      0.74%    100.00%
system.ruby.RegionBuffer_Controller.NP_PS.PrivateNotify::total          272                      
system.ruby.RegionBuffer_Controller.NP_PS.SharedNotify |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.RegionBuffer_Controller.NP_PS.SharedNotify::total            4                      
system.ruby.RegionBuffer_Controller.NP_PS.DoneAck |           8     25.81%     25.81% |          23     74.19%    100.00%
system.ruby.RegionBuffer_Controller.NP_PS.DoneAck::total           31                      
system.ruby.RegionBuffer_Controller.NP_PS.StallAccess |           0      0.00%      0.00% |           1    100.00%    100.00%
system.ruby.RegionBuffer_Controller.NP_PS.StallAccess::total            1                      
system.ruby.RegionBuffer_Controller.S_P.CPUWrite |           0      0.00%      0.00% |          18    100.00%    100.00%
system.ruby.RegionBuffer_Controller.S_P.CPUWrite::total           18                      
system.ruby.RegionBuffer_Controller.S_P.PrivateNotify |           2     66.67%     66.67% |           1     33.33%    100.00%
system.ruby.RegionBuffer_Controller.S_P.PrivateNotify::total            3                      
system.ruby.RegionBuffer_Controller.S_P.DoneAck |          15     53.57%     53.57% |          13     46.43%    100.00%
system.ruby.RegionBuffer_Controller.S_P.DoneAck::total           28                      
system.ruby.RegionBuffer_Controller.P_NP.InvAck |          17     60.71%     60.71% |          11     39.29%    100.00%
system.ruby.RegionBuffer_Controller.P_NP.InvAck::total           28                      
system.ruby.RegionBuffer_Controller.P_NP.Evict |          32     50.00%     50.00% |          32     50.00%    100.00%
system.ruby.RegionBuffer_Controller.P_NP.Evict::total           64                      
system.ruby.RegionBuffer_Controller.P_NP.LastAck_PrbResp |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.RegionBuffer_Controller.P_NP.LastAck_PrbResp::total            4                      
system.ruby.RegionBuffer_Controller.P_S.InvAck |           6    100.00%    100.00% |           0      0.00%    100.00%
system.ruby.RegionBuffer_Controller.P_S.InvAck::total            6                      
system.ruby.RegionBuffer_Controller.P_S.Evict |          32    100.00%    100.00% |           0      0.00%    100.00%
system.ruby.RegionBuffer_Controller.P_S.Evict::total           32                      
system.ruby.RegionBuffer_Controller.P_S.LastAck_PrbResp |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.RegionBuffer_Controller.P_S.LastAck_PrbResp::total            4                      
system.ruby.RegionBuffer_Controller.P_NP_O.AllOutstanding |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.RegionBuffer_Controller.P_NP_O.AllOutstanding::total            4                      
system.ruby.RegionBuffer_Controller.P_S_O.AllOutstanding |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.RegionBuffer_Controller.P_S_O.AllOutstanding::total            4                      
system.ruby.RegionBuffer_Controller.S_O.AllOutstanding |           2     66.67%     66.67% |           1     33.33%    100.00%
system.ruby.RegionBuffer_Controller.S_O.AllOutstanding::total            3                      
system.ruby.RegionBuffer_Controller.SS_P.CPUWrite |           2     66.67%     66.67% |           1     33.33%    100.00%
system.ruby.RegionBuffer_Controller.SS_P.CPUWrite::total            3                      
system.ruby.RegionDir_Controller.SendInv            1      0.00%      0.00%
system.ruby.RegionDir_Controller.SendUpgrade            3      0.00%      0.00%
system.ruby.RegionDir_Controller.SendDowngrade            4      0.00%      0.00%
system.ruby.RegionDir_Controller.PrivateRequest          271      0.00%      0.00%
system.ruby.RegionDir_Controller.InvAckCore            4      0.00%      0.00%
system.ruby.RegionDir_Controller.InvAckCoreNoShare            4      0.00%      0.00%
system.ruby.RegionDir_Controller.CPUPrivateAck          278      0.00%      0.00%
system.ruby.RegionDir_Controller.LastAck            8      0.00%      0.00%
system.ruby.RegionDir_Controller.DirReadyAck            8      0.00%      0.00%
system.ruby.RegionDir_Controller.TriggerInv            4      0.00%      0.00%
system.ruby.RegionDir_Controller.TriggerDowngrade            4      0.00%      0.00%
system.ruby.RegionDir_Controller.NP.PrivateRequest          271      0.00%      0.00%
system.ruby.RegionDir_Controller.P.SendInv            1      0.00%      0.00%
system.ruby.RegionDir_Controller.P.SendDowngrade            4      0.00%      0.00%
system.ruby.RegionDir_Controller.S.SendUpgrade            3      0.00%      0.00%
system.ruby.RegionDir_Controller.NP_P.CPUPrivateAck          270      0.00%      0.00%
system.ruby.RegionDir_Controller.P_P.CPUPrivateAck            1      0.00%      0.00%
system.ruby.RegionDir_Controller.P_S.CPUPrivateAck            4      0.00%      0.00%
system.ruby.RegionDir_Controller.S_P.CPUPrivateAck            3      0.00%      0.00%
system.ruby.RegionDir_Controller.P_AS.InvAckCore            4      0.00%      0.00%
system.ruby.RegionDir_Controller.P_AS.LastAck            4      0.00%      0.00%
system.ruby.RegionDir_Controller.S_AP.InvAckCoreNoShare            3      0.00%      0.00%
system.ruby.RegionDir_Controller.S_AP.LastAck            3      0.00%      0.00%
system.ruby.RegionDir_Controller.P_AP.InvAckCoreNoShare            1      0.00%      0.00%
system.ruby.RegionDir_Controller.P_AP.LastAck            1      0.00%      0.00%
system.ruby.RegionDir_Controller.P_AP_W.DirReadyAck            1      0.00%      0.00%
system.ruby.RegionDir_Controller.P_AP_W.TriggerInv            1      0.00%      0.00%
system.ruby.RegionDir_Controller.P_AS_W.DirReadyAck            4      0.00%      0.00%
system.ruby.RegionDir_Controller.P_AS_W.TriggerDowngrade            4      0.00%      0.00%
system.ruby.RegionDir_Controller.S_AP_W.DirReadyAck            3      0.00%      0.00%
system.ruby.RegionDir_Controller.S_AP_W.TriggerInv            3      0.00%      0.00%
system.ruby.LD.latency_hist::bucket_size           64                      
system.ruby.LD.latency_hist::max_bucket           639                      
system.ruby.LD.latency_hist::samples            16335                      
system.ruby.LD.latency_hist::mean            2.844751                      
system.ruby.LD.latency_hist::gmean           1.060634                      
system.ruby.LD.latency_hist::stdev          17.742972                      
system.ruby.LD.latency_hist              |       16149     98.86%     98.86% |          11      0.07%     98.93% |         119      0.73%     99.66% |          52      0.32%     99.98% |           2      0.01%     99.99% |           1      0.01%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.LD.latency_hist::total              16335                      
system.ruby.LD.hit_latency_hist::bucket_size           64                      
system.ruby.LD.hit_latency_hist::max_bucket          639                      
system.ruby.LD.hit_latency_hist::samples          186                      
system.ruby.LD.hit_latency_hist::mean      162.333333                      
system.ruby.LD.hit_latency_hist::gmean     157.431876                      
system.ruby.LD.hit_latency_hist::stdev      43.755298                      
system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |          11      5.91%      5.91% |         119     63.98%     69.89% |          52     27.96%     97.85% |           2      1.08%     98.92% |           1      0.54%     99.46% |           1      0.54%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.LD.hit_latency_hist::total            186                      
system.ruby.LD.miss_latency_hist::bucket_size            2                      
system.ruby.LD.miss_latency_hist::max_bucket           19                      
system.ruby.LD.miss_latency_hist::samples        16149                      
system.ruby.LD.miss_latency_hist::mean       1.007802                      
system.ruby.LD.miss_latency_hist::gmean      1.001277                      
system.ruby.LD.miss_latency_hist::stdev      0.374686                      
system.ruby.LD.miss_latency_hist         |       16142     99.96%     99.96% |           0      0.00%     99.96% |           0      0.00%     99.96% |           0      0.00%     99.96% |           0      0.00%     99.96% |           0      0.00%     99.96% |           0      0.00%     99.96% |           0      0.00%     99.96% |           0      0.00%     99.96% |           7      0.04%    100.00%
system.ruby.LD.miss_latency_hist::total         16149                      
system.ruby.ST.latency_hist::bucket_size           64                      
system.ruby.ST.latency_hist::max_bucket           639                      
system.ruby.ST.latency_hist::samples            10412                      
system.ruby.ST.latency_hist::mean            5.551287                      
system.ruby.ST.latency_hist::gmean           1.167783                      
system.ruby.ST.latency_hist::stdev          26.172531                      
system.ruby.ST.latency_hist              |       10087     96.88%     96.88% |           0      0.00%     96.88% |         289      2.78%     99.65% |          29      0.28%     99.93% |           4      0.04%     99.97% |           2      0.02%     99.99% |           0      0.00%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.ST.latency_hist::total              10412                      
system.ruby.ST.hit_latency_hist::bucket_size           64                      
system.ruby.ST.hit_latency_hist::max_bucket          639                      
system.ruby.ST.hit_latency_hist::samples          325                      
system.ruby.ST.hit_latency_hist::mean      146.809231                      
system.ruby.ST.hit_latency_hist::gmean     143.903653                      
system.ruby.ST.hit_latency_hist::stdev      36.751508                      
system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |         289     88.92%     88.92% |          29      8.92%     97.85% |           4      1.23%     99.08% |           2      0.62%     99.69% |           0      0.00%     99.69% |           1      0.31%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.ST.hit_latency_hist::total            325                      
system.ruby.ST.miss_latency_hist::bucket_size            1                      
system.ruby.ST.miss_latency_hist::max_bucket            9                      
system.ruby.ST.miss_latency_hist::samples        10087                      
system.ruby.ST.miss_latency_hist::mean              1                      
system.ruby.ST.miss_latency_hist::gmean             1                      
system.ruby.ST.miss_latency_hist         |           0      0.00%      0.00% |       10087    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.ST.miss_latency_hist::total         10087                      
system.ruby.IFETCH.latency_hist::bucket_size           64                      
system.ruby.IFETCH.latency_hist::max_bucket          639                      
system.ruby.IFETCH.latency_hist::samples        87095                      
system.ruby.IFETCH.latency_hist::mean        2.818945                      
system.ruby.IFETCH.latency_hist::gmean       1.063630                      
system.ruby.IFETCH.latency_hist::stdev      17.067789                      
system.ruby.IFETCH.latency_hist          |       86061     98.81%     98.81% |           0      0.00%     98.81% |         826      0.95%     99.76% |         185      0.21%     99.97% |           8      0.01%     99.98% |           9      0.01%     99.99% |           6      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.IFETCH.latency_hist::total          87095                      
system.ruby.IFETCH.hit_latency_hist::bucket_size           64                      
system.ruby.IFETCH.hit_latency_hist::max_bucket          639                      
system.ruby.IFETCH.hit_latency_hist::samples         1034                      
system.ruby.IFETCH.hit_latency_hist::mean   153.045455                      
system.ruby.IFETCH.hit_latency_hist::gmean   149.192268                      
system.ruby.IFETCH.hit_latency_hist::stdev    40.969954                      
system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |         826     79.88%     79.88% |         185     17.89%     97.78% |           8      0.77%     98.55% |           9      0.87%     99.42% |           6      0.58%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.IFETCH.hit_latency_hist::total         1034                      
system.ruby.IFETCH.miss_latency_hist::bucket_size            2                      
system.ruby.IFETCH.miss_latency_hist::max_bucket           19                      
system.ruby.IFETCH.miss_latency_hist::samples        86061                      
system.ruby.IFETCH.miss_latency_hist::mean     1.014013                      
system.ruby.IFETCH.miss_latency_hist::gmean     1.002295                      
system.ruby.IFETCH.miss_latency_hist::stdev     0.502042                      
system.ruby.IFETCH.miss_latency_hist     |       85994     99.92%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |           0      0.00%     99.92% |          67      0.08%    100.00%
system.ruby.IFETCH.miss_latency_hist::total        86061                      
system.ruby.RMW_Read.latency_hist::bucket_size           32                      
system.ruby.RMW_Read.latency_hist::max_bucket          319                      
system.ruby.RMW_Read.latency_hist::samples          341                      
system.ruby.RMW_Read.latency_hist::mean      2.671554                      
system.ruby.RMW_Read.latency_hist::gmean     1.059947                      
system.ruby.RMW_Read.latency_hist::stdev    15.416875                      
system.ruby.RMW_Read.latency_hist        |         337     98.83%     98.83% |           0      0.00%     98.83% |           0      0.00%     98.83% |           0      0.00%     98.83% |           3      0.88%     99.71% |           1      0.29%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.RMW_Read.latency_hist::total          341                      
system.ruby.RMW_Read.hit_latency_hist::bucket_size           32                      
system.ruby.RMW_Read.hit_latency_hist::max_bucket          319                      
system.ruby.RMW_Read.hit_latency_hist::samples            4                      
system.ruby.RMW_Read.hit_latency_hist::mean   143.500000                      
system.ruby.RMW_Read.hit_latency_hist::gmean   143.041358                      
system.ruby.RMW_Read.hit_latency_hist::stdev    13.403980                      
system.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3     75.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.RMW_Read.hit_latency_hist::total            4                      
system.ruby.RMW_Read.miss_latency_hist::bucket_size            1                      
system.ruby.RMW_Read.miss_latency_hist::max_bucket            9                      
system.ruby.RMW_Read.miss_latency_hist::samples          337                      
system.ruby.RMW_Read.miss_latency_hist::mean            1                      
system.ruby.RMW_Read.miss_latency_hist::gmean            1                      
system.ruby.RMW_Read.miss_latency_hist   |           0      0.00%      0.00% |         337    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.RMW_Read.miss_latency_hist::total          337                      
system.ruby.Locked_RMW_Read.latency_hist::bucket_size            1                      
system.ruby.Locked_RMW_Read.latency_hist::max_bucket            9                      
system.ruby.Locked_RMW_Read.latency_hist::samples           10                      
system.ruby.Locked_RMW_Read.latency_hist::mean            1                      
system.ruby.Locked_RMW_Read.latency_hist::gmean            1                      
system.ruby.Locked_RMW_Read.latency_hist |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Locked_RMW_Read.latency_hist::total           10                      
system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size            1                      
system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket            9                      
system.ruby.Locked_RMW_Read.miss_latency_hist::samples           10                      
system.ruby.Locked_RMW_Read.miss_latency_hist::mean            1                      
system.ruby.Locked_RMW_Read.miss_latency_hist::gmean            1                      
system.ruby.Locked_RMW_Read.miss_latency_hist |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Locked_RMW_Read.miss_latency_hist::total           10                      
system.ruby.Locked_RMW_Write.latency_hist::bucket_size            1                      
system.ruby.Locked_RMW_Write.latency_hist::max_bucket            9                      
system.ruby.Locked_RMW_Write.latency_hist::samples           10                      
system.ruby.Locked_RMW_Write.latency_hist::mean            1                      
system.ruby.Locked_RMW_Write.latency_hist::gmean            1                      
system.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Locked_RMW_Write.latency_hist::total           10                      
system.ruby.Locked_RMW_Write.miss_latency_hist::bucket_size            1                      
system.ruby.Locked_RMW_Write.miss_latency_hist::max_bucket            9                      
system.ruby.Locked_RMW_Write.miss_latency_hist::samples           10                      
system.ruby.Locked_RMW_Write.miss_latency_hist::mean            1                      
system.ruby.Locked_RMW_Write.miss_latency_hist::gmean            1                      
system.ruby.Locked_RMW_Write.miss_latency_hist |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Locked_RMW_Write.miss_latency_hist::total           10                      
system.ruby.L1Cache.miss_mach_latency_hist::bucket_size            1                      
system.ruby.L1Cache.miss_mach_latency_hist::max_bucket            9                      
system.ruby.L1Cache.miss_mach_latency_hist::samples       112580                      
system.ruby.L1Cache.miss_mach_latency_hist::mean            1                      
system.ruby.L1Cache.miss_mach_latency_hist::gmean            1                      
system.ruby.L1Cache.miss_mach_latency_hist |           0      0.00%      0.00% |      112580    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.L1Cache.miss_mach_latency_hist::total       112580                      
system.ruby.L2Cache.miss_mach_latency_hist::bucket_size            2                      
system.ruby.L2Cache.miss_mach_latency_hist::max_bucket           19                      
system.ruby.L2Cache.miss_mach_latency_hist::samples           74                      
system.ruby.L2Cache.miss_mach_latency_hist::mean           19                      
system.ruby.L2Cache.miss_mach_latency_hist::gmean    19.000000                      
system.ruby.L2Cache.miss_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          74    100.00%    100.00%
system.ruby.L2Cache.miss_mach_latency_hist::total           74                      
system.ruby.L3Cache.hit_mach_latency_hist::bucket_size           16                      
system.ruby.L3Cache.hit_mach_latency_hist::max_bucket          159                      
system.ruby.L3Cache.hit_mach_latency_hist::samples           11                      
system.ruby.L3Cache.hit_mach_latency_hist::mean          107                      
system.ruby.L3Cache.hit_mach_latency_hist::gmean   107.000000                      
system.ruby.L3Cache.hit_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          11    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.L3Cache.hit_mach_latency_hist::total           11                      
system.ruby.Directory.hit_mach_latency_hist::bucket_size           64                      
system.ruby.Directory.hit_mach_latency_hist::max_bucket          639                      
system.ruby.Directory.hit_mach_latency_hist::samples         1538                      
system.ruby.Directory.hit_mach_latency_hist::mean   153.155397                      
system.ruby.Directory.hit_mach_latency_hist::gmean   149.362802                      
system.ruby.Directory.hit_mach_latency_hist::stdev    40.587599                      
system.ruby.Directory.hit_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |        1238     80.49%     80.49% |         266     17.30%     97.79% |          14      0.91%     98.70% |          12      0.78%     99.48% |           7      0.46%     99.93% |           1      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Directory.hit_mach_latency_hist::total         1538                      
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size            1                      
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket            9                      
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples        16142                      
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean            1                      
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean            1                      
system.ruby.LD.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |       16142    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total        16142                      
system.ruby.LD.L2Cache.miss_type_mach_latency_hist::bucket_size            2                      
system.ruby.LD.L2Cache.miss_type_mach_latency_hist::max_bucket           19                      
system.ruby.LD.L2Cache.miss_type_mach_latency_hist::samples            7                      
system.ruby.LD.L2Cache.miss_type_mach_latency_hist::mean           19                      
system.ruby.LD.L2Cache.miss_type_mach_latency_hist::gmean    19.000000                      
system.ruby.LD.L2Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           7    100.00%    100.00%
system.ruby.LD.L2Cache.miss_type_mach_latency_hist::total            7                      
system.ruby.LD.L3Cache.hit_type_mach_latency_hist::bucket_size           16                      
system.ruby.LD.L3Cache.hit_type_mach_latency_hist::max_bucket          159                      
system.ruby.LD.L3Cache.hit_type_mach_latency_hist::samples           11                      
system.ruby.LD.L3Cache.hit_type_mach_latency_hist::mean          107                      
system.ruby.LD.L3Cache.hit_type_mach_latency_hist::gmean   107.000000                      
system.ruby.LD.L3Cache.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          11    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.LD.L3Cache.hit_type_mach_latency_hist::total           11                      
system.ruby.LD.Directory.hit_type_mach_latency_hist::bucket_size           64                      
system.ruby.LD.Directory.hit_type_mach_latency_hist::max_bucket          639                      
system.ruby.LD.Directory.hit_type_mach_latency_hist::samples          175                      
system.ruby.LD.Directory.hit_type_mach_latency_hist::mean   165.811429                      
system.ruby.LD.Directory.hit_type_mach_latency_hist::gmean   161.300002                      
system.ruby.LD.Directory.hit_type_mach_latency_hist::stdev    42.776536                      
system.ruby.LD.Directory.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         119     68.00%     68.00% |          52     29.71%     97.71% |           2      1.14%     98.86% |           1      0.57%     99.43% |           1      0.57%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.LD.Directory.hit_type_mach_latency_hist::total          175                      
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size            1                      
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket            9                      
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples        10087                      
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean            1                      
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean            1                      
system.ruby.ST.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |       10087    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total        10087                      
system.ruby.ST.Directory.hit_type_mach_latency_hist::bucket_size           64                      
system.ruby.ST.Directory.hit_type_mach_latency_hist::max_bucket          639                      
system.ruby.ST.Directory.hit_type_mach_latency_hist::samples          325                      
system.ruby.ST.Directory.hit_type_mach_latency_hist::mean   146.809231                      
system.ruby.ST.Directory.hit_type_mach_latency_hist::gmean   143.903653                      
system.ruby.ST.Directory.hit_type_mach_latency_hist::stdev    36.751508                      
system.ruby.ST.Directory.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         289     88.92%     88.92% |          29      8.92%     97.85% |           4      1.23%     99.08% |           2      0.62%     99.69% |           0      0.00%     99.69% |           1      0.31%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.ST.Directory.hit_type_mach_latency_hist::total          325                      
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::bucket_size            1                      
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::max_bucket            9                      
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::samples        85994                      
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::mean            1                      
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::gmean            1                      
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |       85994    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::total        85994                      
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::bucket_size            2                      
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::max_bucket           19                      
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::samples           67                      
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::mean           19                      
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::gmean    19.000000                      
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |          67    100.00%    100.00%
system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::total           67                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::bucket_size           64                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::max_bucket          639                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::samples         1034                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::mean   153.045455                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::gmean   149.192268                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::stdev    40.969954                      
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |         826     79.88%     79.88% |         185     17.89%     97.78% |           8      0.77%     98.55% |           9      0.87%     99.42% |           6      0.58%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total         1034                      
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size            1                      
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket            9                      
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::samples          337                      
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::mean            1                      
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean            1                      
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |         337    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::total          337                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::bucket_size           32                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::max_bucket          319                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::samples            4                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::mean   143.500000                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::gmean   143.041358                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::stdev    13.403980                      
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           3     75.00%     75.00% |           1     25.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::total            4                      
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size            1                      
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket            9                      
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::samples           10                      
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::mean            1                      
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean            1                      
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::total           10                      
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::bucket_size            1                      
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::max_bucket            9                      
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::samples           10                      
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::mean            1                      
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::gmean            1                      
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist |           0      0.00%      0.00% |          10    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::total           10                      
system.ruby.SQC_Controller.Fetch                   86      0.00%      0.00%
system.ruby.SQC_Controller.Data                     5      0.00%      0.00%
system.ruby.SQC_Controller.I.Fetch                  5      0.00%      0.00%
system.ruby.SQC_Controller.I.Data                   5      0.00%      0.00%
system.ruby.SQC_Controller.V.Fetch                 81      0.00%      0.00%
system.ruby.TCC_Controller.RdBlk                    9      0.00%      0.00%
system.ruby.TCC_Controller.WrVicBlk                16      0.00%      0.00%
system.ruby.TCC_Controller.Atomic                   2      0.00%      0.00%
system.ruby.TCC_Controller.AtomicDone               1      0.00%      0.00%
system.ruby.TCC_Controller.Data                     9      0.00%      0.00%
system.ruby.TCC_Controller.PrbInv                  11      0.00%      0.00%
system.ruby.TCC_Controller.WBAck                   16      0.00%      0.00%
system.ruby.TCC_Controller.V.PrbInv                 1      0.00%      0.00%
system.ruby.TCC_Controller.I.RdBlk                  7      0.00%      0.00%
system.ruby.TCC_Controller.I.WrVicBlk              16      0.00%      0.00%
system.ruby.TCC_Controller.I.Atomic                 1      0.00%      0.00%
system.ruby.TCC_Controller.I.PrbInv                10      0.00%      0.00%
system.ruby.TCC_Controller.I.WBAck                 16      0.00%      0.00%
system.ruby.TCC_Controller.IV.RdBlk                 2      0.00%      0.00%
system.ruby.TCC_Controller.IV.Data                  7      0.00%      0.00%
system.ruby.TCC_Controller.A.Atomic                 1      0.00%      0.00%
system.ruby.TCC_Controller.A.AtomicDone             1      0.00%      0.00%
system.ruby.TCC_Controller.A.Data                   2      0.00%      0.00%
system.ruby.TCP_Controller.Load          |           5     50.00%     50.00% |           5     50.00%    100.00%
system.ruby.TCP_Controller.Load::total             10                      
system.ruby.TCP_Controller.StoreThrough  |           8     50.00%     50.00% |           8     50.00%    100.00%
system.ruby.TCP_Controller.StoreThrough::total           16                      
system.ruby.TCP_Controller.Atomic        |           1     50.00%     50.00% |           1     50.00%    100.00%
system.ruby.TCP_Controller.Atomic::total            2                      
system.ruby.TCP_Controller.Flush         |         768     50.00%     50.00% |         768     50.00%    100.00%
system.ruby.TCP_Controller.Flush::total          1536                      
system.ruby.TCP_Controller.Evict         |         512     50.00%     50.00% |         512     50.00%    100.00%
system.ruby.TCP_Controller.Evict::total          1024                      
system.ruby.TCP_Controller.TCC_Ack       |           3     50.00%     50.00% |           3     50.00%    100.00%
system.ruby.TCP_Controller.TCC_Ack::total            6                      
system.ruby.TCP_Controller.TCC_AckWB     |           8     50.00%     50.00% |           8     50.00%    100.00%
system.ruby.TCP_Controller.TCC_AckWB::total           16                      
system.ruby.TCP_Controller.I.Load        |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.TCP_Controller.I.Load::total            4                      
system.ruby.TCP_Controller.I.StoreThrough |           8     50.00%     50.00% |           8     50.00%    100.00%
system.ruby.TCP_Controller.I.StoreThrough::total           16                      
system.ruby.TCP_Controller.I.Atomic      |           1     50.00%     50.00% |           1     50.00%    100.00%
system.ruby.TCP_Controller.I.Atomic::total            2                      
system.ruby.TCP_Controller.I.Flush       |         766     50.00%     50.00% |         766     50.00%    100.00%
system.ruby.TCP_Controller.I.Flush::total         1532                      
system.ruby.TCP_Controller.I.Evict       |         510     50.00%     50.00% |         510     50.00%    100.00%
system.ruby.TCP_Controller.I.Evict::total         1020                      
system.ruby.TCP_Controller.I.TCC_Ack     |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.TCP_Controller.I.TCC_Ack::total            4                      
system.ruby.TCP_Controller.I.TCC_AckWB   |           8     50.00%     50.00% |           8     50.00%    100.00%
system.ruby.TCP_Controller.I.TCC_AckWB::total           16                      
system.ruby.TCP_Controller.V.Load        |           3     50.00%     50.00% |           3     50.00%    100.00%
system.ruby.TCP_Controller.V.Load::total            6                      
system.ruby.TCP_Controller.V.Flush       |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.TCP_Controller.V.Flush::total            4                      
system.ruby.TCP_Controller.V.Evict       |           2     50.00%     50.00% |           2     50.00%    100.00%
system.ruby.TCP_Controller.V.Evict::total            4                      
system.ruby.TCP_Controller.A.TCC_Ack     |           1     50.00%     50.00% |           1     50.00%    100.00%
system.ruby.TCP_Controller.A.TCC_Ack::total            2                      

---------- End Simulation Statistics   ----------