stats.txt revision 11606
111106Spower.jg@gmail.com 211106Spower.jg@gmail.com---------- Begin Simulation Statistics ---------- 311606Sandreas.sandberg@arm.comsim_seconds 0.000062 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 62213000 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 62213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611106Spower.jg@gmail.comsim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 276862 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 276760 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 2667377590 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 639424 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 0.02 # Real time elapsed on the host 1211390Ssteve.reinhardt@amd.comsim_insts 6453 # Number of instructions simulated 1311390Ssteve.reinhardt@amd.comsim_ops 6453 # Number of ops (including micro ops) simulated 1411106Spower.jg@gmail.comsystem.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 1511106Spower.jg@gmail.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 1711106Spower.jg@gmail.comsystem.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 1811106Spower.jg@gmail.comsystem.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory 1911106Spower.jg@gmail.comsystem.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory 2011106Spower.jg@gmail.comsystem.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 2111106Spower.jg@gmail.comsystem.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 2211106Spower.jg@gmail.comsystem.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 2311106Spower.jg@gmail.comsystem.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory 2411106Spower.jg@gmail.comsystem.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory 2511606Sandreas.sandberg@arm.comsystem.mem_ctrl.bw_read::cpu.inst 285985244 # Total read bandwidth from this memory (bytes/s) 2611606Sandreas.sandberg@arm.comsystem.mem_ctrl.bw_read::cpu.data 172825615 # Total read bandwidth from this memory (bytes/s) 2711606Sandreas.sandberg@arm.comsystem.mem_ctrl.bw_read::total 458810859 # Total read bandwidth from this memory (bytes/s) 2811606Sandreas.sandberg@arm.comsystem.mem_ctrl.bw_inst_read::cpu.inst 285985244 # Instruction read bandwidth from this memory (bytes/s) 2911606Sandreas.sandberg@arm.comsystem.mem_ctrl.bw_inst_read::total 285985244 # Instruction read bandwidth from this memory (bytes/s) 3011606Sandreas.sandberg@arm.comsystem.mem_ctrl.bw_total::cpu.inst 285985244 # Total bandwidth to/from this memory (bytes/s) 3111606Sandreas.sandberg@arm.comsystem.mem_ctrl.bw_total::cpu.data 172825615 # Total bandwidth to/from this memory (bytes/s) 3211606Sandreas.sandberg@arm.comsystem.mem_ctrl.bw_total::total 458810859 # Total bandwidth to/from this memory (bytes/s) 3311106Spower.jg@gmail.comsystem.mem_ctrl.readReqs 446 # Number of read requests accepted 3411106Spower.jg@gmail.comsystem.mem_ctrl.writeReqs 0 # Number of write requests accepted 3511106Spower.jg@gmail.comsystem.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue 3611106Spower.jg@gmail.comsystem.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711106Spower.jg@gmail.comsystem.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM 3811106Spower.jg@gmail.comsystem.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 3911106Spower.jg@gmail.comsystem.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 4011106Spower.jg@gmail.comsystem.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side 4111106Spower.jg@gmail.comsystem.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side 4211106Spower.jg@gmail.comsystem.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 4311106Spower.jg@gmail.comsystem.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4411106Spower.jg@gmail.comsystem.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::0 62 # Per bank write bursts 4611106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::1 26 # Per bank write bursts 4711106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::2 24 # Per bank write bursts 4811106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::3 43 # Per bank write bursts 4911106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::4 40 # Per bank write bursts 5011106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::5 17 # Per bank write bursts 5111106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::6 1 # Per bank write bursts 5211106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::7 3 # Per bank write bursts 5311106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts 5411106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts 5511106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::10 19 # Per bank write bursts 5611106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::11 23 # Per bank write bursts 5711106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::12 14 # Per bank write bursts 5811106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::13 116 # Per bank write bursts 5911106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::14 45 # Per bank write bursts 6011106Spower.jg@gmail.comsystem.mem_ctrl.perBankRdBursts::15 12 # Per bank write bursts 6111106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts 6211106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts 6311106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts 6411106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts 6511106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts 6611106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts 6711106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts 6811106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts 6911106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts 7011106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts 7111106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 7211106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 7311106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 7411106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 7511106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 7611106Spower.jg@gmail.comsystem.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 7711106Spower.jg@gmail.comsystem.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 7811106Spower.jg@gmail.comsystem.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry 7911606Sandreas.sandberg@arm.comsystem.mem_ctrl.totGap 61962000 # Total gap between requests 8011106Spower.jg@gmail.comsystem.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 8111106Spower.jg@gmail.comsystem.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 8211106Spower.jg@gmail.comsystem.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 8311106Spower.jg@gmail.comsystem.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 8411106Spower.jg@gmail.comsystem.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 8511106Spower.jg@gmail.comsystem.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 8611106Spower.jg@gmail.comsystem.mem_ctrl.readPktSize::6 446 # Read request sizes (log2) 8711106Spower.jg@gmail.comsystem.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) 8811106Spower.jg@gmail.comsystem.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) 8911106Spower.jg@gmail.comsystem.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) 9011106Spower.jg@gmail.comsystem.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) 9111106Spower.jg@gmail.comsystem.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) 9211106Spower.jg@gmail.comsystem.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) 9311106Spower.jg@gmail.comsystem.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) 9411106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::0 446 # What read queue length does an incoming req see 9511106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see 9611106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see 9711106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see 9811106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see 9911106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see 10011106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see 10111106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see 10211106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see 10311106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see 10411106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see 10511106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see 10611106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see 10711106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see 10811106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see 10911106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see 11011106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see 11111106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see 11211106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see 11311106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see 11411106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see 11511106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see 11611106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see 11711106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see 11811106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see 11911106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 12011106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see 12111106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see 12211106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see 12311106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see 12411106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see 12511106Spower.jg@gmail.comsystem.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see 12611106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see 12711106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see 12811106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see 12911106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see 13011106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see 13111106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see 13211106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see 13311106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see 13411106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see 13511106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see 13611106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see 13711106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see 13811106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see 13911106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see 14011106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see 14111106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see 14211106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see 14311106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see 14411106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see 14511106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see 14611106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see 14711106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see 14811106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see 14911106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see 15011106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see 15111106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see 15211106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see 15311106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see 15411106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see 15511106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see 15611106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see 15711106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see 15811106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see 15911106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see 16011106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see 16111106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see 16211106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see 16311106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see 16411106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see 16511106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see 16611106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see 16711106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see 16811106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see 16911106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see 17011106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see 17111106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see 17211106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see 17311106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see 17411106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see 17511106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see 17611106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see 17711106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see 17811106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see 17911106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see 18011106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see 18111106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see 18211106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 18311106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 18411106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 18511106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 18611106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 18711106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 18811106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 18911106Spower.jg@gmail.comsystem.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011106Spower.jg@gmail.comsystem.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation 19111606Sandreas.sandberg@arm.comsystem.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation 19211606Sandreas.sandberg@arm.comsystem.mem_ctrl.bytesPerActivate::gmean 185.768755 # Bytes accessed per row activation 19311606Sandreas.sandberg@arm.comsystem.mem_ctrl.bytesPerActivate::stdev 255.860208 # Bytes accessed per row activation 19411606Sandreas.sandberg@arm.comsystem.mem_ctrl.bytesPerActivate::0-127 22 23.16% 23.16% # Bytes accessed per row activation 19511606Sandreas.sandberg@arm.comsystem.mem_ctrl.bytesPerActivate::128-255 36 37.89% 61.05% # Bytes accessed per row activation 19611606Sandreas.sandberg@arm.comsystem.mem_ctrl.bytesPerActivate::256-383 14 14.74% 75.79% # Bytes accessed per row activation 19711606Sandreas.sandberg@arm.comsystem.mem_ctrl.bytesPerActivate::384-511 5 5.26% 81.05% # Bytes accessed per row activation 19811606Sandreas.sandberg@arm.comsystem.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation 19911106Spower.jg@gmail.comsystem.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation 20011106Spower.jg@gmail.comsystem.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation 20111106Spower.jg@gmail.comsystem.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation 20211106Spower.jg@gmail.comsystem.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation 20311606Sandreas.sandberg@arm.comsystem.mem_ctrl.totQLat 3590750 # Total ticks spent queuing 20411606Sandreas.sandberg@arm.comsystem.mem_ctrl.totMemAccLat 11953250 # Total ticks spent from burst creation until serviced by the DRAM 20511106Spower.jg@gmail.comsystem.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers 20611606Sandreas.sandberg@arm.comsystem.mem_ctrl.avgQLat 8051.01 # Average queueing delay per DRAM burst 20711106Spower.jg@gmail.comsystem.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst 20811606Sandreas.sandberg@arm.comsystem.mem_ctrl.avgMemAccLat 26801.01 # Average memory access latency per DRAM burst 20911606Sandreas.sandberg@arm.comsystem.mem_ctrl.avgRdBW 458.81 # Average DRAM read bandwidth in MiByte/s 21011106Spower.jg@gmail.comsystem.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21111606Sandreas.sandberg@arm.comsystem.mem_ctrl.avgRdBWSys 458.81 # Average system read bandwidth in MiByte/s 21211106Spower.jg@gmail.comsystem.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21311106Spower.jg@gmail.comsystem.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21411606Sandreas.sandberg@arm.comsystem.mem_ctrl.busUtil 3.58 # Data bus utilization in percentage 21511606Sandreas.sandberg@arm.comsystem.mem_ctrl.busUtilRead 3.58 # Data bus utilization in percentage for reads 21611106Spower.jg@gmail.comsystem.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21711106Spower.jg@gmail.comsystem.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 21811106Spower.jg@gmail.comsystem.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 21911606Sandreas.sandberg@arm.comsystem.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads 22011106Spower.jg@gmail.comsystem.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 22111606Sandreas.sandberg@arm.comsystem.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads 22211106Spower.jg@gmail.comsystem.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 22311606Sandreas.sandberg@arm.comsystem.mem_ctrl.avgGap 138928.25 # Average gap between requests 22411606Sandreas.sandberg@arm.comsystem.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined 22511390Ssteve.reinhardt@amd.comsystem.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 22611390Ssteve.reinhardt@amd.comsystem.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 22711606Sandreas.sandberg@arm.comsystem.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ) 22811106Spower.jg@gmail.comsystem.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22911106Spower.jg@gmail.comsystem.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 23011606Sandreas.sandberg@arm.comsystem.mem_ctrl_0.actBackEnergy 37021500 # Energy for active background per rank (pJ) 23111606Sandreas.sandberg@arm.comsystem.mem_ctrl_0.preBackEnergy 383250 # Energy for precharge background per rank (pJ) 23211606Sandreas.sandberg@arm.comsystem.mem_ctrl_0.totalEnergy 43027155 # Total energy per rank (pJ) 23311606Sandreas.sandberg@arm.comsystem.mem_ctrl_0.averagePower 785.686791 # Core power per rank (mW) 23411606Sandreas.sandberg@arm.comsystem.mem_ctrl_0.memoryStateTime::IDLE 966000 # Time in different power states 23511106Spower.jg@gmail.comsystem.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states 23611106Spower.jg@gmail.comsystem.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23711606Sandreas.sandberg@arm.comsystem.mem_ctrl_0.memoryStateTime::ACT 52514000 # Time in different power states 23811106Spower.jg@gmail.comsystem.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23911606Sandreas.sandberg@arm.comsystem.mem_ctrl_1.actEnergy 370440 # Energy for activate commands per rank (pJ) 24011606Sandreas.sandberg@arm.comsystem.mem_ctrl_1.preEnergy 202125 # Energy for precharge commands per rank (pJ) 24111606Sandreas.sandberg@arm.comsystem.mem_ctrl_1.readEnergy 1466400 # Energy for read commands per rank (pJ) 24211106Spower.jg@gmail.comsystem.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24311106Spower.jg@gmail.comsystem.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 24411606Sandreas.sandberg@arm.comsystem.mem_ctrl_1.actBackEnergy 35989515 # Energy for active background per rank (pJ) 24511606Sandreas.sandberg@arm.comsystem.mem_ctrl_1.preBackEnergy 1288500 # Energy for precharge background per rank (pJ) 24611606Sandreas.sandberg@arm.comsystem.mem_ctrl_1.totalEnergy 42876900 # Total energy per rank (pJ) 24711606Sandreas.sandberg@arm.comsystem.mem_ctrl_1.averagePower 782.943096 # Core power per rank (mW) 24811606Sandreas.sandberg@arm.comsystem.mem_ctrl_1.memoryStateTime::IDLE 1815750 # Time in different power states 24911106Spower.jg@gmail.comsystem.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 25011106Spower.jg@gmail.comsystem.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25111606Sandreas.sandberg@arm.comsystem.mem_ctrl_1.memoryStateTime::ACT 51141750 # Time in different power states 25211106Spower.jg@gmail.comsystem.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25311606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 25411106Spower.jg@gmail.comsystem.cpu.dtb.fetch_hits 0 # ITB hits 25511106Spower.jg@gmail.comsystem.cpu.dtb.fetch_misses 0 # ITB misses 25611106Spower.jg@gmail.comsystem.cpu.dtb.fetch_acv 0 # ITB acv 25711106Spower.jg@gmail.comsystem.cpu.dtb.fetch_accesses 0 # ITB accesses 25811390Ssteve.reinhardt@amd.comsystem.cpu.dtb.read_hits 1190 # DTB read hits 25911106Spower.jg@gmail.comsystem.cpu.dtb.read_misses 7 # DTB read misses 26011106Spower.jg@gmail.comsystem.cpu.dtb.read_acv 0 # DTB read access violations 26111390Ssteve.reinhardt@amd.comsystem.cpu.dtb.read_accesses 1197 # DTB read accesses 26211106Spower.jg@gmail.comsystem.cpu.dtb.write_hits 865 # DTB write hits 26311106Spower.jg@gmail.comsystem.cpu.dtb.write_misses 3 # DTB write misses 26411106Spower.jg@gmail.comsystem.cpu.dtb.write_acv 0 # DTB write access violations 26511106Spower.jg@gmail.comsystem.cpu.dtb.write_accesses 868 # DTB write accesses 26611390Ssteve.reinhardt@amd.comsystem.cpu.dtb.data_hits 2055 # DTB hits 26711106Spower.jg@gmail.comsystem.cpu.dtb.data_misses 10 # DTB misses 26811106Spower.jg@gmail.comsystem.cpu.dtb.data_acv 0 # DTB access violations 26911390Ssteve.reinhardt@amd.comsystem.cpu.dtb.data_accesses 2065 # DTB accesses 27011390Ssteve.reinhardt@amd.comsystem.cpu.itb.fetch_hits 6464 # ITB hits 27111106Spower.jg@gmail.comsystem.cpu.itb.fetch_misses 17 # ITB misses 27211106Spower.jg@gmail.comsystem.cpu.itb.fetch_acv 0 # ITB acv 27311390Ssteve.reinhardt@amd.comsystem.cpu.itb.fetch_accesses 6481 # ITB accesses 27411106Spower.jg@gmail.comsystem.cpu.itb.read_hits 0 # DTB read hits 27511106Spower.jg@gmail.comsystem.cpu.itb.read_misses 0 # DTB read misses 27611106Spower.jg@gmail.comsystem.cpu.itb.read_acv 0 # DTB read access violations 27711106Spower.jg@gmail.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 27811106Spower.jg@gmail.comsystem.cpu.itb.write_hits 0 # DTB write hits 27911106Spower.jg@gmail.comsystem.cpu.itb.write_misses 0 # DTB write misses 28011106Spower.jg@gmail.comsystem.cpu.itb.write_acv 0 # DTB write access violations 28111106Spower.jg@gmail.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 28211106Spower.jg@gmail.comsystem.cpu.itb.data_hits 0 # DTB hits 28311106Spower.jg@gmail.comsystem.cpu.itb.data_misses 0 # DTB misses 28411106Spower.jg@gmail.comsystem.cpu.itb.data_acv 0 # DTB access violations 28511106Spower.jg@gmail.comsystem.cpu.itb.data_accesses 0 # DTB accesses 28611106Spower.jg@gmail.comsystem.cpu.workload.num_syscalls 17 # Number of system calls 28711606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 62213000 # Cumulative time (in ticks) in various power states 28811606Sandreas.sandberg@arm.comsystem.cpu.numCycles 62213 # number of cpu cycles simulated 28911106Spower.jg@gmail.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 29011106Spower.jg@gmail.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 29111390Ssteve.reinhardt@amd.comsystem.cpu.committedInsts 6453 # Number of instructions committed 29211390Ssteve.reinhardt@amd.comsystem.cpu.committedOps 6453 # Number of ops (including micro ops) committed 29311390Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses 29411106Spower.jg@gmail.comsystem.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 29511106Spower.jg@gmail.comsystem.cpu.num_func_calls 251 # number of times a function call or return occured 29611390Ssteve.reinhardt@amd.comsystem.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls 29711390Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts 6380 # number of integer instructions 29811106Spower.jg@gmail.comsystem.cpu.num_fp_insts 10 # number of float instructions 29911390Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads 8392 # number of times the integer registers were read 30011390Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes 4621 # number of times the integer registers were written 30111106Spower.jg@gmail.comsystem.cpu.num_fp_register_reads 8 # number of times the floating registers were read 30211106Spower.jg@gmail.comsystem.cpu.num_fp_register_writes 2 # number of times the floating registers were written 30311390Ssteve.reinhardt@amd.comsystem.cpu.num_mem_refs 2065 # number of memory refs 30411390Ssteve.reinhardt@amd.comsystem.cpu.num_load_insts 1197 # Number of load instructions 30511106Spower.jg@gmail.comsystem.cpu.num_store_insts 868 # Number of store instructions 30611106Spower.jg@gmail.comsystem.cpu.num_idle_cycles 0 # Number of idle cycles 30711606Sandreas.sandberg@arm.comsystem.cpu.num_busy_cycles 62213 # Number of busy cycles 30811106Spower.jg@gmail.comsystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 30911106Spower.jg@gmail.comsystem.cpu.idle_fraction 0 # Percentage of idle cycles 31011390Ssteve.reinhardt@amd.comsystem.cpu.Branches 1060 # Number of branches fetched 31111106Spower.jg@gmail.comsystem.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction 31211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction 31311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction 31411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction 31511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction 31611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction 31711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction 31811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction 31911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction 32011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction 32111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction 32211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction 32311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction 32411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction 32511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction 32611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction 32711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction 32811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction 32911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction 33011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction 33111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction 33211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction 33311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction 33411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction 33511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction 33611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction 33711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction 33811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction 33911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction 34011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction 34111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction 34211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction 34311106Spower.jg@gmail.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 34411106Spower.jg@gmail.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 34511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::total 6463 # Class of executed instruction 34611606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 34711106Spower.jg@gmail.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 34811606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tagsinuse 104.646393 # Cycle average of tags in use 34911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. 35011106Spower.jg@gmail.comsystem.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 35111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. 35211106Spower.jg@gmail.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 35311606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 104.646393 # Average occupied blocks per requestor 35411606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.102194 # Average percentage of cache occupancy 35511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.102194 # Average percentage of cache occupancy 35611106Spower.jg@gmail.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 35711106Spower.jg@gmail.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 35811106Spower.jg@gmail.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 35911106Spower.jg@gmail.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id 36011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses 36111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.data_accesses 4278 # Number of data accesses 36211606Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 36311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits 36411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits 36511106Spower.jg@gmail.comsystem.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 36611106Spower.jg@gmail.comsystem.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 36711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits 36811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits 36911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits 37011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_hits::total 1887 # number of overall hits 37111106Spower.jg@gmail.comsystem.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 37211106Spower.jg@gmail.comsystem.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 37311106Spower.jg@gmail.comsystem.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 37411106Spower.jg@gmail.comsystem.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 37511106Spower.jg@gmail.comsystem.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 37611106Spower.jg@gmail.comsystem.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 37711106Spower.jg@gmail.comsystem.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 37811106Spower.jg@gmail.comsystem.cpu.dcache.overall_misses::total 168 # number of overall misses 37911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 9887000 # number of ReadReq miss cycles 38011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 9887000 # number of ReadReq miss cycles 38111606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 7630000 # number of WriteReq miss cycles 38211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 7630000 # number of WriteReq miss cycles 38311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 17517000 # number of demand (read+write) miss cycles 38411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::total 17517000 # number of demand (read+write) miss cycles 38511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 17517000 # number of overall miss cycles 38611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::total 17517000 # number of overall miss cycles 38711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) 38811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) 38911106Spower.jg@gmail.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 39011106Spower.jg@gmail.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 39111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses 39211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses 39311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses 39411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses 39511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses 39611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses 39711106Spower.jg@gmail.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 39811106Spower.jg@gmail.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 39911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses 40011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses 40111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses 40211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses 40311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 104073.684211 # average ReadReq miss latency 40411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 104073.684211 # average ReadReq miss latency 40511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104520.547945 # average WriteReq miss latency 40611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 104520.547945 # average WriteReq miss latency 40711606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency 40811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 104267.857143 # average overall miss latency 40911606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency 41011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 104267.857143 # average overall miss latency 41111106Spower.jg@gmail.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 41211106Spower.jg@gmail.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 41311106Spower.jg@gmail.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 41411106Spower.jg@gmail.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 41511106Spower.jg@gmail.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 41611106Spower.jg@gmail.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 41711106Spower.jg@gmail.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 41811106Spower.jg@gmail.comsystem.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 41911106Spower.jg@gmail.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 42011106Spower.jg@gmail.comsystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 42111106Spower.jg@gmail.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 42211106Spower.jg@gmail.comsystem.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 42311106Spower.jg@gmail.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 42411106Spower.jg@gmail.comsystem.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 42511606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9697000 # number of ReadReq MSHR miss cycles 42611606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 9697000 # number of ReadReq MSHR miss cycles 42711606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7484000 # number of WriteReq MSHR miss cycles 42811606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 7484000 # number of WriteReq MSHR miss cycles 42911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 17181000 # number of demand (read+write) MSHR miss cycles 43011606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 17181000 # number of demand (read+write) MSHR miss cycles 43111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 17181000 # number of overall MSHR miss cycles 43211606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 17181000 # number of overall MSHR miss cycles 43311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses 43411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses 43511106Spower.jg@gmail.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 43611106Spower.jg@gmail.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 43711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses 43811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses 43911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses 44011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses 44111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 102073.684211 # average ReadReq mshr miss latency 44211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 102073.684211 # average ReadReq mshr miss latency 44311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102520.547945 # average WriteReq mshr miss latency 44411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102520.547945 # average WriteReq mshr miss latency 44511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency 44611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency 44711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency 44811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency 44911606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 45011106Spower.jg@gmail.comsystem.cpu.icache.tags.replacements 62 # number of replacements 45111606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tagsinuse 113.718871 # Cycle average of tags in use 45211390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. 45311106Spower.jg@gmail.comsystem.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. 45411390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. 45511106Spower.jg@gmail.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 45611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 113.718871 # Average occupied blocks per requestor 45711606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.444214 # Average percentage of cache occupancy 45811606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::total 0.444214 # Average percentage of cache occupancy 45911106Spower.jg@gmail.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id 46011106Spower.jg@gmail.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 46111106Spower.jg@gmail.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 46211106Spower.jg@gmail.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id 46311390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses 46411390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.data_accesses 13209 # Number of data accesses 46511606Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 46611390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits 46711390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits 46811390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits 46911390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits 47011390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits 47111390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_hits::total 6183 # number of overall hits 47211106Spower.jg@gmail.comsystem.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses 47311106Spower.jg@gmail.comsystem.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses 47411106Spower.jg@gmail.comsystem.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses 47511106Spower.jg@gmail.comsystem.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses 47611106Spower.jg@gmail.comsystem.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses 47711106Spower.jg@gmail.comsystem.cpu.icache.overall_misses::total 281 # number of overall misses 47811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 28558000 # number of ReadReq miss cycles 47911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 28558000 # number of ReadReq miss cycles 48011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 28558000 # number of demand (read+write) miss cycles 48111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::total 28558000 # number of demand (read+write) miss cycles 48211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 28558000 # number of overall miss cycles 48311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::total 28558000 # number of overall miss cycles 48411390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) 48511390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) 48611390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses 48711390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses 48811390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses 48911390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses 49011390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses 49111390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses 49211390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses 49311390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses 49411390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses 49511390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses 49611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101629.893238 # average ReadReq miss latency 49711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 101629.893238 # average ReadReq miss latency 49811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency 49911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 101629.893238 # average overall miss latency 50011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency 50111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 101629.893238 # average overall miss latency 50211106Spower.jg@gmail.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 50311106Spower.jg@gmail.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 50411106Spower.jg@gmail.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 50511106Spower.jg@gmail.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 50611106Spower.jg@gmail.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 50711106Spower.jg@gmail.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 50811106Spower.jg@gmail.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses 50911106Spower.jg@gmail.comsystem.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses 51011106Spower.jg@gmail.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses 51111106Spower.jg@gmail.comsystem.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses 51211106Spower.jg@gmail.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses 51311106Spower.jg@gmail.comsystem.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses 51411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27996000 # number of ReadReq MSHR miss cycles 51511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 27996000 # number of ReadReq MSHR miss cycles 51611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 27996000 # number of demand (read+write) MSHR miss cycles 51711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 27996000 # number of demand (read+write) MSHR miss cycles 51811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 27996000 # number of overall MSHR miss cycles 51911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 27996000 # number of overall MSHR miss cycles 52011390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses 52111390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses 52211390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses 52311390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses 52411390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses 52511390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses 52611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99629.893238 # average ReadReq mshr miss latency 52711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99629.893238 # average ReadReq mshr miss latency 52811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency 52911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency 53011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency 53111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency 53211138Sandreas.hansson@arm.comsystem.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. 53311138Sandreas.hansson@arm.comsystem.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. 53411138Sandreas.hansson@arm.comsystem.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 53511138Sandreas.hansson@arm.comsystem.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 53611138Sandreas.hansson@arm.comsystem.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 53711138Sandreas.hansson@arm.comsystem.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 53811606Sandreas.sandberg@arm.comsystem.l2bus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 53911106Spower.jg@gmail.comsystem.l2bus.trans_dist::ReadResp 376 # Transaction distribution 54011106Spower.jg@gmail.comsystem.l2bus.trans_dist::CleanEvict 62 # Transaction distribution 54111106Spower.jg@gmail.comsystem.l2bus.trans_dist::ReadExReq 73 # Transaction distribution 54211106Spower.jg@gmail.comsystem.l2bus.trans_dist::ReadExResp 73 # Transaction distribution 54311106Spower.jg@gmail.comsystem.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution 54411106Spower.jg@gmail.comsystem.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) 54511106Spower.jg@gmail.comsystem.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 54611106Spower.jg@gmail.comsystem.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) 54711106Spower.jg@gmail.comsystem.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 17984 # Cumulative packet size per connected master and slave (bytes) 54811106Spower.jg@gmail.comsystem.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 54911106Spower.jg@gmail.comsystem.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes) 55011106Spower.jg@gmail.comsystem.l2bus.snoops 0 # Total snoops (count) 55111570SCurtis.Dunham@arm.comsystem.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) 55211201Sandreas.hansson@arm.comsystem.l2bus.snoop_fanout::samples 449 # Request fanout histogram 55311201Sandreas.hansson@arm.comsystem.l2bus.snoop_fanout::mean 0.002227 # Request fanout histogram 55411201Sandreas.hansson@arm.comsystem.l2bus.snoop_fanout::stdev 0.047193 # Request fanout histogram 55511106Spower.jg@gmail.comsystem.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 55611201Sandreas.hansson@arm.comsystem.l2bus.snoop_fanout::0 448 99.78% 99.78% # Request fanout histogram 55711201Sandreas.hansson@arm.comsystem.l2bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram 55811106Spower.jg@gmail.comsystem.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 55911106Spower.jg@gmail.comsystem.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 56011138Sandreas.hansson@arm.comsystem.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 56111106Spower.jg@gmail.comsystem.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 56211201Sandreas.hansson@arm.comsystem.l2bus.snoop_fanout::total 449 # Request fanout histogram 56311106Spower.jg@gmail.comsystem.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) 56411106Spower.jg@gmail.comsystem.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 56511106Spower.jg@gmail.comsystem.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) 56611106Spower.jg@gmail.comsystem.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) 56711106Spower.jg@gmail.comsystem.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) 56811106Spower.jg@gmail.comsystem.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) 56911606Sandreas.sandberg@arm.comsystem.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 57011106Spower.jg@gmail.comsystem.l2cache.tags.replacements 0 # number of replacements 57111606Sandreas.sandberg@arm.comsystem.l2cache.tags.tagsinuse 233.175851 # Cycle average of tags in use 57211106Spower.jg@gmail.comsystem.l2cache.tags.total_refs 65 # Total number of references to valid blocks. 57311606Sandreas.sandberg@arm.comsystem.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. 57411606Sandreas.sandberg@arm.comsystem.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. 57511106Spower.jg@gmail.comsystem.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 57611606Sandreas.sandberg@arm.comsystem.l2cache.tags.occ_blocks::cpu.inst 128.472749 # Average occupied blocks per requestor 57711606Sandreas.sandberg@arm.comsystem.l2cache.tags.occ_blocks::cpu.data 104.703102 # Average occupied blocks per requestor 57811606Sandreas.sandberg@arm.comsystem.l2cache.tags.occ_percent::cpu.inst 0.031365 # Average percentage of cache occupancy 57911606Sandreas.sandberg@arm.comsystem.l2cache.tags.occ_percent::cpu.data 0.025562 # Average percentage of cache occupancy 58011606Sandreas.sandberg@arm.comsystem.l2cache.tags.occ_percent::total 0.056928 # Average percentage of cache occupancy 58111606Sandreas.sandberg@arm.comsystem.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id 58211106Spower.jg@gmail.comsystem.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 58311606Sandreas.sandberg@arm.comsystem.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id 58411606Sandreas.sandberg@arm.comsystem.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id 58511106Spower.jg@gmail.comsystem.l2cache.tags.tag_accesses 4534 # Number of tag accesses 58611106Spower.jg@gmail.comsystem.l2cache.tags.data_accesses 4534 # Number of data accesses 58711606Sandreas.sandberg@arm.comsystem.l2cache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 58811106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits 58911106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 59011106Spower.jg@gmail.comsystem.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 59111106Spower.jg@gmail.comsystem.l2cache.demand_hits::total 3 # number of demand (read+write) hits 59211106Spower.jg@gmail.comsystem.l2cache.overall_hits::cpu.inst 3 # number of overall hits 59311106Spower.jg@gmail.comsystem.l2cache.overall_hits::total 3 # number of overall hits 59411106Spower.jg@gmail.comsystem.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 59511106Spower.jg@gmail.comsystem.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 59611106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses 59711106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses 59811106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses 59911106Spower.jg@gmail.comsystem.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 60011106Spower.jg@gmail.comsystem.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 60111106Spower.jg@gmail.comsystem.l2cache.demand_misses::total 446 # number of demand (read+write) misses 60211106Spower.jg@gmail.comsystem.l2cache.overall_misses::cpu.inst 278 # number of overall misses 60311106Spower.jg@gmail.comsystem.l2cache.overall_misses::cpu.data 168 # number of overall misses 60411106Spower.jg@gmail.comsystem.l2cache.overall_misses::total 446 # number of overall misses 60511606Sandreas.sandberg@arm.comsystem.l2cache.ReadExReq_miss_latency::cpu.data 7265000 # number of ReadExReq miss cycles 60611606Sandreas.sandberg@arm.comsystem.l2cache.ReadExReq_miss_latency::total 7265000 # number of ReadExReq miss cycles 60711606Sandreas.sandberg@arm.comsystem.l2cache.ReadSharedReq_miss_latency::cpu.inst 27088000 # number of ReadSharedReq miss cycles 60811606Sandreas.sandberg@arm.comsystem.l2cache.ReadSharedReq_miss_latency::cpu.data 9412000 # number of ReadSharedReq miss cycles 60911606Sandreas.sandberg@arm.comsystem.l2cache.ReadSharedReq_miss_latency::total 36500000 # number of ReadSharedReq miss cycles 61011606Sandreas.sandberg@arm.comsystem.l2cache.demand_miss_latency::cpu.inst 27088000 # number of demand (read+write) miss cycles 61111606Sandreas.sandberg@arm.comsystem.l2cache.demand_miss_latency::cpu.data 16677000 # number of demand (read+write) miss cycles 61211606Sandreas.sandberg@arm.comsystem.l2cache.demand_miss_latency::total 43765000 # number of demand (read+write) miss cycles 61311606Sandreas.sandberg@arm.comsystem.l2cache.overall_miss_latency::cpu.inst 27088000 # number of overall miss cycles 61411606Sandreas.sandberg@arm.comsystem.l2cache.overall_miss_latency::cpu.data 16677000 # number of overall miss cycles 61511606Sandreas.sandberg@arm.comsystem.l2cache.overall_miss_latency::total 43765000 # number of overall miss cycles 61611106Spower.jg@gmail.comsystem.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 61711106Spower.jg@gmail.comsystem.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 61811106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) 61911106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) 62011106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses) 62111106Spower.jg@gmail.comsystem.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses 62211106Spower.jg@gmail.comsystem.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 62311106Spower.jg@gmail.comsystem.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses 62411106Spower.jg@gmail.comsystem.l2cache.overall_accesses::cpu.inst 281 # number of overall (read+write) accesses 62511106Spower.jg@gmail.comsystem.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 62611106Spower.jg@gmail.comsystem.l2cache.overall_accesses::total 449 # number of overall (read+write) accesses 62711106Spower.jg@gmail.comsystem.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 62811106Spower.jg@gmail.comsystem.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 62911106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.989324 # miss rate for ReadSharedReq accesses 63011106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 63111106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses 63211106Spower.jg@gmail.comsystem.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses 63311106Spower.jg@gmail.comsystem.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 63411106Spower.jg@gmail.comsystem.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses 63511106Spower.jg@gmail.comsystem.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses 63611106Spower.jg@gmail.comsystem.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 63711106Spower.jg@gmail.comsystem.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses 63811606Sandreas.sandberg@arm.comsystem.l2cache.ReadExReq_avg_miss_latency::cpu.data 99520.547945 # average ReadExReq miss latency 63911606Sandreas.sandberg@arm.comsystem.l2cache.ReadExReq_avg_miss_latency::total 99520.547945 # average ReadExReq miss latency 64011606Sandreas.sandberg@arm.comsystem.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97438.848921 # average ReadSharedReq miss latency 64111606Sandreas.sandberg@arm.comsystem.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99073.684211 # average ReadSharedReq miss latency 64211606Sandreas.sandberg@arm.comsystem.l2cache.ReadSharedReq_avg_miss_latency::total 97855.227882 # average ReadSharedReq miss latency 64311606Sandreas.sandberg@arm.comsystem.l2cache.demand_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency 64411606Sandreas.sandberg@arm.comsystem.l2cache.demand_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency 64511606Sandreas.sandberg@arm.comsystem.l2cache.demand_avg_miss_latency::total 98127.802691 # average overall miss latency 64611606Sandreas.sandberg@arm.comsystem.l2cache.overall_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency 64711606Sandreas.sandberg@arm.comsystem.l2cache.overall_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency 64811606Sandreas.sandberg@arm.comsystem.l2cache.overall_avg_miss_latency::total 98127.802691 # average overall miss latency 64911106Spower.jg@gmail.comsystem.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 65011106Spower.jg@gmail.comsystem.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 65111106Spower.jg@gmail.comsystem.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 65211106Spower.jg@gmail.comsystem.l2cache.blocked::no_targets 0 # number of cycles access was blocked 65311106Spower.jg@gmail.comsystem.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 65411106Spower.jg@gmail.comsystem.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 65511106Spower.jg@gmail.comsystem.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 65611106Spower.jg@gmail.comsystem.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 65711106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses 65811106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 65911106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses 66011106Spower.jg@gmail.comsystem.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 66111106Spower.jg@gmail.comsystem.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 66211106Spower.jg@gmail.comsystem.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 66311106Spower.jg@gmail.comsystem.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 66411106Spower.jg@gmail.comsystem.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 66511106Spower.jg@gmail.comsystem.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 66611606Sandreas.sandberg@arm.comsystem.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5805000 # number of ReadExReq MSHR miss cycles 66711606Sandreas.sandberg@arm.comsystem.l2cache.ReadExReq_mshr_miss_latency::total 5805000 # number of ReadExReq MSHR miss cycles 66811606Sandreas.sandberg@arm.comsystem.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21528000 # number of ReadSharedReq MSHR miss cycles 66911606Sandreas.sandberg@arm.comsystem.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7512000 # number of ReadSharedReq MSHR miss cycles 67011606Sandreas.sandberg@arm.comsystem.l2cache.ReadSharedReq_mshr_miss_latency::total 29040000 # number of ReadSharedReq MSHR miss cycles 67111606Sandreas.sandberg@arm.comsystem.l2cache.demand_mshr_miss_latency::cpu.inst 21528000 # number of demand (read+write) MSHR miss cycles 67211606Sandreas.sandberg@arm.comsystem.l2cache.demand_mshr_miss_latency::cpu.data 13317000 # number of demand (read+write) MSHR miss cycles 67311606Sandreas.sandberg@arm.comsystem.l2cache.demand_mshr_miss_latency::total 34845000 # number of demand (read+write) MSHR miss cycles 67411606Sandreas.sandberg@arm.comsystem.l2cache.overall_mshr_miss_latency::cpu.inst 21528000 # number of overall MSHR miss cycles 67511606Sandreas.sandberg@arm.comsystem.l2cache.overall_mshr_miss_latency::cpu.data 13317000 # number of overall MSHR miss cycles 67611606Sandreas.sandberg@arm.comsystem.l2cache.overall_mshr_miss_latency::total 34845000 # number of overall MSHR miss cycles 67711106Spower.jg@gmail.comsystem.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 67811106Spower.jg@gmail.comsystem.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 67911106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses 68011106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 68111106Spower.jg@gmail.comsystem.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses 68211106Spower.jg@gmail.comsystem.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses 68311106Spower.jg@gmail.comsystem.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 68411106Spower.jg@gmail.comsystem.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses 68511106Spower.jg@gmail.comsystem.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses 68611106Spower.jg@gmail.comsystem.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 68711106Spower.jg@gmail.comsystem.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses 68811606Sandreas.sandberg@arm.comsystem.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79520.547945 # average ReadExReq mshr miss latency 68911606Sandreas.sandberg@arm.comsystem.l2cache.ReadExReq_avg_mshr_miss_latency::total 79520.547945 # average ReadExReq mshr miss latency 69011606Sandreas.sandberg@arm.comsystem.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77438.848921 # average ReadSharedReq mshr miss latency 69111606Sandreas.sandberg@arm.comsystem.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79073.684211 # average ReadSharedReq mshr miss latency 69211606Sandreas.sandberg@arm.comsystem.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77855.227882 # average ReadSharedReq mshr miss latency 69311606Sandreas.sandberg@arm.comsystem.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency 69411606Sandreas.sandberg@arm.comsystem.l2cache.demand_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency 69511606Sandreas.sandberg@arm.comsystem.l2cache.demand_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency 69611606Sandreas.sandberg@arm.comsystem.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency 69711606Sandreas.sandberg@arm.comsystem.l2cache.overall_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency 69811606Sandreas.sandberg@arm.comsystem.l2cache.overall_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency 69911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. 70011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 70111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 70211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 70311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 70411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 70511606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 70611106Spower.jg@gmail.comsystem.membus.trans_dist::ReadResp 373 # Transaction distribution 70711106Spower.jg@gmail.comsystem.membus.trans_dist::ReadExReq 73 # Transaction distribution 70811106Spower.jg@gmail.comsystem.membus.trans_dist::ReadExResp 73 # Transaction distribution 70911106Spower.jg@gmail.comsystem.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 71011106Spower.jg@gmail.comsystem.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) 71111106Spower.jg@gmail.comsystem.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 71211106Spower.jg@gmail.comsystem.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) 71311106Spower.jg@gmail.comsystem.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 71411106Spower.jg@gmail.comsystem.membus.snoops 0 # Total snoops (count) 71511570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 71611106Spower.jg@gmail.comsystem.membus.snoop_fanout::samples 446 # Request fanout histogram 71711106Spower.jg@gmail.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 71811106Spower.jg@gmail.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 71911106Spower.jg@gmail.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 72011106Spower.jg@gmail.comsystem.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 72111106Spower.jg@gmail.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 72211106Spower.jg@gmail.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 72311106Spower.jg@gmail.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 72411106Spower.jg@gmail.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 72511106Spower.jg@gmail.comsystem.membus.snoop_fanout::total 446 # Request fanout histogram 72611106Spower.jg@gmail.comsystem.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) 72711106Spower.jg@gmail.comsystem.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 72811606Sandreas.sandberg@arm.comsystem.membus.respLayer0.occupancy 2375750 # Layer occupancy (ticks) 72911606Sandreas.sandberg@arm.comsystem.membus.respLayer0.utilization 3.8 # Layer utilization (%) 73011106Spower.jg@gmail.com 73111106Spower.jg@gmail.com---------- End Simulation Statistics ---------- 732