stats.txt revision 11606
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000062 # Number of seconds simulated 4sim_ticks 62213000 # Number of ticks simulated 5final_tick 62213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 276862 # Simulator instruction rate (inst/s) 8host_op_rate 276760 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2667377590 # Simulator tick rate (ticks/s) 10host_mem_usage 639424 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 6453 # Number of instructions simulated 13sim_ops 6453 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 17system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory 25system.mem_ctrl.bw_read::cpu.inst 285985244 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 172825615 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 458810859 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 285985244 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 285985244 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 285985244 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 172825615 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 458810859 # Total bandwidth to/from this memory (bytes/s) 33system.mem_ctrl.readReqs 446 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side 41system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.mem_ctrl.perBankRdBursts::0 62 # Per bank write bursts 46system.mem_ctrl.perBankRdBursts::1 26 # Per bank write bursts 47system.mem_ctrl.perBankRdBursts::2 24 # Per bank write bursts 48system.mem_ctrl.perBankRdBursts::3 43 # Per bank write bursts 49system.mem_ctrl.perBankRdBursts::4 40 # Per bank write bursts 50system.mem_ctrl.perBankRdBursts::5 17 # Per bank write bursts 51system.mem_ctrl.perBankRdBursts::6 1 # Per bank write bursts 52system.mem_ctrl.perBankRdBursts::7 3 # Per bank write bursts 53system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts 54system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts 55system.mem_ctrl.perBankRdBursts::10 19 # Per bank write bursts 56system.mem_ctrl.perBankRdBursts::11 23 # Per bank write bursts 57system.mem_ctrl.perBankRdBursts::12 14 # Per bank write bursts 58system.mem_ctrl.perBankRdBursts::13 116 # Per bank write bursts 59system.mem_ctrl.perBankRdBursts::14 45 # Per bank write bursts 60system.mem_ctrl.perBankRdBursts::15 12 # Per bank write bursts 61system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts 62system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts 63system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts 64system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts 65system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts 66system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts 67system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts 68system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts 69system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts 70system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry 79system.mem_ctrl.totGap 61962000 # Total gap between requests 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 446 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) 88system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) 89system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) 90system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) 91system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) 92system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) 93system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) 94system.mem_ctrl.rdQLenPdf::0 446 # What read queue length does an incoming req see 95system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see 96system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see 97system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 185.768755 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 255.860208 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::0-127 22 23.16% 23.16% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 36 37.89% 61.05% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::256-383 14 14.74% 75.79% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 5 5.26% 81.05% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation 203system.mem_ctrl.totQLat 3590750 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 11953250 # Total ticks spent from burst creation until serviced by the DRAM 205system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers 206system.mem_ctrl.avgQLat 8051.01 # Average queueing delay per DRAM burst 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.mem_ctrl.avgMemAccLat 26801.01 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 458.81 # Average DRAM read bandwidth in MiByte/s 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.mem_ctrl.avgRdBWSys 458.81 # Average system read bandwidth in MiByte/s 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.mem_ctrl.busUtil 3.58 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.58 # Data bus utilization in percentage for reads 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads 220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 221system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads 222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 223system.mem_ctrl.avgGap 138928.25 # Average gap between requests 224system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 227system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ) 228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 230system.mem_ctrl_0.actBackEnergy 37021500 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 383250 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.totalEnergy 43027155 # Total energy per rank (pJ) 233system.mem_ctrl_0.averagePower 785.686791 # Core power per rank (mW) 234system.mem_ctrl_0.memoryStateTime::IDLE 966000 # Time in different power states 235system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states 236system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.mem_ctrl_0.memoryStateTime::ACT 52514000 # Time in different power states 238system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.mem_ctrl_1.actEnergy 370440 # Energy for activate commands per rank (pJ) 240system.mem_ctrl_1.preEnergy 202125 # Energy for precharge commands per rank (pJ) 241system.mem_ctrl_1.readEnergy 1466400 # Energy for read commands per rank (pJ) 242system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 244system.mem_ctrl_1.actBackEnergy 35989515 # Energy for active background per rank (pJ) 245system.mem_ctrl_1.preBackEnergy 1288500 # Energy for precharge background per rank (pJ) 246system.mem_ctrl_1.totalEnergy 42876900 # Total energy per rank (pJ) 247system.mem_ctrl_1.averagePower 782.943096 # Core power per rank (mW) 248system.mem_ctrl_1.memoryStateTime::IDLE 1815750 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT 51141750 # Time in different power states 252system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 254system.cpu.dtb.fetch_hits 0 # ITB hits 255system.cpu.dtb.fetch_misses 0 # ITB misses 256system.cpu.dtb.fetch_acv 0 # ITB acv 257system.cpu.dtb.fetch_accesses 0 # ITB accesses 258system.cpu.dtb.read_hits 1190 # DTB read hits 259system.cpu.dtb.read_misses 7 # DTB read misses 260system.cpu.dtb.read_acv 0 # DTB read access violations 261system.cpu.dtb.read_accesses 1197 # DTB read accesses 262system.cpu.dtb.write_hits 865 # DTB write hits 263system.cpu.dtb.write_misses 3 # DTB write misses 264system.cpu.dtb.write_acv 0 # DTB write access violations 265system.cpu.dtb.write_accesses 868 # DTB write accesses 266system.cpu.dtb.data_hits 2055 # DTB hits 267system.cpu.dtb.data_misses 10 # DTB misses 268system.cpu.dtb.data_acv 0 # DTB access violations 269system.cpu.dtb.data_accesses 2065 # DTB accesses 270system.cpu.itb.fetch_hits 6464 # ITB hits 271system.cpu.itb.fetch_misses 17 # ITB misses 272system.cpu.itb.fetch_acv 0 # ITB acv 273system.cpu.itb.fetch_accesses 6481 # ITB accesses 274system.cpu.itb.read_hits 0 # DTB read hits 275system.cpu.itb.read_misses 0 # DTB read misses 276system.cpu.itb.read_acv 0 # DTB read access violations 277system.cpu.itb.read_accesses 0 # DTB read accesses 278system.cpu.itb.write_hits 0 # DTB write hits 279system.cpu.itb.write_misses 0 # DTB write misses 280system.cpu.itb.write_acv 0 # DTB write access violations 281system.cpu.itb.write_accesses 0 # DTB write accesses 282system.cpu.itb.data_hits 0 # DTB hits 283system.cpu.itb.data_misses 0 # DTB misses 284system.cpu.itb.data_acv 0 # DTB access violations 285system.cpu.itb.data_accesses 0 # DTB accesses 286system.cpu.workload.num_syscalls 17 # Number of system calls 287system.cpu.pwrStateResidencyTicks::ON 62213000 # Cumulative time (in ticks) in various power states 288system.cpu.numCycles 62213 # number of cpu cycles simulated 289system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 290system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 291system.cpu.committedInsts 6453 # Number of instructions committed 292system.cpu.committedOps 6453 # Number of ops (including micro ops) committed 293system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses 294system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 295system.cpu.num_func_calls 251 # number of times a function call or return occured 296system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls 297system.cpu.num_int_insts 6380 # number of integer instructions 298system.cpu.num_fp_insts 10 # number of float instructions 299system.cpu.num_int_register_reads 8392 # number of times the integer registers were read 300system.cpu.num_int_register_writes 4621 # number of times the integer registers were written 301system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 302system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 303system.cpu.num_mem_refs 2065 # number of memory refs 304system.cpu.num_load_insts 1197 # Number of load instructions 305system.cpu.num_store_insts 868 # Number of store instructions 306system.cpu.num_idle_cycles 0 # Number of idle cycles 307system.cpu.num_busy_cycles 62213 # Number of busy cycles 308system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 309system.cpu.idle_fraction 0 # Percentage of idle cycles 310system.cpu.Branches 1060 # Number of branches fetched 311system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction 312system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction 313system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction 314system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction 315system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction 316system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction 317system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction 318system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction 319system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction 320system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction 321system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction 322system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction 323system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction 324system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction 325system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction 326system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction 327system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction 328system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction 329system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction 330system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction 331system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction 332system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction 333system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction 334system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction 335system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction 336system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction 337system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction 338system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction 339system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction 340system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction 341system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction 342system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction 343system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 344system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 345system.cpu.op_class::total 6463 # Class of executed instruction 346system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 347system.cpu.dcache.tags.replacements 0 # number of replacements 348system.cpu.dcache.tags.tagsinuse 104.646393 # Cycle average of tags in use 349system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. 350system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 351system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. 352system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 353system.cpu.dcache.tags.occ_blocks::cpu.data 104.646393 # Average occupied blocks per requestor 354system.cpu.dcache.tags.occ_percent::cpu.data 0.102194 # Average percentage of cache occupancy 355system.cpu.dcache.tags.occ_percent::total 0.102194 # Average percentage of cache occupancy 356system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 357system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 358system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 359system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id 360system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses 361system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses 362system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 363system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits 364system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits 365system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 366system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 367system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits 368system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits 369system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits 370system.cpu.dcache.overall_hits::total 1887 # number of overall hits 371system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 372system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 373system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 374system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 375system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 376system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 377system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 378system.cpu.dcache.overall_misses::total 168 # number of overall misses 379system.cpu.dcache.ReadReq_miss_latency::cpu.data 9887000 # number of ReadReq miss cycles 380system.cpu.dcache.ReadReq_miss_latency::total 9887000 # number of ReadReq miss cycles 381system.cpu.dcache.WriteReq_miss_latency::cpu.data 7630000 # number of WriteReq miss cycles 382system.cpu.dcache.WriteReq_miss_latency::total 7630000 # number of WriteReq miss cycles 383system.cpu.dcache.demand_miss_latency::cpu.data 17517000 # number of demand (read+write) miss cycles 384system.cpu.dcache.demand_miss_latency::total 17517000 # number of demand (read+write) miss cycles 385system.cpu.dcache.overall_miss_latency::cpu.data 17517000 # number of overall miss cycles 386system.cpu.dcache.overall_miss_latency::total 17517000 # number of overall miss cycles 387system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) 388system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) 389system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 390system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 391system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses 392system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses 393system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses 394system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses 395system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses 396system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses 397system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 398system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 399system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses 400system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses 401system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses 402system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses 403system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 104073.684211 # average ReadReq miss latency 404system.cpu.dcache.ReadReq_avg_miss_latency::total 104073.684211 # average ReadReq miss latency 405system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104520.547945 # average WriteReq miss latency 406system.cpu.dcache.WriteReq_avg_miss_latency::total 104520.547945 # average WriteReq miss latency 407system.cpu.dcache.demand_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency 408system.cpu.dcache.demand_avg_miss_latency::total 104267.857143 # average overall miss latency 409system.cpu.dcache.overall_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency 410system.cpu.dcache.overall_avg_miss_latency::total 104267.857143 # average overall miss latency 411system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 412system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 413system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 415system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 416system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 417system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 418system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 419system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 420system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 421system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 422system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 423system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 424system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 425system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9697000 # number of ReadReq MSHR miss cycles 426system.cpu.dcache.ReadReq_mshr_miss_latency::total 9697000 # number of ReadReq MSHR miss cycles 427system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7484000 # number of WriteReq MSHR miss cycles 428system.cpu.dcache.WriteReq_mshr_miss_latency::total 7484000 # number of WriteReq MSHR miss cycles 429system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17181000 # number of demand (read+write) MSHR miss cycles 430system.cpu.dcache.demand_mshr_miss_latency::total 17181000 # number of demand (read+write) MSHR miss cycles 431system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17181000 # number of overall MSHR miss cycles 432system.cpu.dcache.overall_mshr_miss_latency::total 17181000 # number of overall MSHR miss cycles 433system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses 434system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses 435system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 436system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 437system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses 438system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses 439system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses 440system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses 441system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 102073.684211 # average ReadReq mshr miss latency 442system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 102073.684211 # average ReadReq mshr miss latency 443system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102520.547945 # average WriteReq mshr miss latency 444system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102520.547945 # average WriteReq mshr miss latency 445system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency 446system.cpu.dcache.demand_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency 447system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency 448system.cpu.dcache.overall_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency 449system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 450system.cpu.icache.tags.replacements 62 # number of replacements 451system.cpu.icache.tags.tagsinuse 113.718871 # Cycle average of tags in use 452system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. 453system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. 454system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. 455system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 456system.cpu.icache.tags.occ_blocks::cpu.inst 113.718871 # Average occupied blocks per requestor 457system.cpu.icache.tags.occ_percent::cpu.inst 0.444214 # Average percentage of cache occupancy 458system.cpu.icache.tags.occ_percent::total 0.444214 # Average percentage of cache occupancy 459system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id 460system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 461system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 462system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id 463system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses 464system.cpu.icache.tags.data_accesses 13209 # Number of data accesses 465system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 466system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits 467system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits 468system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits 469system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits 470system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits 471system.cpu.icache.overall_hits::total 6183 # number of overall hits 472system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses 473system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses 474system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses 475system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses 476system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses 477system.cpu.icache.overall_misses::total 281 # number of overall misses 478system.cpu.icache.ReadReq_miss_latency::cpu.inst 28558000 # number of ReadReq miss cycles 479system.cpu.icache.ReadReq_miss_latency::total 28558000 # number of ReadReq miss cycles 480system.cpu.icache.demand_miss_latency::cpu.inst 28558000 # number of demand (read+write) miss cycles 481system.cpu.icache.demand_miss_latency::total 28558000 # number of demand (read+write) miss cycles 482system.cpu.icache.overall_miss_latency::cpu.inst 28558000 # number of overall miss cycles 483system.cpu.icache.overall_miss_latency::total 28558000 # number of overall miss cycles 484system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) 485system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) 486system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses 487system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses 488system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses 489system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses 490system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses 491system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses 492system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses 493system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses 494system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses 495system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses 496system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101629.893238 # average ReadReq miss latency 497system.cpu.icache.ReadReq_avg_miss_latency::total 101629.893238 # average ReadReq miss latency 498system.cpu.icache.demand_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency 499system.cpu.icache.demand_avg_miss_latency::total 101629.893238 # average overall miss latency 500system.cpu.icache.overall_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency 501system.cpu.icache.overall_avg_miss_latency::total 101629.893238 # average overall miss latency 502system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 503system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 504system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 505system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 506system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 507system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 508system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses 509system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses 510system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses 511system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses 512system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses 513system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses 514system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27996000 # number of ReadReq MSHR miss cycles 515system.cpu.icache.ReadReq_mshr_miss_latency::total 27996000 # number of ReadReq MSHR miss cycles 516system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27996000 # number of demand (read+write) MSHR miss cycles 517system.cpu.icache.demand_mshr_miss_latency::total 27996000 # number of demand (read+write) MSHR miss cycles 518system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27996000 # number of overall MSHR miss cycles 519system.cpu.icache.overall_mshr_miss_latency::total 27996000 # number of overall MSHR miss cycles 520system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses 521system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses 522system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses 523system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses 524system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses 525system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses 526system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99629.893238 # average ReadReq mshr miss latency 527system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99629.893238 # average ReadReq mshr miss latency 528system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency 529system.cpu.icache.demand_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency 530system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency 531system.cpu.icache.overall_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency 532system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. 533system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. 534system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 535system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 536system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 537system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 538system.l2bus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 539system.l2bus.trans_dist::ReadResp 376 # Transaction distribution 540system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution 541system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution 542system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution 543system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution 544system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) 545system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 546system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) 547system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 17984 # Cumulative packet size per connected master and slave (bytes) 548system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 549system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes) 550system.l2bus.snoops 0 # Total snoops (count) 551system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) 552system.l2bus.snoop_fanout::samples 449 # Request fanout histogram 553system.l2bus.snoop_fanout::mean 0.002227 # Request fanout histogram 554system.l2bus.snoop_fanout::stdev 0.047193 # Request fanout histogram 555system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 556system.l2bus.snoop_fanout::0 448 99.78% 99.78% # Request fanout histogram 557system.l2bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram 558system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 559system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 560system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 561system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 562system.l2bus.snoop_fanout::total 449 # Request fanout histogram 563system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) 564system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 565system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) 566system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) 567system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) 568system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) 569system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 570system.l2cache.tags.replacements 0 # number of replacements 571system.l2cache.tags.tagsinuse 233.175851 # Cycle average of tags in use 572system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. 573system.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. 574system.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. 575system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 576system.l2cache.tags.occ_blocks::cpu.inst 128.472749 # Average occupied blocks per requestor 577system.l2cache.tags.occ_blocks::cpu.data 104.703102 # Average occupied blocks per requestor 578system.l2cache.tags.occ_percent::cpu.inst 0.031365 # Average percentage of cache occupancy 579system.l2cache.tags.occ_percent::cpu.data 0.025562 # Average percentage of cache occupancy 580system.l2cache.tags.occ_percent::total 0.056928 # Average percentage of cache occupancy 581system.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id 582system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 583system.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id 584system.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id 585system.l2cache.tags.tag_accesses 4534 # Number of tag accesses 586system.l2cache.tags.data_accesses 4534 # Number of data accesses 587system.l2cache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 588system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits 589system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 590system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 591system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 592system.l2cache.overall_hits::cpu.inst 3 # number of overall hits 593system.l2cache.overall_hits::total 3 # number of overall hits 594system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 595system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 596system.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses 597system.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses 598system.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses 599system.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 600system.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 601system.l2cache.demand_misses::total 446 # number of demand (read+write) misses 602system.l2cache.overall_misses::cpu.inst 278 # number of overall misses 603system.l2cache.overall_misses::cpu.data 168 # number of overall misses 604system.l2cache.overall_misses::total 446 # number of overall misses 605system.l2cache.ReadExReq_miss_latency::cpu.data 7265000 # number of ReadExReq miss cycles 606system.l2cache.ReadExReq_miss_latency::total 7265000 # number of ReadExReq miss cycles 607system.l2cache.ReadSharedReq_miss_latency::cpu.inst 27088000 # number of ReadSharedReq miss cycles 608system.l2cache.ReadSharedReq_miss_latency::cpu.data 9412000 # number of ReadSharedReq miss cycles 609system.l2cache.ReadSharedReq_miss_latency::total 36500000 # number of ReadSharedReq miss cycles 610system.l2cache.demand_miss_latency::cpu.inst 27088000 # number of demand (read+write) miss cycles 611system.l2cache.demand_miss_latency::cpu.data 16677000 # number of demand (read+write) miss cycles 612system.l2cache.demand_miss_latency::total 43765000 # number of demand (read+write) miss cycles 613system.l2cache.overall_miss_latency::cpu.inst 27088000 # number of overall miss cycles 614system.l2cache.overall_miss_latency::cpu.data 16677000 # number of overall miss cycles 615system.l2cache.overall_miss_latency::total 43765000 # number of overall miss cycles 616system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 617system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 618system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) 619system.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) 620system.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses) 621system.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses 622system.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 623system.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses 624system.l2cache.overall_accesses::cpu.inst 281 # number of overall (read+write) accesses 625system.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 626system.l2cache.overall_accesses::total 449 # number of overall (read+write) accesses 627system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 628system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 629system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.989324 # miss rate for ReadSharedReq accesses 630system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 631system.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses 632system.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses 633system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 634system.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses 635system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses 636system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 637system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses 638system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99520.547945 # average ReadExReq miss latency 639system.l2cache.ReadExReq_avg_miss_latency::total 99520.547945 # average ReadExReq miss latency 640system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97438.848921 # average ReadSharedReq miss latency 641system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99073.684211 # average ReadSharedReq miss latency 642system.l2cache.ReadSharedReq_avg_miss_latency::total 97855.227882 # average ReadSharedReq miss latency 643system.l2cache.demand_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency 644system.l2cache.demand_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency 645system.l2cache.demand_avg_miss_latency::total 98127.802691 # average overall miss latency 646system.l2cache.overall_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency 647system.l2cache.overall_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency 648system.l2cache.overall_avg_miss_latency::total 98127.802691 # average overall miss latency 649system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 650system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 651system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 652system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 653system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 654system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 655system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 656system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 657system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses 658system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 659system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses 660system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 661system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 662system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 663system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 664system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 665system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 666system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5805000 # number of ReadExReq MSHR miss cycles 667system.l2cache.ReadExReq_mshr_miss_latency::total 5805000 # number of ReadExReq MSHR miss cycles 668system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21528000 # number of ReadSharedReq MSHR miss cycles 669system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7512000 # number of ReadSharedReq MSHR miss cycles 670system.l2cache.ReadSharedReq_mshr_miss_latency::total 29040000 # number of ReadSharedReq MSHR miss cycles 671system.l2cache.demand_mshr_miss_latency::cpu.inst 21528000 # number of demand (read+write) MSHR miss cycles 672system.l2cache.demand_mshr_miss_latency::cpu.data 13317000 # number of demand (read+write) MSHR miss cycles 673system.l2cache.demand_mshr_miss_latency::total 34845000 # number of demand (read+write) MSHR miss cycles 674system.l2cache.overall_mshr_miss_latency::cpu.inst 21528000 # number of overall MSHR miss cycles 675system.l2cache.overall_mshr_miss_latency::cpu.data 13317000 # number of overall MSHR miss cycles 676system.l2cache.overall_mshr_miss_latency::total 34845000 # number of overall MSHR miss cycles 677system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 678system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 679system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses 680system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 681system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses 682system.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses 683system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 684system.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses 685system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses 686system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 687system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses 688system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79520.547945 # average ReadExReq mshr miss latency 689system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79520.547945 # average ReadExReq mshr miss latency 690system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77438.848921 # average ReadSharedReq mshr miss latency 691system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79073.684211 # average ReadSharedReq mshr miss latency 692system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77855.227882 # average ReadSharedReq mshr miss latency 693system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency 694system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency 695system.l2cache.demand_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency 696system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency 697system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency 698system.l2cache.overall_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency 699system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. 700system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 701system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 702system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 703system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 704system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 705system.membus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states 706system.membus.trans_dist::ReadResp 373 # Transaction distribution 707system.membus.trans_dist::ReadExReq 73 # Transaction distribution 708system.membus.trans_dist::ReadExResp 73 # Transaction distribution 709system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 710system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) 711system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 712system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) 713system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 714system.membus.snoops 0 # Total snoops (count) 715system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 716system.membus.snoop_fanout::samples 446 # Request fanout histogram 717system.membus.snoop_fanout::mean 0 # Request fanout histogram 718system.membus.snoop_fanout::stdev 0 # Request fanout histogram 719system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 720system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 721system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 722system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 723system.membus.snoop_fanout::min_value 0 # Request fanout histogram 724system.membus.snoop_fanout::max_value 0 # Request fanout histogram 725system.membus.snoop_fanout::total 446 # Request fanout histogram 726system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) 727system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 728system.membus.respLayer0.occupancy 2375750 # Layer occupancy (ticks) 729system.membus.respLayer0.utilization 3.8 # Layer utilization (%) 730 731---------- End Simulation Statistics ---------- 732