1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred 68cacheStorePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu.interrupts 101isa=system.cpu.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numPhysVecRegs=256 115numROBEntries=192 116numRobs=1 117numThreads=1 118p_state_clk_gate_bins=20 119p_state_clk_gate_max=1000000000000 120p_state_clk_gate_min=1000 121power_model=Null 122profile=0 123progress_interval=0 124renameToDecodeDelay=1 125renameToFetchDelay=1 126renameToIEWDelay=2 127renameToROBDelay=1 128renameWidth=8 129simpoint_start_insts= 130smtCommitPolicy=RoundRobin 131smtFetchPolicy=SingleThread 132smtIQPolicy=Partitioned 133smtIQThreshold=100 134smtLSQPolicy=Partitioned 135smtLSQThreshold=100 136smtNumFetchingThreads=1 137smtROBPolicy=Partitioned 138smtROBThreshold=100 139socket_id=0 140squashWidth=8 141store_set_clear_period=250000 142switched_out=false 143syscallRetryLatency=10000 144system=system 145tracer=system.cpu.tracer 146trapLatency=13 147wait_for_remote_gdb=false 148wbWidth=8 149workload=system.cpu.workload 150dcache_port=system.cpu.dcache.cpu_side 151icache_port=system.cpu.icache.cpu_side 152 153[system.cpu.branchPred] 154type=TournamentBP 155BTBEntries=4096 156BTBTagSize=16 157RASSize=16 158choiceCtrBits=2 159choicePredictorSize=8192 160eventq_index=0 161globalCtrBits=2 162globalPredictorSize=8192 163indirectHashGHR=true 164indirectHashTargets=true 165indirectPathLength=3 166indirectSets=256 167indirectTagSize=16 168indirectWays=2 169instShiftAmt=2 170localCtrBits=2 171localHistoryTableSize=2048 172localPredictorSize=2048 173numThreads=1 174useIndirect=true 175 176[system.cpu.dcache] 177type=Cache 178children=tags 179addr_ranges=0:18446744073709551615:0:0:0:0 180assoc=2 181clk_domain=system.cpu_clk_domain 182clusivity=mostly_incl 183data_latency=2 184default_p_state=UNDEFINED 185demand_mshr_reserve=1 186eventq_index=0 187is_read_only=false 188max_miss_count=0 189mshrs=4 190p_state_clk_gate_bins=20 191p_state_clk_gate_max=1000000000000 192p_state_clk_gate_min=1000 193power_model=Null 194prefetch_on_access=false 195prefetcher=Null 196response_latency=2 197sequential_access=false 198size=262144 199system=system 200tag_latency=2 201tags=system.cpu.dcache.tags 202tgts_per_mshr=20 203write_buffers=8 204writeback_clean=false 205cpu_side=system.cpu.dcache_port 206mem_side=system.cpu.toL2Bus.slave[1] 207 208[system.cpu.dcache.tags] 209type=LRU 210assoc=2 211block_size=64 212clk_domain=system.cpu_clk_domain 213data_latency=2 214default_p_state=UNDEFINED 215eventq_index=0 216p_state_clk_gate_bins=20 217p_state_clk_gate_max=1000000000000 218p_state_clk_gate_min=1000 219power_model=Null 220sequential_access=false 221size=262144 222tag_latency=2 223 224[system.cpu.dtb] 225type=RiscvTLB 226eventq_index=0 227size=64 228 229[system.cpu.fuPool] 230type=FUPool 231children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 232FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 233eventq_index=0 234 235[system.cpu.fuPool.FUList0] 236type=FUDesc 237children=opList 238count=6 239eventq_index=0 240opList=system.cpu.fuPool.FUList0.opList 241 242[system.cpu.fuPool.FUList0.opList] 243type=OpDesc 244eventq_index=0 245opClass=IntAlu 246opLat=1 247pipelined=true 248 249[system.cpu.fuPool.FUList1] 250type=FUDesc 251children=opList0 opList1 252count=2 253eventq_index=0 254opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 255 256[system.cpu.fuPool.FUList1.opList0] 257type=OpDesc 258eventq_index=0 259opClass=IntMult 260opLat=3 261pipelined=true 262 263[system.cpu.fuPool.FUList1.opList1] 264type=OpDesc 265eventq_index=0 266opClass=IntDiv 267opLat=20 268pipelined=false 269 270[system.cpu.fuPool.FUList2] 271type=FUDesc 272children=opList0 opList1 opList2 273count=4 274eventq_index=0 275opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 276 277[system.cpu.fuPool.FUList2.opList0] 278type=OpDesc 279eventq_index=0 280opClass=FloatAdd 281opLat=2 282pipelined=true 283 284[system.cpu.fuPool.FUList2.opList1] 285type=OpDesc 286eventq_index=0 287opClass=FloatCmp 288opLat=2 289pipelined=true 290 291[system.cpu.fuPool.FUList2.opList2] 292type=OpDesc 293eventq_index=0 294opClass=FloatCvt 295opLat=2 296pipelined=true 297 298[system.cpu.fuPool.FUList3] 299type=FUDesc 300children=opList0 opList1 opList2 opList3 opList4 301count=2 302eventq_index=0 303opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 304 305[system.cpu.fuPool.FUList3.opList0] 306type=OpDesc 307eventq_index=0 308opClass=FloatMult 309opLat=4 310pipelined=true 311 312[system.cpu.fuPool.FUList3.opList1] 313type=OpDesc 314eventq_index=0 315opClass=FloatMultAcc 316opLat=5 317pipelined=true 318 319[system.cpu.fuPool.FUList3.opList2] 320type=OpDesc 321eventq_index=0 322opClass=FloatMisc 323opLat=3 324pipelined=true 325 326[system.cpu.fuPool.FUList3.opList3] 327type=OpDesc 328eventq_index=0 329opClass=FloatDiv 330opLat=12 331pipelined=false 332 333[system.cpu.fuPool.FUList3.opList4] 334type=OpDesc 335eventq_index=0 336opClass=FloatSqrt 337opLat=24 338pipelined=false 339 340[system.cpu.fuPool.FUList4] 341type=FUDesc 342children=opList0 opList1 343count=0 344eventq_index=0 345opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 346 347[system.cpu.fuPool.FUList4.opList0] 348type=OpDesc 349eventq_index=0 350opClass=MemRead 351opLat=1 352pipelined=true 353 354[system.cpu.fuPool.FUList4.opList1] 355type=OpDesc 356eventq_index=0 357opClass=FloatMemRead 358opLat=1 359pipelined=true 360 361[system.cpu.fuPool.FUList5] 362type=FUDesc 363children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 364count=4 365eventq_index=0 366opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 367 368[system.cpu.fuPool.FUList5.opList00] 369type=OpDesc 370eventq_index=0 371opClass=SimdAdd 372opLat=1 373pipelined=true 374 375[system.cpu.fuPool.FUList5.opList01] 376type=OpDesc 377eventq_index=0 378opClass=SimdAddAcc 379opLat=1 380pipelined=true 381 382[system.cpu.fuPool.FUList5.opList02] 383type=OpDesc 384eventq_index=0 385opClass=SimdAlu 386opLat=1 387pipelined=true 388 389[system.cpu.fuPool.FUList5.opList03] 390type=OpDesc 391eventq_index=0 392opClass=SimdCmp 393opLat=1 394pipelined=true 395 396[system.cpu.fuPool.FUList5.opList04] 397type=OpDesc 398eventq_index=0 399opClass=SimdCvt 400opLat=1 401pipelined=true 402 403[system.cpu.fuPool.FUList5.opList05] 404type=OpDesc 405eventq_index=0 406opClass=SimdMisc 407opLat=1 408pipelined=true 409 410[system.cpu.fuPool.FUList5.opList06] 411type=OpDesc 412eventq_index=0 413opClass=SimdMult 414opLat=1 415pipelined=true 416 417[system.cpu.fuPool.FUList5.opList07] 418type=OpDesc 419eventq_index=0 420opClass=SimdMultAcc 421opLat=1 422pipelined=true 423 424[system.cpu.fuPool.FUList5.opList08] 425type=OpDesc 426eventq_index=0 427opClass=SimdShift 428opLat=1 429pipelined=true 430 431[system.cpu.fuPool.FUList5.opList09] 432type=OpDesc 433eventq_index=0 434opClass=SimdShiftAcc 435opLat=1 436pipelined=true 437 438[system.cpu.fuPool.FUList5.opList10] 439type=OpDesc 440eventq_index=0 441opClass=SimdSqrt 442opLat=1 443pipelined=true 444 445[system.cpu.fuPool.FUList5.opList11] 446type=OpDesc 447eventq_index=0 448opClass=SimdFloatAdd 449opLat=1 450pipelined=true 451 452[system.cpu.fuPool.FUList5.opList12] 453type=OpDesc 454eventq_index=0 455opClass=SimdFloatAlu 456opLat=1 457pipelined=true 458 459[system.cpu.fuPool.FUList5.opList13] 460type=OpDesc 461eventq_index=0 462opClass=SimdFloatCmp 463opLat=1 464pipelined=true 465 466[system.cpu.fuPool.FUList5.opList14] 467type=OpDesc 468eventq_index=0 469opClass=SimdFloatCvt 470opLat=1 471pipelined=true 472 473[system.cpu.fuPool.FUList5.opList15] 474type=OpDesc 475eventq_index=0 476opClass=SimdFloatDiv 477opLat=1 478pipelined=true 479 480[system.cpu.fuPool.FUList5.opList16] 481type=OpDesc 482eventq_index=0 483opClass=SimdFloatMisc 484opLat=1 485pipelined=true 486 487[system.cpu.fuPool.FUList5.opList17] 488type=OpDesc 489eventq_index=0 490opClass=SimdFloatMult 491opLat=1 492pipelined=true 493 494[system.cpu.fuPool.FUList5.opList18] 495type=OpDesc 496eventq_index=0 497opClass=SimdFloatMultAcc 498opLat=1 499pipelined=true 500 501[system.cpu.fuPool.FUList5.opList19] 502type=OpDesc 503eventq_index=0 504opClass=SimdFloatSqrt 505opLat=1 506pipelined=true 507 508[system.cpu.fuPool.FUList6] 509type=FUDesc 510children=opList0 opList1 511count=0 512eventq_index=0 513opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 514 515[system.cpu.fuPool.FUList6.opList0] 516type=OpDesc 517eventq_index=0 518opClass=MemWrite 519opLat=1 520pipelined=true 521 522[system.cpu.fuPool.FUList6.opList1] 523type=OpDesc 524eventq_index=0 525opClass=FloatMemWrite 526opLat=1 527pipelined=true 528 529[system.cpu.fuPool.FUList7] 530type=FUDesc 531children=opList0 opList1 opList2 opList3 532count=4 533eventq_index=0 534opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 535 536[system.cpu.fuPool.FUList7.opList0] 537type=OpDesc 538eventq_index=0 539opClass=MemRead 540opLat=1 541pipelined=true 542 543[system.cpu.fuPool.FUList7.opList1] 544type=OpDesc 545eventq_index=0 546opClass=MemWrite 547opLat=1 548pipelined=true 549 550[system.cpu.fuPool.FUList7.opList2] 551type=OpDesc 552eventq_index=0 553opClass=FloatMemRead 554opLat=1 555pipelined=true 556 557[system.cpu.fuPool.FUList7.opList3] 558type=OpDesc 559eventq_index=0 560opClass=FloatMemWrite 561opLat=1 562pipelined=true 563 564[system.cpu.fuPool.FUList8] 565type=FUDesc 566children=opList 567count=1 568eventq_index=0 569opList=system.cpu.fuPool.FUList8.opList 570 571[system.cpu.fuPool.FUList8.opList] 572type=OpDesc 573eventq_index=0 574opClass=IprAccess 575opLat=3 576pipelined=false 577 578[system.cpu.icache] 579type=Cache 580children=tags 581addr_ranges=0:18446744073709551615:0:0:0:0 582assoc=2 583clk_domain=system.cpu_clk_domain 584clusivity=mostly_incl 585data_latency=2 586default_p_state=UNDEFINED 587demand_mshr_reserve=1 588eventq_index=0 589is_read_only=true 590max_miss_count=0 591mshrs=4 592p_state_clk_gate_bins=20 593p_state_clk_gate_max=1000000000000 594p_state_clk_gate_min=1000 595power_model=Null 596prefetch_on_access=false 597prefetcher=Null 598response_latency=2 599sequential_access=false 600size=131072 601system=system 602tag_latency=2 603tags=system.cpu.icache.tags 604tgts_per_mshr=20 605write_buffers=8 606writeback_clean=true 607cpu_side=system.cpu.icache_port 608mem_side=system.cpu.toL2Bus.slave[0] 609 610[system.cpu.icache.tags] 611type=LRU 612assoc=2 613block_size=64 614clk_domain=system.cpu_clk_domain 615data_latency=2 616default_p_state=UNDEFINED 617eventq_index=0 618p_state_clk_gate_bins=20 619p_state_clk_gate_max=1000000000000 620p_state_clk_gate_min=1000 621power_model=Null 622sequential_access=false 623size=131072 624tag_latency=2 625 626[system.cpu.interrupts] 627type=RiscvInterrupts 628eventq_index=0 629 630[system.cpu.isa] 631type=RiscvISA 632eventq_index=0 633 634[system.cpu.itb] 635type=RiscvTLB 636eventq_index=0 637size=64 638 639[system.cpu.l2cache] 640type=Cache 641children=tags 642addr_ranges=0:18446744073709551615:0:0:0:0 643assoc=8 644clk_domain=system.cpu_clk_domain 645clusivity=mostly_incl 646data_latency=20 647default_p_state=UNDEFINED 648demand_mshr_reserve=1 649eventq_index=0 650is_read_only=false 651max_miss_count=0 652mshrs=20 653p_state_clk_gate_bins=20 654p_state_clk_gate_max=1000000000000 655p_state_clk_gate_min=1000 656power_model=Null 657prefetch_on_access=false 658prefetcher=Null 659response_latency=20 660sequential_access=false 661size=2097152 662system=system 663tag_latency=20 664tags=system.cpu.l2cache.tags 665tgts_per_mshr=12 666write_buffers=8 667writeback_clean=false 668cpu_side=system.cpu.toL2Bus.master[0] 669mem_side=system.membus.slave[1] 670 671[system.cpu.l2cache.tags] 672type=LRU 673assoc=8 674block_size=64 675clk_domain=system.cpu_clk_domain 676data_latency=20 677default_p_state=UNDEFINED 678eventq_index=0 679p_state_clk_gate_bins=20 680p_state_clk_gate_max=1000000000000 681p_state_clk_gate_min=1000 682power_model=Null 683sequential_access=false 684size=2097152 685tag_latency=20 686 687[system.cpu.toL2Bus] 688type=CoherentXBar 689children=snoop_filter 690clk_domain=system.cpu_clk_domain 691default_p_state=UNDEFINED 692eventq_index=0 693forward_latency=0 694frontend_latency=1 695p_state_clk_gate_bins=20 696p_state_clk_gate_max=1000000000000 697p_state_clk_gate_min=1000 698point_of_coherency=false 699power_model=Null 700response_latency=1 701snoop_filter=system.cpu.toL2Bus.snoop_filter 702snoop_response_latency=1 703system=system 704use_default_range=false 705width=32 706master=system.cpu.l2cache.cpu_side 707slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 708 709[system.cpu.toL2Bus.snoop_filter] 710type=SnoopFilter 711eventq_index=0 712lookup_latency=0 713max_capacity=8388608 714system=system 715 716[system.cpu.tracer] 717type=ExeTracer 718eventq_index=0 719 720[system.cpu.workload] 721type=Process 722cmd=insttest 723cwd= 724drivers= 725egid=100 726env= 727errout=cerr 728euid=100 729eventq_index=0 730executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest 731gid=100 732input=cin 733kvmInSE=false 734maxStackSize=67108864 735output=cout 736pgid=100 737pid=100 738ppid=0 739simpoint=0 740system=system 741uid=100 742useArchPT=false 743 744[system.cpu_clk_domain] 745type=SrcClockDomain 746clock=500 747domain_id=-1 748eventq_index=0 749init_perf_level=0 750voltage_domain=system.voltage_domain 751 752[system.dvfs_handler] 753type=DVFSHandler 754domains= 755enable=false 756eventq_index=0 757sys_clk_domain=system.clk_domain 758transition_latency=100000000 759 760[system.membus] 761type=CoherentXBar 762children=snoop_filter 763clk_domain=system.clk_domain 764default_p_state=UNDEFINED 765eventq_index=0 766forward_latency=4 767frontend_latency=3 768p_state_clk_gate_bins=20 769p_state_clk_gate_max=1000000000000 770p_state_clk_gate_min=1000 771point_of_coherency=true 772power_model=Null 773response_latency=2 774snoop_filter=system.membus.snoop_filter 775snoop_response_latency=4 776system=system 777use_default_range=false 778width=16 779master=system.physmem.port 780slave=system.system_port system.cpu.l2cache.mem_side 781 782[system.membus.snoop_filter] 783type=SnoopFilter 784eventq_index=0 785lookup_latency=1 786max_capacity=8388608 787system=system 788 789[system.physmem] 790type=DRAMCtrl 791IDD0=0.055000 792IDD02=0.000000 793IDD2N=0.032000 794IDD2N2=0.000000 795IDD2P0=0.000000 796IDD2P02=0.000000 797IDD2P1=0.032000 798IDD2P12=0.000000 799IDD3N=0.038000 800IDD3N2=0.000000 801IDD3P0=0.000000 802IDD3P02=0.000000 803IDD3P1=0.038000 804IDD3P12=0.000000 805IDD4R=0.157000 806IDD4R2=0.000000 807IDD4W=0.125000 808IDD4W2=0.000000 809IDD5=0.235000 810IDD52=0.000000 811IDD6=0.020000 812IDD62=0.000000 813VDD=1.500000 814VDD2=0.000000 815activation_limit=4 816addr_mapping=RoRaBaCoCh 817bank_groups_per_rank=0 818banks_per_rank=8 819burst_length=8 820channels=1 821clk_domain=system.clk_domain 822conf_table_reported=true 823default_p_state=UNDEFINED 824device_bus_width=8 825device_rowbuffer_size=1024 826device_size=536870912 827devices_per_rank=8 828dll=true 829eventq_index=0 830in_addr_map=true 831kvm_map=true 832max_accesses_per_row=16 833mem_sched_policy=frfcfs 834min_writes_per_switch=16 835null=false 836p_state_clk_gate_bins=20 837p_state_clk_gate_max=1000000000000 838p_state_clk_gate_min=1000 839page_policy=open_adaptive 840power_model=Null 841range=0:134217727:0:0:0:0 842ranks_per_channel=2 843read_buffer_size=32 844static_backend_latency=10000 845static_frontend_latency=10000 846tBURST=5000 847tCCD_L=0 848tCK=1250 849tCL=13750 850tCS=2500 851tRAS=35000 852tRCD=13750 853tREFI=7800000 854tRFC=260000 855tRP=13750 856tRRD=6000 857tRRD_L=0 858tRTP=7500 859tRTW=2500 860tWR=15000 861tWTR=7500 862tXAW=30000 863tXP=6000 864tXPDLL=0 865tXS=270000 866tXSDLL=0 867write_buffer_size=64 868write_high_thresh_perc=85 869write_low_thresh_perc=50 870port=system.membus.master[0] 871 872[system.voltage_domain] 873type=VoltageDomain 874eventq_index=0 875voltage=1.000000 876 877