config.ini revision 11268:8b4b55d79ddd
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27multi_thread=false 28num_work_ids=16 29readfile= 30symbolfile= 31work_begin_ckpt_count=0 32work_begin_cpu_id_exit=-1 33work_begin_exit_count=0 34work_cpus_ckpt_count=0 35work_end_ckpt_count=0 36work_end_exit_count=0 37work_item_id=-1 38system_port=system.membus.slave[0] 39 40[system.clk_domain] 41type=SrcClockDomain 42clock=1000 43domain_id=-1 44eventq_index=0 45init_perf_level=0 46voltage_domain=system.voltage_domain 47 48[system.cpu] 49type=DerivO3CPU 50children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55SQEntries=32 56SSITSize=1024 57activity=0 58backComSize=5 59branchPred=system.cpu.branchPred 60cachePorts=200 61checker=Null 62clk_domain=system.cpu_clk_domain 63commitToDecodeDelay=1 64commitToFetchDelay=1 65commitToIEWDelay=1 66commitToRenameDelay=1 67commitWidth=8 68cpu_id=0 69decodeToFetchDelay=1 70decodeToRenameDelay=1 71decodeWidth=8 72dispatchWidth=8 73do_checkpoint_insts=true 74do_quiesce=true 75do_statistics_insts=true 76dtb=system.cpu.dtb 77eventq_index=0 78fetchBufferSize=64 79fetchQueueSize=32 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93issueToExecuteDelay=1 94issueWidth=8 95itb=system.cpu.itb 96max_insts_all_threads=0 97max_insts_any_thread=0 98max_loads_all_threads=0 99max_loads_any_thread=0 100needsTSO=true 101numIQEntries=64 102numPhysCCRegs=1280 103numPhysFloatRegs=256 104numPhysIntRegs=256 105numROBEntries=192 106numRobs=1 107numThreads=1 108profile=0 109progress_interval=0 110renameToDecodeDelay=1 111renameToFetchDelay=1 112renameToIEWDelay=2 113renameToROBDelay=1 114renameWidth=8 115simpoint_start_insts= 116smtCommitPolicy=RoundRobin 117smtFetchPolicy=SingleThread 118smtIQPolicy=Partitioned 119smtIQThreshold=100 120smtLSQPolicy=Partitioned 121smtLSQThreshold=100 122smtNumFetchingThreads=1 123smtROBPolicy=Partitioned 124smtROBThreshold=100 125socket_id=0 126squashWidth=8 127store_set_clear_period=250000 128switched_out=false 129system=system 130tracer=system.cpu.tracer 131trapLatency=13 132wbWidth=8 133workload=system.cpu.workload 134dcache_port=system.cpu.dcache.cpu_side 135icache_port=system.cpu.icache.cpu_side 136 137[system.cpu.apic_clk_domain] 138type=DerivedClockDomain 139clk_divider=16 140clk_domain=system.cpu_clk_domain 141eventq_index=0 142 143[system.cpu.branchPred] 144type=TournamentBP 145BTBEntries=4096 146BTBTagSize=16 147RASSize=16 148choiceCtrBits=2 149choicePredictorSize=8192 150eventq_index=0 151globalCtrBits=2 152globalPredictorSize=8192 153instShiftAmt=2 154localCtrBits=2 155localHistoryTableSize=2048 156localPredictorSize=2048 157numThreads=1 158 159[system.cpu.dcache] 160type=Cache 161children=tags 162addr_ranges=0:18446744073709551615 163assoc=2 164clk_domain=system.cpu_clk_domain 165clusivity=mostly_incl 166demand_mshr_reserve=1 167eventq_index=0 168forward_snoops=true 169hit_latency=2 170is_read_only=false 171max_miss_count=0 172mshrs=4 173prefetch_on_access=false 174prefetcher=Null 175response_latency=2 176sequential_access=false 177size=262144 178system=system 179tags=system.cpu.dcache.tags 180tgts_per_mshr=20 181write_buffers=8 182writeback_clean=false 183cpu_side=system.cpu.dcache_port 184mem_side=system.cpu.toL2Bus.slave[1] 185 186[system.cpu.dcache.tags] 187type=LRU 188assoc=2 189block_size=64 190clk_domain=system.cpu_clk_domain 191eventq_index=0 192hit_latency=2 193sequential_access=false 194size=262144 195 196[system.cpu.dtb] 197type=X86TLB 198children=walker 199eventq_index=0 200size=64 201walker=system.cpu.dtb.walker 202 203[system.cpu.dtb.walker] 204type=X86PagetableWalker 205clk_domain=system.cpu_clk_domain 206eventq_index=0 207num_squash_per_cycle=4 208system=system 209port=system.cpu.toL2Bus.slave[3] 210 211[system.cpu.fuPool] 212type=FUPool 213children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 214FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 215eventq_index=0 216 217[system.cpu.fuPool.FUList0] 218type=FUDesc 219children=opList 220count=6 221eventq_index=0 222opList=system.cpu.fuPool.FUList0.opList 223 224[system.cpu.fuPool.FUList0.opList] 225type=OpDesc 226eventq_index=0 227opClass=IntAlu 228opLat=1 229pipelined=true 230 231[system.cpu.fuPool.FUList1] 232type=FUDesc 233children=opList0 opList1 234count=2 235eventq_index=0 236opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 237 238[system.cpu.fuPool.FUList1.opList0] 239type=OpDesc 240eventq_index=0 241opClass=IntMult 242opLat=3 243pipelined=true 244 245[system.cpu.fuPool.FUList1.opList1] 246type=OpDesc 247eventq_index=0 248opClass=IntDiv 249opLat=1 250pipelined=false 251 252[system.cpu.fuPool.FUList2] 253type=FUDesc 254children=opList0 opList1 opList2 255count=4 256eventq_index=0 257opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 258 259[system.cpu.fuPool.FUList2.opList0] 260type=OpDesc 261eventq_index=0 262opClass=FloatAdd 263opLat=2 264pipelined=true 265 266[system.cpu.fuPool.FUList2.opList1] 267type=OpDesc 268eventq_index=0 269opClass=FloatCmp 270opLat=2 271pipelined=true 272 273[system.cpu.fuPool.FUList2.opList2] 274type=OpDesc 275eventq_index=0 276opClass=FloatCvt 277opLat=2 278pipelined=true 279 280[system.cpu.fuPool.FUList3] 281type=FUDesc 282children=opList0 opList1 opList2 283count=2 284eventq_index=0 285opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 286 287[system.cpu.fuPool.FUList3.opList0] 288type=OpDesc 289eventq_index=0 290opClass=FloatMult 291opLat=4 292pipelined=true 293 294[system.cpu.fuPool.FUList3.opList1] 295type=OpDesc 296eventq_index=0 297opClass=FloatDiv 298opLat=12 299pipelined=false 300 301[system.cpu.fuPool.FUList3.opList2] 302type=OpDesc 303eventq_index=0 304opClass=FloatSqrt 305opLat=24 306pipelined=false 307 308[system.cpu.fuPool.FUList4] 309type=FUDesc 310children=opList 311count=0 312eventq_index=0 313opList=system.cpu.fuPool.FUList4.opList 314 315[system.cpu.fuPool.FUList4.opList] 316type=OpDesc 317eventq_index=0 318opClass=MemRead 319opLat=1 320pipelined=true 321 322[system.cpu.fuPool.FUList5] 323type=FUDesc 324children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 325count=4 326eventq_index=0 327opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 328 329[system.cpu.fuPool.FUList5.opList00] 330type=OpDesc 331eventq_index=0 332opClass=SimdAdd 333opLat=1 334pipelined=true 335 336[system.cpu.fuPool.FUList5.opList01] 337type=OpDesc 338eventq_index=0 339opClass=SimdAddAcc 340opLat=1 341pipelined=true 342 343[system.cpu.fuPool.FUList5.opList02] 344type=OpDesc 345eventq_index=0 346opClass=SimdAlu 347opLat=1 348pipelined=true 349 350[system.cpu.fuPool.FUList5.opList03] 351type=OpDesc 352eventq_index=0 353opClass=SimdCmp 354opLat=1 355pipelined=true 356 357[system.cpu.fuPool.FUList5.opList04] 358type=OpDesc 359eventq_index=0 360opClass=SimdCvt 361opLat=1 362pipelined=true 363 364[system.cpu.fuPool.FUList5.opList05] 365type=OpDesc 366eventq_index=0 367opClass=SimdMisc 368opLat=1 369pipelined=true 370 371[system.cpu.fuPool.FUList5.opList06] 372type=OpDesc 373eventq_index=0 374opClass=SimdMult 375opLat=1 376pipelined=true 377 378[system.cpu.fuPool.FUList5.opList07] 379type=OpDesc 380eventq_index=0 381opClass=SimdMultAcc 382opLat=1 383pipelined=true 384 385[system.cpu.fuPool.FUList5.opList08] 386type=OpDesc 387eventq_index=0 388opClass=SimdShift 389opLat=1 390pipelined=true 391 392[system.cpu.fuPool.FUList5.opList09] 393type=OpDesc 394eventq_index=0 395opClass=SimdShiftAcc 396opLat=1 397pipelined=true 398 399[system.cpu.fuPool.FUList5.opList10] 400type=OpDesc 401eventq_index=0 402opClass=SimdSqrt 403opLat=1 404pipelined=true 405 406[system.cpu.fuPool.FUList5.opList11] 407type=OpDesc 408eventq_index=0 409opClass=SimdFloatAdd 410opLat=1 411pipelined=true 412 413[system.cpu.fuPool.FUList5.opList12] 414type=OpDesc 415eventq_index=0 416opClass=SimdFloatAlu 417opLat=1 418pipelined=true 419 420[system.cpu.fuPool.FUList5.opList13] 421type=OpDesc 422eventq_index=0 423opClass=SimdFloatCmp 424opLat=1 425pipelined=true 426 427[system.cpu.fuPool.FUList5.opList14] 428type=OpDesc 429eventq_index=0 430opClass=SimdFloatCvt 431opLat=1 432pipelined=true 433 434[system.cpu.fuPool.FUList5.opList15] 435type=OpDesc 436eventq_index=0 437opClass=SimdFloatDiv 438opLat=1 439pipelined=true 440 441[system.cpu.fuPool.FUList5.opList16] 442type=OpDesc 443eventq_index=0 444opClass=SimdFloatMisc 445opLat=1 446pipelined=true 447 448[system.cpu.fuPool.FUList5.opList17] 449type=OpDesc 450eventq_index=0 451opClass=SimdFloatMult 452opLat=1 453pipelined=true 454 455[system.cpu.fuPool.FUList5.opList18] 456type=OpDesc 457eventq_index=0 458opClass=SimdFloatMultAcc 459opLat=1 460pipelined=true 461 462[system.cpu.fuPool.FUList5.opList19] 463type=OpDesc 464eventq_index=0 465opClass=SimdFloatSqrt 466opLat=1 467pipelined=true 468 469[system.cpu.fuPool.FUList6] 470type=FUDesc 471children=opList 472count=0 473eventq_index=0 474opList=system.cpu.fuPool.FUList6.opList 475 476[system.cpu.fuPool.FUList6.opList] 477type=OpDesc 478eventq_index=0 479opClass=MemWrite 480opLat=1 481pipelined=true 482 483[system.cpu.fuPool.FUList7] 484type=FUDesc 485children=opList0 opList1 486count=4 487eventq_index=0 488opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 489 490[system.cpu.fuPool.FUList7.opList0] 491type=OpDesc 492eventq_index=0 493opClass=MemRead 494opLat=1 495pipelined=true 496 497[system.cpu.fuPool.FUList7.opList1] 498type=OpDesc 499eventq_index=0 500opClass=MemWrite 501opLat=1 502pipelined=true 503 504[system.cpu.fuPool.FUList8] 505type=FUDesc 506children=opList 507count=1 508eventq_index=0 509opList=system.cpu.fuPool.FUList8.opList 510 511[system.cpu.fuPool.FUList8.opList] 512type=OpDesc 513eventq_index=0 514opClass=IprAccess 515opLat=3 516pipelined=false 517 518[system.cpu.icache] 519type=Cache 520children=tags 521addr_ranges=0:18446744073709551615 522assoc=2 523clk_domain=system.cpu_clk_domain 524clusivity=mostly_incl 525demand_mshr_reserve=1 526eventq_index=0 527forward_snoops=true 528hit_latency=2 529is_read_only=true 530max_miss_count=0 531mshrs=4 532prefetch_on_access=false 533prefetcher=Null 534response_latency=2 535sequential_access=false 536size=131072 537system=system 538tags=system.cpu.icache.tags 539tgts_per_mshr=20 540write_buffers=8 541writeback_clean=true 542cpu_side=system.cpu.icache_port 543mem_side=system.cpu.toL2Bus.slave[0] 544 545[system.cpu.icache.tags] 546type=LRU 547assoc=2 548block_size=64 549clk_domain=system.cpu_clk_domain 550eventq_index=0 551hit_latency=2 552sequential_access=false 553size=131072 554 555[system.cpu.interrupts] 556type=X86LocalApic 557clk_domain=system.cpu.apic_clk_domain 558eventq_index=0 559int_latency=1000 560pio_addr=2305843009213693952 561pio_latency=100000 562system=system 563int_master=system.membus.slave[2] 564int_slave=system.membus.master[2] 565pio=system.membus.master[1] 566 567[system.cpu.isa] 568type=X86ISA 569eventq_index=0 570 571[system.cpu.itb] 572type=X86TLB 573children=walker 574eventq_index=0 575size=64 576walker=system.cpu.itb.walker 577 578[system.cpu.itb.walker] 579type=X86PagetableWalker 580clk_domain=system.cpu_clk_domain 581eventq_index=0 582num_squash_per_cycle=4 583system=system 584port=system.cpu.toL2Bus.slave[2] 585 586[system.cpu.l2cache] 587type=Cache 588children=tags 589addr_ranges=0:18446744073709551615 590assoc=8 591clk_domain=system.cpu_clk_domain 592clusivity=mostly_incl 593demand_mshr_reserve=1 594eventq_index=0 595forward_snoops=true 596hit_latency=20 597is_read_only=false 598max_miss_count=0 599mshrs=20 600prefetch_on_access=false 601prefetcher=Null 602response_latency=20 603sequential_access=false 604size=2097152 605system=system 606tags=system.cpu.l2cache.tags 607tgts_per_mshr=12 608write_buffers=8 609writeback_clean=false 610cpu_side=system.cpu.toL2Bus.master[0] 611mem_side=system.membus.slave[1] 612 613[system.cpu.l2cache.tags] 614type=LRU 615assoc=8 616block_size=64 617clk_domain=system.cpu_clk_domain 618eventq_index=0 619hit_latency=20 620sequential_access=false 621size=2097152 622 623[system.cpu.toL2Bus] 624type=CoherentXBar 625children=snoop_filter 626clk_domain=system.cpu_clk_domain 627eventq_index=0 628forward_latency=0 629frontend_latency=1 630response_latency=1 631snoop_filter=system.cpu.toL2Bus.snoop_filter 632snoop_response_latency=1 633system=system 634use_default_range=false 635width=32 636master=system.cpu.l2cache.cpu_side 637slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 638 639[system.cpu.toL2Bus.snoop_filter] 640type=SnoopFilter 641eventq_index=0 642lookup_latency=0 643max_capacity=8388608 644system=system 645 646[system.cpu.tracer] 647type=ExeTracer 648eventq_index=0 649 650[system.cpu.workload] 651type=LiveProcess 652cmd=hello 653cwd= 654drivers= 655egid=100 656env= 657errout=cerr 658euid=100 659eventq_index=0 660executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello 661gid=100 662input=cin 663kvmInSE=false 664max_stack_size=67108864 665output=cout 666pid=100 667ppid=99 668simpoint=0 669system=system 670uid=100 671useArchPT=false 672 673[system.cpu_clk_domain] 674type=SrcClockDomain 675clock=500 676domain_id=-1 677eventq_index=0 678init_perf_level=0 679voltage_domain=system.voltage_domain 680 681[system.dvfs_handler] 682type=DVFSHandler 683domains= 684enable=false 685eventq_index=0 686sys_clk_domain=system.clk_domain 687transition_latency=100000000 688 689[system.membus] 690type=CoherentXBar 691clk_domain=system.clk_domain 692eventq_index=0 693forward_latency=4 694frontend_latency=3 695response_latency=2 696snoop_filter=Null 697snoop_response_latency=4 698system=system 699use_default_range=false 700width=16 701master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 702slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 703 704[system.physmem] 705type=DRAMCtrl 706IDD0=0.075000 707IDD02=0.000000 708IDD2N=0.050000 709IDD2N2=0.000000 710IDD2P0=0.000000 711IDD2P02=0.000000 712IDD2P1=0.000000 713IDD2P12=0.000000 714IDD3N=0.057000 715IDD3N2=0.000000 716IDD3P0=0.000000 717IDD3P02=0.000000 718IDD3P1=0.000000 719IDD3P12=0.000000 720IDD4R=0.187000 721IDD4R2=0.000000 722IDD4W=0.165000 723IDD4W2=0.000000 724IDD5=0.220000 725IDD52=0.000000 726IDD6=0.000000 727IDD62=0.000000 728VDD=1.500000 729VDD2=0.000000 730activation_limit=4 731addr_mapping=RoRaBaCoCh 732bank_groups_per_rank=0 733banks_per_rank=8 734burst_length=8 735channels=1 736clk_domain=system.clk_domain 737conf_table_reported=true 738device_bus_width=8 739device_rowbuffer_size=1024 740device_size=536870912 741devices_per_rank=8 742dll=true 743eventq_index=0 744in_addr_map=true 745max_accesses_per_row=16 746mem_sched_policy=frfcfs 747min_writes_per_switch=16 748null=false 749page_policy=open_adaptive 750range=0:134217727 751ranks_per_channel=2 752read_buffer_size=32 753static_backend_latency=10000 754static_frontend_latency=10000 755tBURST=5000 756tCCD_L=0 757tCK=1250 758tCL=13750 759tCS=2500 760tRAS=35000 761tRCD=13750 762tREFI=7800000 763tRFC=260000 764tRP=13750 765tRRD=6000 766tRRD_L=0 767tRTP=7500 768tRTW=2500 769tWR=15000 770tWTR=7500 771tXAW=30000 772tXP=0 773tXPDLL=0 774tXS=0 775tXSDLL=0 776write_buffer_size=64 777write_high_thresh_perc=85 778write_low_thresh_perc=50 779port=system.membus.master[0] 780 781[system.voltage_domain] 782type=VoltageDomain 783eventq_index=0 784voltage=1.000000 785 786