1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23kvm_vm=Null 24load_addr_mask=1099511627775 25load_offset=0 26mem_mode=timing 27mem_ranges= 28memories=system.physmem 29mmap_using_noreserve=false 30multi_thread=false 31num_work_ids=16 32p_state_clk_gate_bins=20 33p_state_clk_gate_max=1000000000000 34p_state_clk_gate_min=1000 35power_model=Null 36readfile= 37symbolfile= 38thermal_components= 39thermal_model=Null 40work_begin_ckpt_count=0 41work_begin_cpu_id_exit=-1 42work_begin_exit_count=0 43work_cpus_ckpt_count=0 44work_end_ckpt_count=0 45work_end_exit_count=0 46work_item_id=-1 47system_port=system.membus.slave[0] 48 49[system.clk_domain] 50type=SrcClockDomain 51clock=1000 52domain_id=-1 53eventq_index=0 54init_perf_level=0 55voltage_domain=system.voltage_domain 56 57[system.cpu] 58type=DerivO3CPU 59children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 60LFSTSize=1024 61LQEntries=32 62LSQCheckLoads=true 63LSQDepCheckShift=4 64SQEntries=32 65SSITSize=1024 66activity=0 67backComSize=5 68branchPred=system.cpu.branchPred 69cacheStorePorts=200 70checker=Null 71clk_domain=system.cpu_clk_domain 72commitToDecodeDelay=1 73commitToFetchDelay=1 74commitToIEWDelay=1 75commitToRenameDelay=1 76commitWidth=8 77cpu_id=0 78decodeToFetchDelay=1 79decodeToRenameDelay=1 80decodeWidth=8 81default_p_state=UNDEFINED 82dispatchWidth=8 83do_checkpoint_insts=true 84do_quiesce=true 85do_statistics_insts=true 86dtb=system.cpu.dtb 87eventq_index=0 88fetchBufferSize=64 89fetchQueueSize=32 90fetchToDecodeDelay=1 91fetchTrapLatency=1 92fetchWidth=8 93forwardComSize=5 94fuPool=system.cpu.fuPool 95function_trace=false 96function_trace_start=0 97iewToCommitDelay=1 98iewToDecodeDelay=1 99iewToFetchDelay=1 100iewToRenameDelay=1 101interrupts=system.cpu.interrupts 102isa=system.cpu.isa 103issueToExecuteDelay=1 104issueWidth=8 105itb=system.cpu.itb 106max_insts_all_threads=0 107max_insts_any_thread=0 108max_loads_all_threads=0 109max_loads_any_thread=0 110needsTSO=true 111numIQEntries=64 112numPhysCCRegs=1280 113numPhysFloatRegs=256 114numPhysIntRegs=256 115numROBEntries=192 116numRobs=1 117numThreads=1 118p_state_clk_gate_bins=20 119p_state_clk_gate_max=1000000000000 120p_state_clk_gate_min=1000 121power_model=Null 122profile=0 123progress_interval=0 124renameToDecodeDelay=1 125renameToFetchDelay=1 126renameToIEWDelay=2 127renameToROBDelay=1 128renameWidth=8 129simpoint_start_insts= 130smtCommitPolicy=RoundRobin 131smtFetchPolicy=SingleThread 132smtIQPolicy=Partitioned 133smtIQThreshold=100 134smtLSQPolicy=Partitioned 135smtLSQThreshold=100 136smtNumFetchingThreads=1 137smtROBPolicy=Partitioned 138smtROBThreshold=100 139socket_id=0 140squashWidth=8 141store_set_clear_period=250000 142switched_out=false 143syscallRetryLatency=10000 144system=system 145tracer=system.cpu.tracer 146trapLatency=13 147wbWidth=8 148workload=system.cpu.workload 149dcache_port=system.cpu.dcache.cpu_side 150icache_port=system.cpu.icache.cpu_side 151 152[system.cpu.apic_clk_domain] 153type=DerivedClockDomain 154clk_divider=16 155clk_domain=system.cpu_clk_domain 156eventq_index=0 157 158[system.cpu.branchPred] 159type=TournamentBP 160BTBEntries=4096 161BTBTagSize=16 162RASSize=16 163choiceCtrBits=2 164choicePredictorSize=8192 165eventq_index=0 166globalCtrBits=2 167globalPredictorSize=8192 168indirectHashGHR=true 169indirectHashTargets=true 170indirectPathLength=3 171indirectSets=256 172indirectTagSize=16 173indirectWays=2 174instShiftAmt=2 175localCtrBits=2 176localHistoryTableSize=2048 177localPredictorSize=2048 178numThreads=1 179useIndirect=true 180 181[system.cpu.dcache] 182type=Cache 183children=tags 184addr_ranges=0:18446744073709551615:0:0:0:0 185assoc=2 186clk_domain=system.cpu_clk_domain 187clusivity=mostly_incl 188data_latency=2 189default_p_state=UNDEFINED 190demand_mshr_reserve=1 191eventq_index=0 192is_read_only=false 193max_miss_count=0 194mshrs=4 195p_state_clk_gate_bins=20 196p_state_clk_gate_max=1000000000000 197p_state_clk_gate_min=1000 198power_model=Null 199prefetch_on_access=false 200prefetcher=Null 201response_latency=2 202sequential_access=false 203size=262144 204system=system 205tag_latency=2 206tags=system.cpu.dcache.tags 207tgts_per_mshr=20 208write_buffers=8 209writeback_clean=false 210cpu_side=system.cpu.dcache_port 211mem_side=system.cpu.toL2Bus.slave[1] 212 213[system.cpu.dcache.tags] 214type=LRU 215assoc=2 216block_size=64 217clk_domain=system.cpu_clk_domain 218data_latency=2 219default_p_state=UNDEFINED 220eventq_index=0 221p_state_clk_gate_bins=20 222p_state_clk_gate_max=1000000000000 223p_state_clk_gate_min=1000 224power_model=Null 225sequential_access=false 226size=262144 227tag_latency=2 228 229[system.cpu.dtb] 230type=X86TLB 231children=walker 232eventq_index=0 233size=64 234walker=system.cpu.dtb.walker 235 236[system.cpu.dtb.walker] 237type=X86PagetableWalker 238clk_domain=system.cpu_clk_domain 239default_p_state=UNDEFINED 240eventq_index=0 241num_squash_per_cycle=4 242p_state_clk_gate_bins=20 243p_state_clk_gate_max=1000000000000 244p_state_clk_gate_min=1000 245power_model=Null 246system=system 247port=system.cpu.toL2Bus.slave[3] 248 249[system.cpu.fuPool] 250type=FUPool 251children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 252FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 253eventq_index=0 254 255[system.cpu.fuPool.FUList0] 256type=FUDesc 257children=opList 258count=6 259eventq_index=0 260opList=system.cpu.fuPool.FUList0.opList 261 262[system.cpu.fuPool.FUList0.opList] 263type=OpDesc 264eventq_index=0 265opClass=IntAlu 266opLat=1 267pipelined=true 268 269[system.cpu.fuPool.FUList1] 270type=FUDesc 271children=opList0 opList1 272count=2 273eventq_index=0 274opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 275 276[system.cpu.fuPool.FUList1.opList0] 277type=OpDesc 278eventq_index=0 279opClass=IntMult 280opLat=3 281pipelined=true 282 283[system.cpu.fuPool.FUList1.opList1] 284type=OpDesc 285eventq_index=0 286opClass=IntDiv 287opLat=1 288pipelined=false 289 290[system.cpu.fuPool.FUList2] 291type=FUDesc 292children=opList0 opList1 opList2 293count=4 294eventq_index=0 295opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 296 297[system.cpu.fuPool.FUList2.opList0] 298type=OpDesc 299eventq_index=0 300opClass=FloatAdd 301opLat=2 302pipelined=true 303 304[system.cpu.fuPool.FUList2.opList1] 305type=OpDesc 306eventq_index=0 307opClass=FloatCmp 308opLat=2 309pipelined=true 310 311[system.cpu.fuPool.FUList2.opList2] 312type=OpDesc 313eventq_index=0 314opClass=FloatCvt 315opLat=2 316pipelined=true 317 318[system.cpu.fuPool.FUList3] 319type=FUDesc 320children=opList0 opList1 opList2 opList3 opList4 321count=2 322eventq_index=0 323opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 324 325[system.cpu.fuPool.FUList3.opList0] 326type=OpDesc 327eventq_index=0 328opClass=FloatMult 329opLat=4 330pipelined=true 331 332[system.cpu.fuPool.FUList3.opList1] 333type=OpDesc 334eventq_index=0 335opClass=FloatMultAcc 336opLat=5 337pipelined=true 338 339[system.cpu.fuPool.FUList3.opList2] 340type=OpDesc 341eventq_index=0 342opClass=FloatMisc 343opLat=3 344pipelined=true 345 346[system.cpu.fuPool.FUList3.opList3] 347type=OpDesc 348eventq_index=0 349opClass=FloatDiv 350opLat=12 351pipelined=false 352 353[system.cpu.fuPool.FUList3.opList4] 354type=OpDesc 355eventq_index=0 356opClass=FloatSqrt 357opLat=24 358pipelined=false 359 360[system.cpu.fuPool.FUList4] 361type=FUDesc 362children=opList0 opList1 363count=0 364eventq_index=0 365opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 366 367[system.cpu.fuPool.FUList4.opList0] 368type=OpDesc 369eventq_index=0 370opClass=MemRead 371opLat=1 372pipelined=true 373 374[system.cpu.fuPool.FUList4.opList1] 375type=OpDesc 376eventq_index=0 377opClass=FloatMemRead 378opLat=1 379pipelined=true 380 381[system.cpu.fuPool.FUList5] 382type=FUDesc 383children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 384count=4 385eventq_index=0 386opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 387 388[system.cpu.fuPool.FUList5.opList00] 389type=OpDesc 390eventq_index=0 391opClass=SimdAdd 392opLat=1 393pipelined=true 394 395[system.cpu.fuPool.FUList5.opList01] 396type=OpDesc 397eventq_index=0 398opClass=SimdAddAcc 399opLat=1 400pipelined=true 401 402[system.cpu.fuPool.FUList5.opList02] 403type=OpDesc 404eventq_index=0 405opClass=SimdAlu 406opLat=1 407pipelined=true 408 409[system.cpu.fuPool.FUList5.opList03] 410type=OpDesc 411eventq_index=0 412opClass=SimdCmp 413opLat=1 414pipelined=true 415 416[system.cpu.fuPool.FUList5.opList04] 417type=OpDesc 418eventq_index=0 419opClass=SimdCvt 420opLat=1 421pipelined=true 422 423[system.cpu.fuPool.FUList5.opList05] 424type=OpDesc 425eventq_index=0 426opClass=SimdMisc 427opLat=1 428pipelined=true 429 430[system.cpu.fuPool.FUList5.opList06] 431type=OpDesc 432eventq_index=0 433opClass=SimdMult 434opLat=1 435pipelined=true 436 437[system.cpu.fuPool.FUList5.opList07] 438type=OpDesc 439eventq_index=0 440opClass=SimdMultAcc 441opLat=1 442pipelined=true 443 444[system.cpu.fuPool.FUList5.opList08] 445type=OpDesc 446eventq_index=0 447opClass=SimdShift 448opLat=1 449pipelined=true 450 451[system.cpu.fuPool.FUList5.opList09] 452type=OpDesc 453eventq_index=0 454opClass=SimdShiftAcc 455opLat=1 456pipelined=true 457 458[system.cpu.fuPool.FUList5.opList10] 459type=OpDesc 460eventq_index=0 461opClass=SimdSqrt 462opLat=1 463pipelined=true 464 465[system.cpu.fuPool.FUList5.opList11] 466type=OpDesc 467eventq_index=0 468opClass=SimdFloatAdd 469opLat=1 470pipelined=true 471 472[system.cpu.fuPool.FUList5.opList12] 473type=OpDesc 474eventq_index=0 475opClass=SimdFloatAlu 476opLat=1 477pipelined=true 478 479[system.cpu.fuPool.FUList5.opList13] 480type=OpDesc 481eventq_index=0 482opClass=SimdFloatCmp 483opLat=1 484pipelined=true 485 486[system.cpu.fuPool.FUList5.opList14] 487type=OpDesc 488eventq_index=0 489opClass=SimdFloatCvt 490opLat=1 491pipelined=true 492 493[system.cpu.fuPool.FUList5.opList15] 494type=OpDesc 495eventq_index=0 496opClass=SimdFloatDiv 497opLat=1 498pipelined=true 499 500[system.cpu.fuPool.FUList5.opList16] 501type=OpDesc 502eventq_index=0 503opClass=SimdFloatMisc 504opLat=1 505pipelined=true 506 507[system.cpu.fuPool.FUList5.opList17] 508type=OpDesc 509eventq_index=0 510opClass=SimdFloatMult 511opLat=1 512pipelined=true 513 514[system.cpu.fuPool.FUList5.opList18] 515type=OpDesc 516eventq_index=0 517opClass=SimdFloatMultAcc 518opLat=1 519pipelined=true 520 521[system.cpu.fuPool.FUList5.opList19] 522type=OpDesc 523eventq_index=0 524opClass=SimdFloatSqrt 525opLat=1 526pipelined=true 527 528[system.cpu.fuPool.FUList6] 529type=FUDesc 530children=opList0 opList1 531count=0 532eventq_index=0 533opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 534 535[system.cpu.fuPool.FUList6.opList0] 536type=OpDesc 537eventq_index=0 538opClass=MemWrite 539opLat=1 540pipelined=true 541 542[system.cpu.fuPool.FUList6.opList1] 543type=OpDesc 544eventq_index=0 545opClass=FloatMemWrite 546opLat=1 547pipelined=true 548 549[system.cpu.fuPool.FUList7] 550type=FUDesc 551children=opList0 opList1 opList2 opList3 552count=4 553eventq_index=0 554opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 555 556[system.cpu.fuPool.FUList7.opList0] 557type=OpDesc 558eventq_index=0 559opClass=MemRead 560opLat=1 561pipelined=true 562 563[system.cpu.fuPool.FUList7.opList1] 564type=OpDesc 565eventq_index=0 566opClass=MemWrite 567opLat=1 568pipelined=true 569 570[system.cpu.fuPool.FUList7.opList2] 571type=OpDesc 572eventq_index=0 573opClass=FloatMemRead 574opLat=1 575pipelined=true 576 577[system.cpu.fuPool.FUList7.opList3] 578type=OpDesc 579eventq_index=0 580opClass=FloatMemWrite 581opLat=1 582pipelined=true 583 584[system.cpu.fuPool.FUList8] 585type=FUDesc 586children=opList 587count=1 588eventq_index=0 589opList=system.cpu.fuPool.FUList8.opList 590 591[system.cpu.fuPool.FUList8.opList] 592type=OpDesc 593eventq_index=0 594opClass=IprAccess 595opLat=3 596pipelined=false 597 598[system.cpu.icache] 599type=Cache 600children=tags 601addr_ranges=0:18446744073709551615:0:0:0:0 602assoc=2 603clk_domain=system.cpu_clk_domain 604clusivity=mostly_incl 605data_latency=2 606default_p_state=UNDEFINED 607demand_mshr_reserve=1 608eventq_index=0 609is_read_only=true 610max_miss_count=0 611mshrs=4 612p_state_clk_gate_bins=20 613p_state_clk_gate_max=1000000000000 614p_state_clk_gate_min=1000 615power_model=Null 616prefetch_on_access=false 617prefetcher=Null 618response_latency=2 619sequential_access=false 620size=131072 621system=system 622tag_latency=2 623tags=system.cpu.icache.tags 624tgts_per_mshr=20 625write_buffers=8 626writeback_clean=true 627cpu_side=system.cpu.icache_port 628mem_side=system.cpu.toL2Bus.slave[0] 629 630[system.cpu.icache.tags] 631type=LRU 632assoc=2 633block_size=64 634clk_domain=system.cpu_clk_domain 635data_latency=2 636default_p_state=UNDEFINED 637eventq_index=0 638p_state_clk_gate_bins=20 639p_state_clk_gate_max=1000000000000 640p_state_clk_gate_min=1000 641power_model=Null 642sequential_access=false 643size=131072 644tag_latency=2 645 646[system.cpu.interrupts] 647type=X86LocalApic 648clk_domain=system.cpu.apic_clk_domain 649default_p_state=UNDEFINED 650eventq_index=0 651int_latency=1000 652p_state_clk_gate_bins=20 653p_state_clk_gate_max=1000000000000 654p_state_clk_gate_min=1000 655pio_addr=2305843009213693952 656pio_latency=100000 657power_model=Null 658system=system 659int_master=system.membus.slave[2] 660int_slave=system.membus.master[2] 661pio=system.membus.master[1] 662 663[system.cpu.isa] 664type=X86ISA 665eventq_index=0 666 667[system.cpu.itb] 668type=X86TLB 669children=walker 670eventq_index=0 671size=64 672walker=system.cpu.itb.walker 673 674[system.cpu.itb.walker] 675type=X86PagetableWalker 676clk_domain=system.cpu_clk_domain 677default_p_state=UNDEFINED 678eventq_index=0 679num_squash_per_cycle=4 680p_state_clk_gate_bins=20 681p_state_clk_gate_max=1000000000000 682p_state_clk_gate_min=1000 683power_model=Null 684system=system 685port=system.cpu.toL2Bus.slave[2] 686 687[system.cpu.l2cache] 688type=Cache 689children=tags 690addr_ranges=0:18446744073709551615:0:0:0:0 691assoc=8 692clk_domain=system.cpu_clk_domain 693clusivity=mostly_incl 694data_latency=20 695default_p_state=UNDEFINED 696demand_mshr_reserve=1 697eventq_index=0 698is_read_only=false 699max_miss_count=0 700mshrs=20 701p_state_clk_gate_bins=20 702p_state_clk_gate_max=1000000000000 703p_state_clk_gate_min=1000 704power_model=Null 705prefetch_on_access=false 706prefetcher=Null 707response_latency=20 708sequential_access=false 709size=2097152 710system=system 711tag_latency=20 712tags=system.cpu.l2cache.tags 713tgts_per_mshr=12 714write_buffers=8 715writeback_clean=false 716cpu_side=system.cpu.toL2Bus.master[0] 717mem_side=system.membus.slave[1] 718 719[system.cpu.l2cache.tags] 720type=LRU 721assoc=8 722block_size=64 723clk_domain=system.cpu_clk_domain 724data_latency=20 725default_p_state=UNDEFINED 726eventq_index=0 727p_state_clk_gate_bins=20 728p_state_clk_gate_max=1000000000000 729p_state_clk_gate_min=1000 730power_model=Null 731sequential_access=false 732size=2097152 733tag_latency=20 734 735[system.cpu.toL2Bus] 736type=CoherentXBar 737children=snoop_filter 738clk_domain=system.cpu_clk_domain 739default_p_state=UNDEFINED 740eventq_index=0 741forward_latency=0 742frontend_latency=1 743p_state_clk_gate_bins=20 744p_state_clk_gate_max=1000000000000 745p_state_clk_gate_min=1000 746point_of_coherency=false 747power_model=Null 748response_latency=1 749snoop_filter=system.cpu.toL2Bus.snoop_filter 750snoop_response_latency=1 751system=system 752use_default_range=false 753width=32 754master=system.cpu.l2cache.cpu_side 755slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 756 757[system.cpu.toL2Bus.snoop_filter] 758type=SnoopFilter 759eventq_index=0 760lookup_latency=0 761max_capacity=8388608 762system=system 763 764[system.cpu.tracer] 765type=ExeTracer 766eventq_index=0 767 768[system.cpu.workload] 769type=Process 770cmd=hello 771cwd= 772drivers= 773egid=100 774env= 775errout=cerr 776euid=100 777eventq_index=0 778executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello 779gid=100 780input=cin 781kvmInSE=false 782maxStackSize=67108864 783output=cout 784pgid=100 785pid=100 786ppid=0 787simpoint=0 788system=system 789uid=100 790useArchPT=false 791 792[system.cpu_clk_domain] 793type=SrcClockDomain 794clock=500 795domain_id=-1 796eventq_index=0 797init_perf_level=0 798voltage_domain=system.voltage_domain 799 800[system.dvfs_handler] 801type=DVFSHandler 802domains= 803enable=false 804eventq_index=0 805sys_clk_domain=system.clk_domain 806transition_latency=100000000 807 808[system.membus] 809type=CoherentXBar 810children=snoop_filter 811clk_domain=system.clk_domain 812default_p_state=UNDEFINED 813eventq_index=0 814forward_latency=4 815frontend_latency=3 816p_state_clk_gate_bins=20 817p_state_clk_gate_max=1000000000000 818p_state_clk_gate_min=1000 819point_of_coherency=true 820power_model=Null 821response_latency=2 822snoop_filter=system.membus.snoop_filter 823snoop_response_latency=4 824system=system 825use_default_range=false 826width=16 827master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 828slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 829 830[system.membus.snoop_filter] 831type=SnoopFilter 832eventq_index=0 833lookup_latency=1 834max_capacity=8388608 835system=system 836 837[system.physmem] 838type=DRAMCtrl 839IDD0=0.055000 840IDD02=0.000000 841IDD2N=0.032000 842IDD2N2=0.000000 843IDD2P0=0.000000 844IDD2P02=0.000000 845IDD2P1=0.032000 846IDD2P12=0.000000 847IDD3N=0.038000 848IDD3N2=0.000000 849IDD3P0=0.000000 850IDD3P02=0.000000 851IDD3P1=0.038000 852IDD3P12=0.000000 853IDD4R=0.157000 854IDD4R2=0.000000 855IDD4W=0.125000 856IDD4W2=0.000000 857IDD5=0.235000 858IDD52=0.000000 859IDD6=0.020000 860IDD62=0.000000 861VDD=1.500000 862VDD2=0.000000 863activation_limit=4 864addr_mapping=RoRaBaCoCh 865bank_groups_per_rank=0 866banks_per_rank=8 867burst_length=8 868channels=1 869clk_domain=system.clk_domain 870conf_table_reported=true 871default_p_state=UNDEFINED 872device_bus_width=8 873device_rowbuffer_size=1024 874device_size=536870912 875devices_per_rank=8 876dll=true 877eventq_index=0 878in_addr_map=true 879kvm_map=true 880max_accesses_per_row=16 881mem_sched_policy=frfcfs 882min_writes_per_switch=16 883null=false 884p_state_clk_gate_bins=20 885p_state_clk_gate_max=1000000000000 886p_state_clk_gate_min=1000 887page_policy=open_adaptive 888power_model=Null 889range=0:134217727:0:0:0:0 890ranks_per_channel=2 891read_buffer_size=32 892static_backend_latency=10000 893static_frontend_latency=10000 894tBURST=5000 895tCCD_L=0 896tCK=1250 897tCL=13750 898tCS=2500 899tRAS=35000 900tRCD=13750 901tREFI=7800000 902tRFC=260000 903tRP=13750 904tRRD=6000 905tRRD_L=0 906tRTP=7500 907tRTW=2500 908tWR=15000 909tWTR=7500 910tXAW=30000 911tXP=6000 912tXPDLL=0 913tXS=270000 914tXSDLL=0 915write_buffer_size=64 916write_high_thresh_perc=85 917write_low_thresh_perc=50 918port=system.membus.master[0] 919 920[system.voltage_domain] 921type=VoltageDomain 922eventq_index=0 923voltage=1.000000 924 925