stats.txt revision 8893:e29c604a2582
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 26361000 # Number of ticks simulated 5final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 29458 # Simulator instruction rate (inst/s) 8host_op_rate 36586 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 169706423 # Simulator tick rate (ticks/s) 10host_mem_usage 223936 # Number of bytes of host memory used 11host_seconds 0.16 # Real time elapsed on the host 12sim_insts 4574 # Number of instructions simulated 13sim_ops 5682 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 22400 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 14400 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 350 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 849740146 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 546261523 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 849740146 # Total bandwidth to/from this memory (bytes/s) 23system.cpu.dtb.inst_hits 0 # ITB inst hits 24system.cpu.dtb.inst_misses 0 # ITB inst misses 25system.cpu.dtb.read_hits 0 # DTB read hits 26system.cpu.dtb.read_misses 0 # DTB read misses 27system.cpu.dtb.write_hits 0 # DTB write hits 28system.cpu.dtb.write_misses 0 # DTB write misses 29system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 30system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 32system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 34system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 35system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 36system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 37system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38system.cpu.dtb.read_accesses 0 # DTB read accesses 39system.cpu.dtb.write_accesses 0 # DTB write accesses 40system.cpu.dtb.inst_accesses 0 # ITB inst accesses 41system.cpu.dtb.hits 0 # DTB hits 42system.cpu.dtb.misses 0 # DTB misses 43system.cpu.dtb.accesses 0 # DTB accesses 44system.cpu.itb.inst_hits 0 # ITB inst hits 45system.cpu.itb.inst_misses 0 # ITB inst misses 46system.cpu.itb.read_hits 0 # DTB read hits 47system.cpu.itb.read_misses 0 # DTB read misses 48system.cpu.itb.write_hits 0 # DTB write hits 49system.cpu.itb.write_misses 0 # DTB write misses 50system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 51system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 53system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 54system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 55system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 56system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 57system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.itb.read_accesses 0 # DTB read accesses 60system.cpu.itb.write_accesses 0 # DTB write accesses 61system.cpu.itb.inst_accesses 0 # ITB inst accesses 62system.cpu.itb.hits 0 # DTB hits 63system.cpu.itb.misses 0 # DTB misses 64system.cpu.itb.accesses 0 # DTB accesses 65system.cpu.workload.num_syscalls 13 # Number of system calls 66system.cpu.numCycles 52722 # number of cpu cycles simulated 67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 69system.cpu.committedInsts 4574 # Number of instructions committed 70system.cpu.committedOps 5682 # Number of ops (including micro ops) committed 71system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses 72system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 73system.cpu.num_func_calls 185 # number of times a function call or return occured 74system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls 75system.cpu.num_int_insts 4985 # number of integer instructions 76system.cpu.num_fp_insts 16 # number of float instructions 77system.cpu.num_int_register_reads 28701 # number of times the integer registers were read 78system.cpu.num_int_register_writes 5345 # number of times the integer registers were written 79system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 80system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 81system.cpu.num_mem_refs 2139 # number of memory refs 82system.cpu.num_load_insts 1201 # Number of load instructions 83system.cpu.num_store_insts 938 # Number of store instructions 84system.cpu.num_idle_cycles 0 # Number of idle cycles 85system.cpu.num_busy_cycles 52722 # Number of busy cycles 86system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 87system.cpu.idle_fraction 0 # Percentage of idle cycles 88system.cpu.icache.replacements 1 # number of replacements 89system.cpu.icache.tagsinuse 114.525744 # Cycle average of tags in use 90system.cpu.icache.total_refs 4373 # Total number of references to valid blocks. 91system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. 92system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks. 93system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 94system.cpu.icache.occ_blocks::cpu.inst 114.525744 # Average occupied blocks per requestor 95system.cpu.icache.occ_percent::cpu.inst 0.055921 # Average percentage of cache occupancy 96system.cpu.icache.occ_percent::total 0.055921 # Average percentage of cache occupancy 97system.cpu.icache.ReadReq_hits::cpu.inst 4373 # number of ReadReq hits 98system.cpu.icache.ReadReq_hits::total 4373 # number of ReadReq hits 99system.cpu.icache.demand_hits::cpu.inst 4373 # number of demand (read+write) hits 100system.cpu.icache.demand_hits::total 4373 # number of demand (read+write) hits 101system.cpu.icache.overall_hits::cpu.inst 4373 # number of overall hits 102system.cpu.icache.overall_hits::total 4373 # number of overall hits 103system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 104system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses 105system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses 106system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses 107system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses 108system.cpu.icache.overall_misses::total 241 # number of overall misses 109system.cpu.icache.ReadReq_miss_latency::cpu.inst 12824000 # number of ReadReq miss cycles 110system.cpu.icache.ReadReq_miss_latency::total 12824000 # number of ReadReq miss cycles 111system.cpu.icache.demand_miss_latency::cpu.inst 12824000 # number of demand (read+write) miss cycles 112system.cpu.icache.demand_miss_latency::total 12824000 # number of demand (read+write) miss cycles 113system.cpu.icache.overall_miss_latency::cpu.inst 12824000 # number of overall miss cycles 114system.cpu.icache.overall_miss_latency::total 12824000 # number of overall miss cycles 115system.cpu.icache.ReadReq_accesses::cpu.inst 4614 # number of ReadReq accesses(hits+misses) 116system.cpu.icache.ReadReq_accesses::total 4614 # number of ReadReq accesses(hits+misses) 117system.cpu.icache.demand_accesses::cpu.inst 4614 # number of demand (read+write) accesses 118system.cpu.icache.demand_accesses::total 4614 # number of demand (read+write) accesses 119system.cpu.icache.overall_accesses::cpu.inst 4614 # number of overall (read+write) accesses 120system.cpu.icache.overall_accesses::total 4614 # number of overall (read+write) accesses 121system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052232 # miss rate for ReadReq accesses 122system.cpu.icache.demand_miss_rate::cpu.inst 0.052232 # miss rate for demand accesses 123system.cpu.icache.overall_miss_rate::cpu.inst 0.052232 # miss rate for overall accesses 124system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency 125system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency 126system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency 127system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 128system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 129system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 130system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 131system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 132system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 133system.cpu.icache.fast_writes 0 # number of fast writes performed 134system.cpu.icache.cache_copies 0 # number of cache copies performed 135system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 136system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 137system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 138system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 139system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 140system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses 141system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12101000 # number of ReadReq MSHR miss cycles 142system.cpu.icache.ReadReq_mshr_miss_latency::total 12101000 # number of ReadReq MSHR miss cycles 143system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 # number of demand (read+write) MSHR miss cycles 144system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles 145system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles 146system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles 147system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for ReadReq accesses 148system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for demand accesses 149system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for overall accesses 150system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency 151system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency 152system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency 153system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 154system.cpu.dcache.replacements 0 # number of replacements 155system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use 156system.cpu.dcache.total_refs 1941 # Total number of references to valid blocks. 157system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 158system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks. 159system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 160system.cpu.dcache.occ_blocks::cpu.data 82.937979 # Average occupied blocks per requestor 161system.cpu.dcache.occ_percent::cpu.data 0.020249 # Average percentage of cache occupancy 162system.cpu.dcache.occ_percent::total 0.020249 # Average percentage of cache occupancy 163system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits 164system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits 165system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 166system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 167system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 168system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 169system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 170system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 171system.cpu.dcache.demand_hits::cpu.data 1919 # number of demand (read+write) hits 172system.cpu.dcache.demand_hits::total 1919 # number of demand (read+write) hits 173system.cpu.dcache.overall_hits::cpu.data 1919 # number of overall hits 174system.cpu.dcache.overall_hits::total 1919 # number of overall hits 175system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses 176system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses 177system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 178system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 179system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses 180system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses 181system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses 182system.cpu.dcache.overall_misses::total 141 # number of overall misses 183system.cpu.dcache.ReadReq_miss_latency::cpu.data 4816000 # number of ReadReq miss cycles 184system.cpu.dcache.ReadReq_miss_latency::total 4816000 # number of ReadReq miss cycles 185system.cpu.dcache.WriteReq_miss_latency::cpu.data 2408000 # number of WriteReq miss cycles 186system.cpu.dcache.WriteReq_miss_latency::total 2408000 # number of WriteReq miss cycles 187system.cpu.dcache.demand_miss_latency::cpu.data 7224000 # number of demand (read+write) miss cycles 188system.cpu.dcache.demand_miss_latency::total 7224000 # number of demand (read+write) miss cycles 189system.cpu.dcache.overall_miss_latency::cpu.data 7224000 # number of overall miss cycles 190system.cpu.dcache.overall_miss_latency::total 7224000 # number of overall miss cycles 191system.cpu.dcache.ReadReq_accesses::cpu.data 1147 # number of ReadReq accesses(hits+misses) 192system.cpu.dcache.ReadReq_accesses::total 1147 # number of ReadReq accesses(hits+misses) 193system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 194system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 195system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 196system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 197system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 198system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 199system.cpu.dcache.demand_accesses::cpu.data 2060 # number of demand (read+write) accesses 200system.cpu.dcache.demand_accesses::total 2060 # number of demand (read+write) accesses 201system.cpu.dcache.overall_accesses::cpu.data 2060 # number of overall (read+write) accesses 202system.cpu.dcache.overall_accesses::total 2060 # number of overall (read+write) accesses 203system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085440 # miss rate for ReadReq accesses 204system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses 205system.cpu.dcache.demand_miss_rate::cpu.data 0.068447 # miss rate for demand accesses 206system.cpu.dcache.overall_miss_rate::cpu.data 0.068447 # miss rate for overall accesses 207system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency 208system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 209system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency 210system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency 211system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 212system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 213system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 214system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 215system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 216system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 217system.cpu.dcache.fast_writes 0 # number of fast writes performed 218system.cpu.dcache.cache_copies 0 # number of cache copies performed 219system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 220system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 221system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 222system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 223system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 224system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 225system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 226system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 227system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles 228system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles 229system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles 230system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles 231system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles 232system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles 233system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles 234system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles 235system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085440 # mshr miss rate for ReadReq accesses 236system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 237system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for demand accesses 238system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for overall accesses 239system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency 240system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 241system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 242system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 243system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 244system.cpu.l2cache.replacements 0 # number of replacements 245system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use 246system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. 247system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. 248system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. 249system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 250system.cpu.l2cache.occ_blocks::cpu.inst 105.806385 # Average occupied blocks per requestor 251system.cpu.l2cache.occ_blocks::cpu.data 48.148099 # Average occupied blocks per requestor 252system.cpu.l2cache.occ_percent::cpu.inst 0.003229 # Average percentage of cache occupancy 253system.cpu.l2cache.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy 254system.cpu.l2cache.occ_percent::total 0.004698 # Average percentage of cache occupancy 255system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 256system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits 257system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits 258system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 259system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 260system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 261system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 262system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits 263system.cpu.l2cache.overall_hits::total 32 # number of overall hits 264system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses 265system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses 266system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses 267system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 268system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 269system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 270system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses 271system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses 272system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses 273system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses 274system.cpu.l2cache.overall_misses::total 350 # number of overall misses 275system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11700000 # number of ReadReq miss cycles 276system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles 277system.cpu.l2cache.ReadReq_miss_latency::total 15964000 # number of ReadReq miss cycles 278system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles 279system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles 280system.cpu.l2cache.demand_miss_latency::cpu.inst 11700000 # number of demand (read+write) miss cycles 281system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles 282system.cpu.l2cache.demand_miss_latency::total 18200000 # number of demand (read+write) miss cycles 283system.cpu.l2cache.overall_miss_latency::cpu.inst 11700000 # number of overall miss cycles 284system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles 285system.cpu.l2cache.overall_miss_latency::total 18200000 # number of overall miss cycles 286system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) 287system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) 288system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) 289system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 290system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 291system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses 292system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 293system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses 294system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses 295system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 296system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses 297system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses 298system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses 299system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 300system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses 301system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses 302system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses 303system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses 304system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 305system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 306system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 307system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 308system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 309system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 310system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 311system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 312system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 313system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 314system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 315system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 316system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 317system.cpu.l2cache.fast_writes 0 # number of fast writes performed 318system.cpu.l2cache.cache_copies 0 # number of cache copies performed 319system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses 320system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses 321system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses 322system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 323system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 324system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 325system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses 326system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 327system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 328system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses 329system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses 330system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles 331system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles 332system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles 333system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles 334system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles 335system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles 336system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles 337system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles 338system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles 339system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles 340system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles 341system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses 342system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses 343system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 344system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses 345system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses 346system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses 347system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses 348system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 349system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 350system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 351system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 352system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 353system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 354system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 355system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 356 357---------- End Simulation Statistics ---------- 358