1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000029 4sim_ticks 28648500 5final_tick 28648500 6sim_freq 1000000000000 7host_inst_rate 277751 8host_op_rate 323869 9host_tick_rate 1739012040 10host_mem_usage 279272 11host_seconds 0.02 12sim_insts 4566 13sim_ops 5330 14system.voltage_domain.voltage 1 15system.clk_domain.clock 1000 16system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 17system.physmem.bytes_read::cpu.inst 14400 18system.physmem.bytes_read::cpu.data 8000 19system.physmem.bytes_read::total 22400 20system.physmem.bytes_inst_read::cpu.inst 14400 21system.physmem.bytes_inst_read::total 14400 22system.physmem.num_reads::cpu.inst 225 23system.physmem.num_reads::cpu.data 125 24system.physmem.num_reads::total 350 25system.physmem.bw_read::cpu.inst 502644117 26system.physmem.bw_read::cpu.data 279246732 27system.physmem.bw_read::total 781890849 28system.physmem.bw_inst_read::cpu.inst 502644117 29system.physmem.bw_inst_read::total 502644117 30system.physmem.bw_total::cpu.inst 502644117 31system.physmem.bw_total::cpu.data 279246732 32system.physmem.bw_total::total 781890849 33system.pwrStateResidencyTicks::UNDEFINED 28648500 34system.cpu_clk_domain.clock 500 35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 44system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 45system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 46system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 47system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 48system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 49system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 52system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 53system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 54system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 55system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 56system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 62system.cpu.dstage2_mmu.stage2_tlb.hits 0 63system.cpu.dstage2_mmu.stage2_tlb.misses 0 64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 66system.cpu.dtb.walker.walks 0 67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 73system.cpu.dtb.walker.walkRequestOrigin::total 0 74system.cpu.dtb.inst_hits 0 75system.cpu.dtb.inst_misses 0 76system.cpu.dtb.read_hits 0 77system.cpu.dtb.read_misses 0 78system.cpu.dtb.write_hits 0 79system.cpu.dtb.write_misses 0 80system.cpu.dtb.flush_tlb 0 81system.cpu.dtb.flush_tlb_mva 0 82system.cpu.dtb.flush_tlb_mva_asid 0 83system.cpu.dtb.flush_tlb_asid 0 84system.cpu.dtb.flush_entries 0 85system.cpu.dtb.align_faults 0 86system.cpu.dtb.prefetch_faults 0 87system.cpu.dtb.domain_faults 0 88system.cpu.dtb.perms_faults 0 89system.cpu.dtb.read_accesses 0 90system.cpu.dtb.write_accesses 0 91system.cpu.dtb.inst_accesses 0 92system.cpu.dtb.hits 0 93system.cpu.dtb.misses 0 94system.cpu.dtb.accesses 0 95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 104system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 105system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 106system.cpu.istage2_mmu.stage2_tlb.read_hits 0 107system.cpu.istage2_mmu.stage2_tlb.read_misses 0 108system.cpu.istage2_mmu.stage2_tlb.write_hits 0 109system.cpu.istage2_mmu.stage2_tlb.write_misses 0 110system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 111system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 114system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 115system.cpu.istage2_mmu.stage2_tlb.align_faults 0 116system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 122system.cpu.istage2_mmu.stage2_tlb.hits 0 123system.cpu.istage2_mmu.stage2_tlb.misses 0 124system.cpu.istage2_mmu.stage2_tlb.accesses 0 125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 126system.cpu.itb.walker.walks 0 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 133system.cpu.itb.walker.walkRequestOrigin::total 0 134system.cpu.itb.inst_hits 0 135system.cpu.itb.inst_misses 0 136system.cpu.itb.read_hits 0 137system.cpu.itb.read_misses 0 138system.cpu.itb.write_hits 0 139system.cpu.itb.write_misses 0 140system.cpu.itb.flush_tlb 0 141system.cpu.itb.flush_tlb_mva 0 142system.cpu.itb.flush_tlb_mva_asid 0 143system.cpu.itb.flush_tlb_asid 0 144system.cpu.itb.flush_entries 0 145system.cpu.itb.align_faults 0 146system.cpu.itb.prefetch_faults 0 147system.cpu.itb.domain_faults 0 148system.cpu.itb.perms_faults 0 149system.cpu.itb.read_accesses 0 150system.cpu.itb.write_accesses 0 151system.cpu.itb.inst_accesses 0 152system.cpu.itb.hits 0 153system.cpu.itb.misses 0 154system.cpu.itb.accesses 0 155system.cpu.workload.numSyscalls 13 156system.cpu.pwrStateResidencyTicks::ON 28648500 157system.cpu.numCycles 57297 158system.cpu.numWorkItemsStarted 0 159system.cpu.numWorkItemsCompleted 0 160system.cpu.committedInsts 4566 161system.cpu.committedOps 5330 162system.cpu.num_int_alu_accesses 4624 163system.cpu.num_fp_alu_accesses 16 164system.cpu.num_func_calls 203 165system.cpu.num_conditional_control_insts 722 166system.cpu.num_int_insts 4624 167system.cpu.num_fp_insts 16 168system.cpu.num_int_register_reads 7538 169system.cpu.num_int_register_writes 2728 170system.cpu.num_fp_register_reads 16 171system.cpu.num_fp_register_writes 0 172system.cpu.num_cc_register_reads 19187 173system.cpu.num_cc_register_writes 2432 174system.cpu.num_mem_refs 1965 175system.cpu.num_load_insts 1027 176system.cpu.num_store_insts 938 177system.cpu.num_idle_cycles 0 178system.cpu.num_busy_cycles 57297 179system.cpu.not_idle_fraction 1 180system.cpu.idle_fraction 0 181system.cpu.Branches 1008 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% 183system.cpu.op_class::IntAlu 3419 63.42% 63.42% 184system.cpu.op_class::IntMult 4 0.07% 63.49% 185system.cpu.op_class::IntDiv 0 0.00% 63.49% 186system.cpu.op_class::FloatAdd 0 0.00% 63.49% 187system.cpu.op_class::FloatCmp 0 0.00% 63.49% 188system.cpu.op_class::FloatCvt 0 0.00% 63.49% 189system.cpu.op_class::FloatMult 0 0.00% 63.49% 190system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% 191system.cpu.op_class::FloatDiv 0 0.00% 63.49% 192system.cpu.op_class::FloatMisc 0 0.00% 63.49% 193system.cpu.op_class::FloatSqrt 0 0.00% 63.49% 194system.cpu.op_class::SimdAdd 0 0.00% 63.49% 195system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% 196system.cpu.op_class::SimdAlu 0 0.00% 63.49% 197system.cpu.op_class::SimdCmp 0 0.00% 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217system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% 218system.cpu.op_class::IprAccess 0 0.00% 100.00% 219system.cpu.op_class::InstPrefetch 0 0.00% 100.00% 220system.cpu.op_class::total 5391 221system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 222system.cpu.dcache.tags.replacements 0 223system.cpu.dcache.tags.tagsinuse 82.616265 224system.cpu.dcache.tags.total_refs 1786 225system.cpu.dcache.tags.sampled_refs 141 226system.cpu.dcache.tags.avg_refs 12.666667 227system.cpu.dcache.tags.warmup_cycle 0 228system.cpu.dcache.tags.occ_blocks::cpu.data 82.616265 229system.cpu.dcache.tags.occ_percent::cpu.data 0.020170 230system.cpu.dcache.tags.occ_percent::total 0.020170 231system.cpu.dcache.tags.occ_task_id_blocks::1024 141 232system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 233system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 234system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 235system.cpu.dcache.tags.tag_accesses 3995 236system.cpu.dcache.tags.data_accesses 3995 237system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28648500 238system.cpu.dcache.ReadReq_hits::cpu.data 894 239system.cpu.dcache.ReadReq_hits::total 894 240system.cpu.dcache.WriteReq_hits::cpu.data 870 241system.cpu.dcache.WriteReq_hits::total 870 242system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 243system.cpu.dcache.LoadLockedReq_hits::total 11 244system.cpu.dcache.StoreCondReq_hits::cpu.data 11 245system.cpu.dcache.StoreCondReq_hits::total 11 246system.cpu.dcache.demand_hits::cpu.data 1764 247system.cpu.dcache.demand_hits::total 1764 248system.cpu.dcache.overall_hits::cpu.data 1764 249system.cpu.dcache.overall_hits::total 1764 250system.cpu.dcache.ReadReq_misses::cpu.data 98 251system.cpu.dcache.ReadReq_misses::total 98 252system.cpu.dcache.WriteReq_misses::cpu.data 43 253system.cpu.dcache.WriteReq_misses::total 43 254system.cpu.dcache.demand_misses::cpu.data 141 255system.cpu.dcache.demand_misses::total 141 256system.cpu.dcache.overall_misses::cpu.data 141 257system.cpu.dcache.overall_misses::total 141 258system.cpu.dcache.ReadReq_miss_latency::cpu.data 5390000 259system.cpu.dcache.ReadReq_miss_latency::total 5390000 260system.cpu.dcache.WriteReq_miss_latency::cpu.data 2709000 261system.cpu.dcache.WriteReq_miss_latency::total 2709000 262system.cpu.dcache.demand_miss_latency::cpu.data 8099000 263system.cpu.dcache.demand_miss_latency::total 8099000 264system.cpu.dcache.overall_miss_latency::cpu.data 8099000 265system.cpu.dcache.overall_miss_latency::total 8099000 266system.cpu.dcache.ReadReq_accesses::cpu.data 992 267system.cpu.dcache.ReadReq_accesses::total 992 268system.cpu.dcache.WriteReq_accesses::cpu.data 913 269system.cpu.dcache.WriteReq_accesses::total 913 270system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 271system.cpu.dcache.LoadLockedReq_accesses::total 11 272system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 273system.cpu.dcache.StoreCondReq_accesses::total 11 274system.cpu.dcache.demand_accesses::cpu.data 1905 275system.cpu.dcache.demand_accesses::total 1905 276system.cpu.dcache.overall_accesses::cpu.data 1905 277system.cpu.dcache.overall_accesses::total 1905 278system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 279system.cpu.dcache.ReadReq_miss_rate::total 0.098790 280system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 281system.cpu.dcache.WriteReq_miss_rate::total 0.047097 282system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 283system.cpu.dcache.demand_miss_rate::total 0.074016 284system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 285system.cpu.dcache.overall_miss_rate::total 0.074016 286system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 287system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 288system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 289system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 290system.cpu.dcache.demand_avg_miss_latency::cpu.data 57439.716312 291system.cpu.dcache.demand_avg_miss_latency::total 57439.716312 292system.cpu.dcache.overall_avg_miss_latency::cpu.data 57439.716312 293system.cpu.dcache.overall_avg_miss_latency::total 57439.716312 294system.cpu.dcache.blocked_cycles::no_mshrs 0 295system.cpu.dcache.blocked_cycles::no_targets 0 296system.cpu.dcache.blocked::no_mshrs 0 297system.cpu.dcache.blocked::no_targets 0 298system.cpu.dcache.avg_blocked_cycles::no_mshrs nan 299system.cpu.dcache.avg_blocked_cycles::no_targets nan 300system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 301system.cpu.dcache.ReadReq_mshr_misses::total 98 302system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 303system.cpu.dcache.WriteReq_mshr_misses::total 43 304system.cpu.dcache.demand_mshr_misses::cpu.data 141 305system.cpu.dcache.demand_mshr_misses::total 141 306system.cpu.dcache.overall_mshr_misses::cpu.data 141 307system.cpu.dcache.overall_mshr_misses::total 141 308system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5292000 309system.cpu.dcache.ReadReq_mshr_miss_latency::total 5292000 310system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2666000 311system.cpu.dcache.WriteReq_mshr_miss_latency::total 2666000 312system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7958000 313system.cpu.dcache.demand_mshr_miss_latency::total 7958000 314system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7958000 315system.cpu.dcache.overall_mshr_miss_latency::total 7958000 316system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 317system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 318system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 319system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 320system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 321system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 322system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 323system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 324system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 325system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 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548system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 549system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 550system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.444444 551system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.444444 552system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 553system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 554system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.444444 555system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 556system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50515.714286 557system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.444444 558system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 559system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50515.714286 560system.cpu.toL2Bus.snoop_filter.tot_requests 383 561system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 562system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 563system.cpu.toL2Bus.snoop_filter.tot_snoops 0 564system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 565system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 566system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 567system.cpu.toL2Bus.trans_dist::ReadResp 339 568system.cpu.toL2Bus.trans_dist::WritebackClean 1 569system.cpu.toL2Bus.trans_dist::ReadExReq 43 570system.cpu.toL2Bus.trans_dist::ReadExResp 43 571system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 572system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 573system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 574system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 575system.cpu.toL2Bus.pkt_count::total 765 576system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 577system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 578system.cpu.toL2Bus.pkt_size::total 24512 579system.cpu.toL2Bus.snoops 0 580system.cpu.toL2Bus.snoopTraffic 0 581system.cpu.toL2Bus.snoop_fanout::samples 382 582system.cpu.toL2Bus.snoop_fanout::mean 0.083770 583system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 584system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% 585system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% 586system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% 587system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% 588system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% 589system.cpu.toL2Bus.snoop_fanout::min_value 0 590system.cpu.toL2Bus.snoop_fanout::max_value 1 591system.cpu.toL2Bus.snoop_fanout::total 382 592system.cpu.toL2Bus.reqLayer0.occupancy 192500 593system.cpu.toL2Bus.reqLayer0.utilization 0.7 594system.cpu.toL2Bus.respLayer0.occupancy 361500 595system.cpu.toL2Bus.respLayer0.utilization 1.3 596system.cpu.toL2Bus.respLayer1.occupancy 211500 597system.cpu.toL2Bus.respLayer1.utilization 0.7 598system.membus.snoop_filter.tot_requests 350 599system.membus.snoop_filter.hit_single_requests 0 600system.membus.snoop_filter.hit_multi_requests 0 601system.membus.snoop_filter.tot_snoops 0 602system.membus.snoop_filter.hit_single_snoops 0 603system.membus.snoop_filter.hit_multi_snoops 0 604system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 605system.membus.trans_dist::ReadResp 307 606system.membus.trans_dist::ReadExReq 43 607system.membus.trans_dist::ReadExResp 43 608system.membus.trans_dist::ReadSharedReq 307 609system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 610system.membus.pkt_count::total 700 611system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 612system.membus.pkt_size::total 22400 613system.membus.snoops 0 614system.membus.snoopTraffic 0 615system.membus.snoop_fanout::samples 350 616system.membus.snoop_fanout::mean 0 617system.membus.snoop_fanout::stdev 0 618system.membus.snoop_fanout::underflows 0 0.00% 0.00% 619system.membus.snoop_fanout::0 350 100.00% 100.00% 620system.membus.snoop_fanout::1 0 0.00% 100.00% 621system.membus.snoop_fanout::overflows 0 0.00% 100.00% 622system.membus.snoop_fanout::min_value 0 623system.membus.snoop_fanout::max_value 0 624system.membus.snoop_fanout::total 350 625system.membus.reqLayer0.occupancy 355500 626system.membus.reqLayer0.utilization 1.2 627system.membus.respLayer1.occupancy 1750000 628system.membus.respLayer1.utilization 6.1 629 630---------- End Simulation Statistics ---------- 631