stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 26361000 # Number of ticks simulated 5final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 20483 # Simulator instruction rate (inst/s) 8host_tick_rate 95024596 # Simulator tick rate (ticks/s) 9host_mem_usage 217432 # Number of bytes of host memory used 10host_seconds 0.28 # Real time elapsed on the host 11sim_insts 5682 # Number of instructions simulated 12system.physmem.bytes_read 22400 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 14400 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 0 # Number of bytes written to this memory 15system.physmem.num_reads 350 # Number of read requests responded to by this memory 16system.physmem.num_writes 0 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 849740146 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 546261523 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_total 849740146 # Total bandwidth to/from this memory (bytes/s) 21system.cpu.dtb.inst_hits 0 # ITB inst hits 22system.cpu.dtb.inst_misses 0 # ITB inst misses 23system.cpu.dtb.read_hits 0 # DTB read hits 24system.cpu.dtb.read_misses 0 # DTB read misses 25system.cpu.dtb.write_hits 0 # DTB write hits 26system.cpu.dtb.write_misses 0 # DTB write misses 27system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 28system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 29system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 30system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 32system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 33system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 34system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 35system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36system.cpu.dtb.read_accesses 0 # DTB read accesses 37system.cpu.dtb.write_accesses 0 # DTB write accesses 38system.cpu.dtb.inst_accesses 0 # ITB inst accesses 39system.cpu.dtb.hits 0 # DTB hits 40system.cpu.dtb.misses 0 # DTB misses 41system.cpu.dtb.accesses 0 # DTB accesses 42system.cpu.itb.inst_hits 0 # ITB inst hits 43system.cpu.itb.inst_misses 0 # ITB inst misses 44system.cpu.itb.read_hits 0 # DTB read hits 45system.cpu.itb.read_misses 0 # DTB read misses 46system.cpu.itb.write_hits 0 # DTB write hits 47system.cpu.itb.write_misses 0 # DTB write misses 48system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 49system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 53system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 54system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 56system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57system.cpu.itb.read_accesses 0 # DTB read accesses 58system.cpu.itb.write_accesses 0 # DTB write accesses 59system.cpu.itb.inst_accesses 0 # ITB inst accesses 60system.cpu.itb.hits 0 # DTB hits 61system.cpu.itb.misses 0 # DTB misses 62system.cpu.itb.accesses 0 # DTB accesses 63system.cpu.workload.num_syscalls 13 # Number of system calls 64system.cpu.numCycles 52722 # number of cpu cycles simulated 65system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 66system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 67system.cpu.num_insts 5682 # Number of instructions executed 68system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses 69system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 70system.cpu.num_func_calls 185 # number of times a function call or return occured 71system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls 72system.cpu.num_int_insts 4985 # number of integer instructions 73system.cpu.num_fp_insts 16 # number of float instructions 74system.cpu.num_int_register_reads 28701 # number of times the integer registers were read 75system.cpu.num_int_register_writes 5345 # number of times the integer registers were written 76system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 77system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 78system.cpu.num_mem_refs 2139 # number of memory refs 79system.cpu.num_load_insts 1201 # Number of load instructions 80system.cpu.num_store_insts 938 # Number of store instructions 81system.cpu.num_idle_cycles 0 # Number of idle cycles 82system.cpu.num_busy_cycles 52722 # Number of busy cycles 83system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 84system.cpu.idle_fraction 0 # Percentage of idle cycles 85system.cpu.icache.replacements 1 # number of replacements 86system.cpu.icache.tagsinuse 114.525744 # Cycle average of tags in use 87system.cpu.icache.total_refs 4373 # Total number of references to valid blocks. 88system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. 89system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks. 90system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 91system.cpu.icache.occ_blocks::0 114.525744 # Average occupied blocks per context 92system.cpu.icache.occ_percent::0 0.055921 # Average percentage of cache occupancy 93system.cpu.icache.ReadReq_hits 4373 # number of ReadReq hits 94system.cpu.icache.demand_hits 4373 # number of demand (read+write) hits 95system.cpu.icache.overall_hits 4373 # number of overall hits 96system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses 97system.cpu.icache.demand_misses 241 # number of demand (read+write) misses 98system.cpu.icache.overall_misses 241 # number of overall misses 99system.cpu.icache.ReadReq_miss_latency 12824000 # number of ReadReq miss cycles 100system.cpu.icache.demand_miss_latency 12824000 # number of demand (read+write) miss cycles 101system.cpu.icache.overall_miss_latency 12824000 # number of overall miss cycles 102system.cpu.icache.ReadReq_accesses 4614 # number of ReadReq accesses(hits+misses) 103system.cpu.icache.demand_accesses 4614 # number of demand (read+write) accesses 104system.cpu.icache.overall_accesses 4614 # number of overall (read+write) accesses 105system.cpu.icache.ReadReq_miss_rate 0.052232 # miss rate for ReadReq accesses 106system.cpu.icache.demand_miss_rate 0.052232 # miss rate for demand accesses 107system.cpu.icache.overall_miss_rate 0.052232 # miss rate for overall accesses 108system.cpu.icache.ReadReq_avg_miss_latency 53211.618257 # average ReadReq miss latency 109system.cpu.icache.demand_avg_miss_latency 53211.618257 # average overall miss latency 110system.cpu.icache.overall_avg_miss_latency 53211.618257 # average overall miss latency 111system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 112system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 113system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 114system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 115system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 116system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 117system.cpu.icache.fast_writes 0 # number of fast writes performed 118system.cpu.icache.cache_copies 0 # number of cache copies performed 119system.cpu.icache.writebacks 0 # number of writebacks 120system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 121system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 122system.cpu.icache.ReadReq_mshr_misses 241 # number of ReadReq MSHR misses 123system.cpu.icache.demand_mshr_misses 241 # number of demand (read+write) MSHR misses 124system.cpu.icache.overall_mshr_misses 241 # number of overall MSHR misses 125system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 126system.cpu.icache.ReadReq_mshr_miss_latency 12101000 # number of ReadReq MSHR miss cycles 127system.cpu.icache.demand_mshr_miss_latency 12101000 # number of demand (read+write) MSHR miss cycles 128system.cpu.icache.overall_mshr_miss_latency 12101000 # number of overall MSHR miss cycles 129system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 130system.cpu.icache.ReadReq_mshr_miss_rate 0.052232 # mshr miss rate for ReadReq accesses 131system.cpu.icache.demand_mshr_miss_rate 0.052232 # mshr miss rate for demand accesses 132system.cpu.icache.overall_mshr_miss_rate 0.052232 # mshr miss rate for overall accesses 133system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257 # average ReadReq mshr miss latency 134system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency 135system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency 136system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 137system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 138system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 139system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 140system.cpu.dcache.replacements 0 # number of replacements 141system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use 142system.cpu.dcache.total_refs 1941 # Total number of references to valid blocks. 143system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 144system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks. 145system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 146system.cpu.dcache.occ_blocks::0 82.937979 # Average occupied blocks per context 147system.cpu.dcache.occ_percent::0 0.020249 # Average percentage of cache occupancy 148system.cpu.dcache.ReadReq_hits 1049 # number of ReadReq hits 149system.cpu.dcache.WriteReq_hits 870 # number of WriteReq hits 150system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits 151system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits 152system.cpu.dcache.demand_hits 1919 # number of demand (read+write) hits 153system.cpu.dcache.overall_hits 1919 # number of overall hits 154system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses 155system.cpu.dcache.WriteReq_misses 43 # number of WriteReq misses 156system.cpu.dcache.demand_misses 141 # number of demand (read+write) misses 157system.cpu.dcache.overall_misses 141 # number of overall misses 158system.cpu.dcache.ReadReq_miss_latency 4816000 # number of ReadReq miss cycles 159system.cpu.dcache.WriteReq_miss_latency 2408000 # number of WriteReq miss cycles 160system.cpu.dcache.demand_miss_latency 7224000 # number of demand (read+write) miss cycles 161system.cpu.dcache.overall_miss_latency 7224000 # number of overall miss cycles 162system.cpu.dcache.ReadReq_accesses 1147 # number of ReadReq accesses(hits+misses) 163system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) 164system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) 165system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) 166system.cpu.dcache.demand_accesses 2060 # number of demand (read+write) accesses 167system.cpu.dcache.overall_accesses 2060 # number of overall (read+write) accesses 168system.cpu.dcache.ReadReq_miss_rate 0.085440 # miss rate for ReadReq accesses 169system.cpu.dcache.WriteReq_miss_rate 0.047097 # miss rate for WriteReq accesses 170system.cpu.dcache.demand_miss_rate 0.068447 # miss rate for demand accesses 171system.cpu.dcache.overall_miss_rate 0.068447 # miss rate for overall accesses 172system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143 # average ReadReq miss latency 173system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency 174system.cpu.dcache.demand_avg_miss_latency 51234.042553 # average overall miss latency 175system.cpu.dcache.overall_avg_miss_latency 51234.042553 # average overall miss latency 176system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 177system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 178system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 179system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 180system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 181system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 182system.cpu.dcache.fast_writes 0 # number of fast writes performed 183system.cpu.dcache.cache_copies 0 # number of cache copies performed 184system.cpu.dcache.writebacks 0 # number of writebacks 185system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 186system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 187system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses 188system.cpu.dcache.WriteReq_mshr_misses 43 # number of WriteReq MSHR misses 189system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses 190system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses 191system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 192system.cpu.dcache.ReadReq_mshr_miss_latency 4522000 # number of ReadReq MSHR miss cycles 193system.cpu.dcache.WriteReq_mshr_miss_latency 2279000 # number of WriteReq MSHR miss cycles 194system.cpu.dcache.demand_mshr_miss_latency 6801000 # number of demand (read+write) MSHR miss cycles 195system.cpu.dcache.overall_mshr_miss_latency 6801000 # number of overall MSHR miss cycles 196system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 197system.cpu.dcache.ReadReq_mshr_miss_rate 0.085440 # mshr miss rate for ReadReq accesses 198system.cpu.dcache.WriteReq_mshr_miss_rate 0.047097 # mshr miss rate for WriteReq accesses 199system.cpu.dcache.demand_mshr_miss_rate 0.068447 # mshr miss rate for demand accesses 200system.cpu.dcache.overall_mshr_miss_rate 0.068447 # mshr miss rate for overall accesses 201system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143 # average ReadReq mshr miss latency 202system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency 203system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency 204system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency 205system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 206system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 207system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 208system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 209system.cpu.l2cache.replacements 0 # number of replacements 210system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use 211system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. 212system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. 213system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. 214system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 215system.cpu.l2cache.occ_blocks::0 153.954484 # Average occupied blocks per context 216system.cpu.l2cache.occ_percent::0 0.004698 # Average percentage of cache occupancy 217system.cpu.l2cache.ReadReq_hits 32 # number of ReadReq hits 218system.cpu.l2cache.demand_hits 32 # number of demand (read+write) hits 219system.cpu.l2cache.overall_hits 32 # number of overall hits 220system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses 221system.cpu.l2cache.ReadExReq_misses 43 # number of ReadExReq misses 222system.cpu.l2cache.demand_misses 350 # number of demand (read+write) misses 223system.cpu.l2cache.overall_misses 350 # number of overall misses 224system.cpu.l2cache.ReadReq_miss_latency 15964000 # number of ReadReq miss cycles 225system.cpu.l2cache.ReadExReq_miss_latency 2236000 # number of ReadExReq miss cycles 226system.cpu.l2cache.demand_miss_latency 18200000 # number of demand (read+write) miss cycles 227system.cpu.l2cache.overall_miss_latency 18200000 # number of overall miss cycles 228system.cpu.l2cache.ReadReq_accesses 339 # number of ReadReq accesses(hits+misses) 229system.cpu.l2cache.ReadExReq_accesses 43 # number of ReadExReq accesses(hits+misses) 230system.cpu.l2cache.demand_accesses 382 # number of demand (read+write) accesses 231system.cpu.l2cache.overall_accesses 382 # number of overall (read+write) accesses 232system.cpu.l2cache.ReadReq_miss_rate 0.905605 # miss rate for ReadReq accesses 233system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 234system.cpu.l2cache.demand_miss_rate 0.916230 # miss rate for demand accesses 235system.cpu.l2cache.overall_miss_rate 0.916230 # miss rate for overall accesses 236system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency 237system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency 238system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency 239system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency 240system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 241system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 242system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 243system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 244system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 245system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 246system.cpu.l2cache.fast_writes 0 # number of fast writes performed 247system.cpu.l2cache.cache_copies 0 # number of cache copies performed 248system.cpu.l2cache.writebacks 0 # number of writebacks 249system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 250system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 251system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses 252system.cpu.l2cache.ReadExReq_mshr_misses 43 # number of ReadExReq MSHR misses 253system.cpu.l2cache.demand_mshr_misses 350 # number of demand (read+write) MSHR misses 254system.cpu.l2cache.overall_mshr_misses 350 # number of overall MSHR misses 255system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 256system.cpu.l2cache.ReadReq_mshr_miss_latency 12280000 # number of ReadReq MSHR miss cycles 257system.cpu.l2cache.ReadExReq_mshr_miss_latency 1720000 # number of ReadExReq MSHR miss cycles 258system.cpu.l2cache.demand_mshr_miss_latency 14000000 # number of demand (read+write) MSHR miss cycles 259system.cpu.l2cache.overall_mshr_miss_latency 14000000 # number of overall MSHR miss cycles 260system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 261system.cpu.l2cache.ReadReq_mshr_miss_rate 0.905605 # mshr miss rate for ReadReq accesses 262system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 263system.cpu.l2cache.demand_mshr_miss_rate 0.916230 # mshr miss rate for demand accesses 264system.cpu.l2cache.overall_mshr_miss_rate 0.916230 # mshr miss rate for overall accesses 265system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency 266system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency 267system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency 268system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency 269system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 270system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 271system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 272system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 273 274---------- End Simulation Statistics ---------- 275