stats.txt revision 7860
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 315416 # Simulator instruction rate (inst/s) 4host_mem_usage 248988 # Number of bytes of host memory used 5host_seconds 0.02 # Real time elapsed on the host 6host_tick_rate 1472008046 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 5563 # Number of instructions simulated 9sim_seconds 0.000026 # Number of seconds simulated 10sim_ticks 26346000 # Number of ticks simulated 11system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) 12system.cpu.dcache.ReadReq_avg_miss_latency 48787.878788 # average ReadReq miss latency 13system.cpu.dcache.ReadReq_avg_mshr_miss_latency 45787.878788 # average ReadReq mshr miss latency 14system.cpu.dcache.ReadReq_hits 1065 # number of ReadReq hits 15system.cpu.dcache.ReadReq_miss_latency 4830000 # number of ReadReq miss cycles 16system.cpu.dcache.ReadReq_miss_rate 0.085052 # miss rate for ReadReq accesses 17system.cpu.dcache.ReadReq_misses 99 # number of ReadReq misses 18system.cpu.dcache.ReadReq_mshr_miss_latency 4533000 # number of ReadReq MSHR miss cycles 19system.cpu.dcache.ReadReq_mshr_miss_rate 0.085052 # mshr miss rate for ReadReq accesses 20system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses 21system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) 22system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency 23system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency 24system.cpu.dcache.WriteReq_hits 881 # number of WriteReq hits 25system.cpu.dcache.WriteReq_miss_latency 2408000 # number of WriteReq miss cycles 26system.cpu.dcache.WriteReq_miss_rate 0.046537 # miss rate for WriteReq accesses 27system.cpu.dcache.WriteReq_misses 43 # number of WriteReq misses 28system.cpu.dcache.WriteReq_mshr_miss_latency 2279000 # number of WriteReq MSHR miss cycles 29system.cpu.dcache.WriteReq_mshr_miss_rate 0.046537 # mshr miss rate for WriteReq accesses 30system.cpu.dcache.WriteReq_mshr_misses 43 # number of WriteReq MSHR misses 31system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 32system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 33system.cpu.dcache.avg_refs 13.704225 # Average number of references to valid blocks. 34system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 35system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 36system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 37system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38system.cpu.dcache.cache_copies 0 # number of cache copies performed 39system.cpu.dcache.demand_accesses 2088 # number of demand (read+write) accesses 40system.cpu.dcache.demand_avg_miss_latency 50971.830986 # average overall miss latency 41system.cpu.dcache.demand_avg_mshr_miss_latency 47971.830986 # average overall mshr miss latency 42system.cpu.dcache.demand_hits 1946 # number of demand (read+write) hits 43system.cpu.dcache.demand_miss_latency 7238000 # number of demand (read+write) miss cycles 44system.cpu.dcache.demand_miss_rate 0.068008 # miss rate for demand accesses 45system.cpu.dcache.demand_misses 142 # number of demand (read+write) misses 46system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 47system.cpu.dcache.demand_mshr_miss_latency 6812000 # number of demand (read+write) MSHR miss cycles 48system.cpu.dcache.demand_mshr_miss_rate 0.068008 # mshr miss rate for demand accesses 49system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses 50system.cpu.dcache.fast_writes 0 # number of fast writes performed 51system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 52system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 53system.cpu.dcache.occ_%::0 0.020405 # Average percentage of cache occupancy 54system.cpu.dcache.occ_blocks::0 83.579331 # Average occupied blocks per context 55system.cpu.dcache.overall_accesses 2088 # number of overall (read+write) accesses 56system.cpu.dcache.overall_avg_miss_latency 50971.830986 # average overall miss latency 57system.cpu.dcache.overall_avg_mshr_miss_latency 47971.830986 # average overall mshr miss latency 58system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 59system.cpu.dcache.overall_hits 1946 # number of overall hits 60system.cpu.dcache.overall_miss_latency 7238000 # number of overall miss cycles 61system.cpu.dcache.overall_miss_rate 0.068008 # miss rate for overall accesses 62system.cpu.dcache.overall_misses 142 # number of overall misses 63system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 64system.cpu.dcache.overall_mshr_miss_latency 6812000 # number of overall MSHR miss cycles 65system.cpu.dcache.overall_mshr_miss_rate 0.068008 # mshr miss rate for overall accesses 66system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses 67system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 68system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 69system.cpu.dcache.replacements 0 # number of replacements 70system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. 71system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 72system.cpu.dcache.tagsinuse 83.579331 # Cycle average of tags in use 73system.cpu.dcache.total_refs 1946 # Total number of references to valid blocks. 74system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 75system.cpu.dcache.writebacks 0 # number of writebacks 76system.cpu.dtb.accesses 0 # DTB accesses 77system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 78system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 79system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 80system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 81system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 82system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 83system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 84system.cpu.dtb.hits 0 # DTB hits 85system.cpu.dtb.inst_accesses 0 # ITB inst accesses 86system.cpu.dtb.inst_hits 0 # ITB inst hits 87system.cpu.dtb.inst_misses 0 # ITB inst misses 88system.cpu.dtb.misses 0 # DTB misses 89system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 90system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 91system.cpu.dtb.read_accesses 0 # DTB read accesses 92system.cpu.dtb.read_hits 0 # DTB read hits 93system.cpu.dtb.read_misses 0 # DTB read misses 94system.cpu.dtb.write_accesses 0 # DTB write accesses 95system.cpu.dtb.write_hits 0 # DTB write hits 96system.cpu.dtb.write_misses 0 # DTB write misses 97system.cpu.icache.ReadReq_accesses 4580 # number of ReadReq accesses(hits+misses) 98system.cpu.icache.ReadReq_avg_miss_latency 53211.618257 # average ReadReq miss latency 99system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257 # average ReadReq mshr miss latency 100system.cpu.icache.ReadReq_hits 4339 # number of ReadReq hits 101system.cpu.icache.ReadReq_miss_latency 12824000 # number of ReadReq miss cycles 102system.cpu.icache.ReadReq_miss_rate 0.052620 # miss rate for ReadReq accesses 103system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses 104system.cpu.icache.ReadReq_mshr_miss_latency 12101000 # number of ReadReq MSHR miss cycles 105system.cpu.icache.ReadReq_mshr_miss_rate 0.052620 # mshr miss rate for ReadReq accesses 106system.cpu.icache.ReadReq_mshr_misses 241 # number of ReadReq MSHR misses 107system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 108system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 109system.cpu.icache.avg_refs 18.004149 # Average number of references to valid blocks. 110system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 111system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 112system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 113system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 114system.cpu.icache.cache_copies 0 # number of cache copies performed 115system.cpu.icache.demand_accesses 4580 # number of demand (read+write) accesses 116system.cpu.icache.demand_avg_miss_latency 53211.618257 # average overall miss latency 117system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency 118system.cpu.icache.demand_hits 4339 # number of demand (read+write) hits 119system.cpu.icache.demand_miss_latency 12824000 # number of demand (read+write) miss cycles 120system.cpu.icache.demand_miss_rate 0.052620 # miss rate for demand accesses 121system.cpu.icache.demand_misses 241 # number of demand (read+write) misses 122system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 123system.cpu.icache.demand_mshr_miss_latency 12101000 # number of demand (read+write) MSHR miss cycles 124system.cpu.icache.demand_mshr_miss_rate 0.052620 # mshr miss rate for demand accesses 125system.cpu.icache.demand_mshr_misses 241 # number of demand (read+write) MSHR misses 126system.cpu.icache.fast_writes 0 # number of fast writes performed 127system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 128system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 129system.cpu.icache.occ_%::0 0.055892 # Average percentage of cache occupancy 130system.cpu.icache.occ_blocks::0 114.467059 # Average occupied blocks per context 131system.cpu.icache.overall_accesses 4580 # number of overall (read+write) accesses 132system.cpu.icache.overall_avg_miss_latency 53211.618257 # average overall miss latency 133system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency 134system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 135system.cpu.icache.overall_hits 4339 # number of overall hits 136system.cpu.icache.overall_miss_latency 12824000 # number of overall miss cycles 137system.cpu.icache.overall_miss_rate 0.052620 # miss rate for overall accesses 138system.cpu.icache.overall_misses 241 # number of overall misses 139system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 140system.cpu.icache.overall_mshr_miss_latency 12101000 # number of overall MSHR miss cycles 141system.cpu.icache.overall_mshr_miss_rate 0.052620 # mshr miss rate for overall accesses 142system.cpu.icache.overall_mshr_misses 241 # number of overall MSHR misses 143system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 144system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 145system.cpu.icache.replacements 1 # number of replacements 146system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. 147system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 148system.cpu.icache.tagsinuse 114.467059 # Cycle average of tags in use 149system.cpu.icache.total_refs 4339 # Total number of references to valid blocks. 150system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 151system.cpu.icache.writebacks 0 # number of writebacks 152system.cpu.idle_fraction 0 # Percentage of idle cycles 153system.cpu.itb.accesses 0 # DTB accesses 154system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 155system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 156system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 157system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 158system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 159system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 160system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 161system.cpu.itb.hits 0 # DTB hits 162system.cpu.itb.inst_accesses 0 # ITB inst accesses 163system.cpu.itb.inst_hits 0 # ITB inst hits 164system.cpu.itb.inst_misses 0 # ITB inst misses 165system.cpu.itb.misses 0 # DTB misses 166system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 167system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 168system.cpu.itb.read_accesses 0 # DTB read accesses 169system.cpu.itb.read_hits 0 # DTB read hits 170system.cpu.itb.read_misses 0 # DTB read misses 171system.cpu.itb.write_accesses 0 # DTB write accesses 172system.cpu.itb.write_hits 0 # DTB write hits 173system.cpu.itb.write_misses 0 # DTB write misses 174system.cpu.l2cache.ReadExReq_accesses 43 # number of ReadExReq accesses(hits+misses) 175system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency 176system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency 177system.cpu.l2cache.ReadExReq_miss_latency 2236000 # number of ReadExReq miss cycles 178system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 179system.cpu.l2cache.ReadExReq_misses 43 # number of ReadExReq misses 180system.cpu.l2cache.ReadExReq_mshr_miss_latency 1720000 # number of ReadExReq MSHR miss cycles 181system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 182system.cpu.l2cache.ReadExReq_mshr_misses 43 # number of ReadExReq MSHR misses 183system.cpu.l2cache.ReadReq_accesses 340 # number of ReadReq accesses(hits+misses) 184system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency 185system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency 186system.cpu.l2cache.ReadReq_hits 33 # number of ReadReq hits 187system.cpu.l2cache.ReadReq_miss_latency 15964000 # number of ReadReq miss cycles 188system.cpu.l2cache.ReadReq_miss_rate 0.902941 # miss rate for ReadReq accesses 189system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses 190system.cpu.l2cache.ReadReq_mshr_miss_latency 12280000 # number of ReadReq MSHR miss cycles 191system.cpu.l2cache.ReadReq_mshr_miss_rate 0.902941 # mshr miss rate for ReadReq accesses 192system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses 193system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 194system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 195system.cpu.l2cache.avg_refs 0.107492 # Average number of references to valid blocks. 196system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 197system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 198system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 199system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 200system.cpu.l2cache.cache_copies 0 # number of cache copies performed 201system.cpu.l2cache.demand_accesses 383 # number of demand (read+write) accesses 202system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency 203system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency 204system.cpu.l2cache.demand_hits 33 # number of demand (read+write) hits 205system.cpu.l2cache.demand_miss_latency 18200000 # number of demand (read+write) miss cycles 206system.cpu.l2cache.demand_miss_rate 0.913838 # miss rate for demand accesses 207system.cpu.l2cache.demand_misses 350 # number of demand (read+write) misses 208system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 209system.cpu.l2cache.demand_mshr_miss_latency 14000000 # number of demand (read+write) MSHR miss cycles 210system.cpu.l2cache.demand_mshr_miss_rate 0.913838 # mshr miss rate for demand accesses 211system.cpu.l2cache.demand_mshr_misses 350 # number of demand (read+write) MSHR misses 212system.cpu.l2cache.fast_writes 0 # number of fast writes performed 213system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 214system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 215system.cpu.l2cache.occ_%::0 0.004696 # Average percentage of cache occupancy 216system.cpu.l2cache.occ_blocks::0 153.883328 # Average occupied blocks per context 217system.cpu.l2cache.overall_accesses 383 # number of overall (read+write) accesses 218system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency 219system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency 220system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 221system.cpu.l2cache.overall_hits 33 # number of overall hits 222system.cpu.l2cache.overall_miss_latency 18200000 # number of overall miss cycles 223system.cpu.l2cache.overall_miss_rate 0.913838 # miss rate for overall accesses 224system.cpu.l2cache.overall_misses 350 # number of overall misses 225system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 226system.cpu.l2cache.overall_mshr_miss_latency 14000000 # number of overall MSHR miss cycles 227system.cpu.l2cache.overall_mshr_miss_rate 0.913838 # mshr miss rate for overall accesses 228system.cpu.l2cache.overall_mshr_misses 350 # number of overall MSHR misses 229system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 230system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 231system.cpu.l2cache.replacements 0 # number of replacements 232system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. 233system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 234system.cpu.l2cache.tagsinuse 153.883328 # Cycle average of tags in use 235system.cpu.l2cache.total_refs 33 # Total number of references to valid blocks. 236system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 237system.cpu.l2cache.writebacks 0 # number of writebacks 238system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 239system.cpu.numCycles 52692 # number of cpu cycles simulated 240system.cpu.num_insts 5563 # Number of instructions executed 241system.cpu.num_refs 2145 # Number of memory references 242system.cpu.workload.PROG:num_syscalls 13 # Number of system calls 243 244---------- End Simulation Statistics ---------- 245