stats.txt revision 9096
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 39096Sandreas.hansson@arm.comsim_seconds 0.000011 # Number of seconds simulated 49096Sandreas.hansson@arm.comsim_ticks 10843000 # Number of ticks simulated 59096Sandreas.hansson@arm.comfinal_tick 10843000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79096Sandreas.hansson@arm.comhost_inst_rate 17631 # Simulator instruction rate (inst/s) 89096Sandreas.hansson@arm.comhost_op_rate 22000 # Simulator op (including micro ops) rate (op/s) 99096Sandreas.hansson@arm.comhost_tick_rate 41635778 # Simulator tick rate (ticks/s) 109096Sandreas.hansson@arm.comhost_mem_usage 232604 # Number of bytes of host memory used 119096Sandreas.hansson@arm.comhost_seconds 0.26 # Real time elapsed on the host 129079SAli.Saidi@ARM.comsim_insts 4591 # Number of instructions simulated 139079SAli.Saidi@ARM.comsim_ops 5729 # Number of ops (including micro ops) simulated 149096Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 159079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory 169096Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25472 # Number of bytes read from this memory 179096Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory 189096Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory 199096Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory 209079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory 219096Sandreas.hansson@arm.comsystem.physmem.num_reads::total 398 # Number of read requests responded to by this memory 229096Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1623167020 # Total read bandwidth from this memory (bytes/s) 239096Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 725998340 # Total read bandwidth from this memory (bytes/s) 249096Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2349165360 # Total read bandwidth from this memory (bytes/s) 259096Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1623167020 # Instruction read bandwidth from this memory (bytes/s) 269096Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1623167020 # Instruction read bandwidth from this memory (bytes/s) 279096Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1623167020 # Total bandwidth to/from this memory (bytes/s) 289096Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 725998340 # Total bandwidth to/from this memory (bytes/s) 299096Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2349165360 # Total bandwidth to/from this memory (bytes/s) 308317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 318317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 328317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 338317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 348317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 358317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 367860SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 377860SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 387860SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 398317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 408317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 418317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 428317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 438317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 448317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 458317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 468317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 478317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 487860SN/Asystem.cpu.dtb.hits 0 # DTB hits 497860SN/Asystem.cpu.dtb.misses 0 # DTB misses 508317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 518317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 528317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 538317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 548317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 558317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 568317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 578317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 588317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 598317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 608317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 618317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 628317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 638317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 648317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 658317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 668317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 678317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 688317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 698317SN/Asystem.cpu.itb.hits 0 # DTB hits 708317SN/Asystem.cpu.itb.misses 0 # DTB misses 718317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 728317SN/Asystem.cpu.workload.num_syscalls 13 # Number of system calls 739096Sandreas.hansson@arm.comsystem.cpu.numCycles 21687 # number of cpu cycles simulated 748317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 758317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 769096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.lookups 2517 # Number of BP lookups 779096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condPredicted 1836 # Number of conditional branches predicted 789096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condIncorrect 456 # Number of conditional branches incorrect 799096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBLookups 1920 # Number of BTB lookups 809096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBHits 676 # Number of BTB hits 818317SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 829096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.usedRAS 253 # Number of times the RAS was used to get a target. 839079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. 849096Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 7080 # Number of cycles fetch is stalled on an Icache miss 859096Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 12862 # Number of instructions fetch has processed 869096Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2517 # Number of branches that fetch encountered 879096Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 929 # Number of branches that fetch has predicted taken 889096Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 2805 # Number of cycles fetch has run and was not squashing or blocked 899096Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1740 # Number of cycles fetch has spent squashing 909096Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 2260 # Number of cycles fetch has spent blocked 919079SAli.Saidi@ARM.comsystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 929096Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 1997 # Number of cache lines fetched 939096Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed 949096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 13334 # Number of instructions fetched each cycle (Total) 959096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.230988 # Number of instructions fetched each cycle (Total) 969096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.652427 # Number of instructions fetched each cycle (Total) 977860SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 989096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 10529 78.96% 78.96% # Number of instructions fetched each cycle (Total) 999096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 255 1.91% 80.88% # Number of instructions fetched each cycle (Total) 1009096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 171 1.28% 82.16% # Number of instructions fetched each cycle (Total) 1019096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 221 1.66% 83.82% # Number of instructions fetched each cycle (Total) 1029096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 220 1.65% 85.47% # Number of instructions fetched each cycle (Total) 1039096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 289 2.17% 87.63% # Number of instructions fetched each cycle (Total) 1049096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 122 0.91% 88.55% # Number of instructions fetched each cycle (Total) 1059096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 119 0.89% 89.44% # Number of instructions fetched each cycle (Total) 1069096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1408 10.56% 100.00% # Number of instructions fetched each cycle (Total) 1077860SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1087860SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1097860SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1109096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 13334 # Number of instructions fetched each cycle (Total) 1119096Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.116060 # Number of branch fetches per cycle 1129096Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.593074 # Number of inst fetches per cycle 1139096Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 7240 # Number of cycles decode is idle 1149096Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 2427 # Number of cycles decode is blocked 1159096Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2551 # Number of cycles decode is running 1169096Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking 1179096Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1028 # Number of cycles decode is squashing 1189096Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 446 # Number of times decode resolved a branch 1199096Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction 1209096Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 14296 # Number of instructions handled by decode 1219096Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 558 # Number of squashed instructions handled by decode 1229096Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1028 # Number of cycles rename is squashing 1239096Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 7514 # Number of cycles rename is idle 1249096Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 500 # Number of cycles rename is blocking 1259096Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 1638 # count of cycles rename stalled for serializing inst 1269096Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2347 # Number of cycles rename is running 1279096Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 307 # Number of cycles rename is unblocking 1289096Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 13390 # Number of instructions processed by rename 1299096Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full 1309096Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 246 # Number of times rename has blocked due to LSQ full 1319096Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 13047 # Number of destination operands rename has renamed 1329096Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 61618 # Number of register rename lookups that rename has made 1339096Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 60098 # Number of integer rename lookups 1349096Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 1520 # Number of floating rename lookups 1359079SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 1369096Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 7374 # Number of HB maps that are undone due to squashing 1379096Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 46 # count of serializing insts renamed 1388911SAli.Saidi@ARM.comsystem.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed 1399096Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 753 # count of insts added to the skid buffer 1409096Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. 1419096Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1819 # Number of stores inserted to the mem dependence unit. 1429096Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. 1439096Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. 1449096Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 11727 # Number of instructions added to the IQ (excludes non-spec) 1459096Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ 1469096Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 9087 # Number of instructions issued 1479096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued 1489096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 5777 # Number of squashed instructions iterated over during squash; mainly for profiling 1499096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 16432 # Number of squashed operands that are examined and possibly removed from graph 1509096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed 1519096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 13334 # Number of insts issued each cycle 1529096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.681491 # Number of insts issued each cycle 1539096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.365437 # Number of insts issued each cycle 1548241SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1559096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 9565 71.73% 71.73% # Number of insts issued each cycle 1569096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1503 11.27% 83.01% # Number of insts issued each cycle 1579096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 815 6.11% 89.12% # Number of insts issued each cycle 1589096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 548 4.11% 93.23% # Number of insts issued each cycle 1599096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 447 3.35% 96.58% # Number of insts issued each cycle 1609096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 275 2.06% 98.64% # Number of insts issued each cycle 1619096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 130 0.97% 99.62% # Number of insts issued each cycle 1629096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 41 0.31% 99.93% # Number of insts issued each cycle 1639096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle 1648241SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1658241SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1668241SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1679096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 13334 # Number of insts issued each cycle 1688317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1699096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 6 2.86% 2.86% # attempts to use FU when none available 1709096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available 1719096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 2.86% # attempts to use FU when none available 1729096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 2.86% # attempts to use FU when none available 1739096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 2.86% # attempts to use FU when none available 1749096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 2.86% # attempts to use FU when none available 1759096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available 1769096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available 1779096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available 1789096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 2.86% # attempts to use FU when none available 1799096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.86% # attempts to use FU when none available 1809096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 2.86% # attempts to use FU when none available 1819096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 2.86% # attempts to use FU when none available 1829096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 2.86% # attempts to use FU when none available 1839096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 2.86% # attempts to use FU when none available 1849096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 2.86% # attempts to use FU when none available 1859096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.86% # attempts to use FU when none available 1869096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 2.86% # attempts to use FU when none available 1879096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.86% # attempts to use FU when none available 1889096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.86% # attempts to use FU when none available 1899096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.86% # attempts to use FU when none available 1909096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.86% # attempts to use FU when none available 1919096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.86% # attempts to use FU when none available 1929096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.86% # attempts to use FU when none available 1939096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.86% # attempts to use FU when none available 1949096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.86% # attempts to use FU when none available 1959096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.86% # attempts to use FU when none available 1969096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.86% # attempts to use FU when none available 1979096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.86% # attempts to use FU when none available 1989096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 142 67.62% 70.48% # attempts to use FU when none available 1999096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 62 29.52% 100.00% # attempts to use FU when none available 2008317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2018317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2028317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 2039096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 5478 60.28% 60.28% # Type of FU issued 2049096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 8 0.09% 60.37% # Type of FU issued 2059096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.37% # Type of FU issued 2069096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.37% # Type of FU issued 2079096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.37% # Type of FU issued 2089096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.37% # Type of FU issued 2099096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.37% # Type of FU issued 2109096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.37% # Type of FU issued 2119096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.37% # Type of FU issued 2129096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.37% # Type of FU issued 2139096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.37% # Type of FU issued 2149096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.37% # Type of FU issued 2159096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.37% # Type of FU issued 2169096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.37% # Type of FU issued 2179096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.37% # Type of FU issued 2189096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.37% # Type of FU issued 2199096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.37% # Type of FU issued 2209096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.37% # Type of FU issued 2219096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.37% # Type of FU issued 2229096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.37% # Type of FU issued 2239096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.37% # Type of FU issued 2249096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.37% # Type of FU issued 2259096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.37% # Type of FU issued 2269096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.37% # Type of FU issued 2279096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.37% # Type of FU issued 2289096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.40% # Type of FU issued 2299096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.40% # Type of FU issued 2309096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.40% # Type of FU issued 2319096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.40% # Type of FU issued 2329096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2349 25.85% 86.26% # Type of FU issued 2339096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1249 13.74% 100.00% # Type of FU issued 2348317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2358317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2369096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 9087 # Type of FU issued 2379096Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.419007 # Inst issue rate 2389096Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 210 # FU busy when requested 2399096Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.023110 # FU busy rate (busy events/executed inst) 2409096Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 31814 # Number of integer instruction queue reads 2419096Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 17497 # Number of integer instruction queue writes 2429096Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 8174 # Number of integer instruction queue wakeup accesses 2438632SN/Asystem.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 2449096Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes 2458317SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 2469096Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 9277 # Number of integer alu accesses 2478632SN/Asystem.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 2489096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores 2498317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2509096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1634 # Number of loads squashed 2519096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 2528844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 2539096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 881 # Number of stores squashed 2548317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2558317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2568632SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2578317SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2588317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2599096Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1028 # Number of cycles IEW is squashing 2609096Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 203 # Number of cycles IEW is blocking 2619096Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking 2629096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 11780 # Number of instructions dispatched to IQ 2639096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 137 # Number of squashed instructions skipped by dispatch 2649096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions 2659096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1819 # Number of dispatched store instructions 2669096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions 2679096Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall 2689096Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall 2698844SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 2709096Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly 2719096Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 334 # Number of branches that were predicted not taken incorrectly 2729096Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 423 # Number of branch mispredicts detected at execute 2739096Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 8660 # Number of executed instructions 2749096Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed 2759096Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 427 # Number of squashed instructions skipped in execute 2768317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2779079SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 2789096Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3344 # number of memory reference insts executed 2799096Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1407 # Number of branches executed 2809096Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1204 # Number of stores executed 2819096Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.399318 # Inst execution rate 2829096Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 8336 # cumulative count of insts sent to commit 2839096Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 8190 # cumulative count of insts written-back 2849096Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 3858 # num instructions producing a value 2859096Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 7806 # num instructions consuming a value 2868317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2879096Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.377646 # insts written-back per cycle 2889096Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.494235 # average fanout of values written-back 2898317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2909079SAli.Saidi@ARM.comsystem.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions 2919079SAli.Saidi@ARM.comsystem.cpu.commit.commitCommittedOps 5729 # The number of committed instructions 2929096Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 6051 # The number of squashed insts skipped by commit 2938632SN/Asystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 2949096Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted 2959096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 12307 # Number of insts commited each cycle 2969096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.465507 # Number of insts commited each cycle 2979096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.263835 # Number of insts commited each cycle 2988317SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2999096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 9888 80.34% 80.34% # Number of insts commited each cycle 3009096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1205 9.79% 90.14% # Number of insts commited each cycle 3019096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 432 3.51% 93.65% # Number of insts commited each cycle 3029096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 264 2.15% 95.79% # Number of insts commited each cycle 3039096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 159 1.29% 97.08% # Number of insts commited each cycle 3049096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 164 1.33% 98.42% # Number of insts commited each cycle 3059096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 55 0.45% 98.86% # Number of insts commited each cycle 3069096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 38 0.31% 99.17% # Number of insts commited each cycle 3079096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 102 0.83% 100.00% # Number of insts commited each cycle 3088317SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 3098317SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 3108317SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 3119096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 12307 # Number of insts commited each cycle 3129079SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 4591 # Number of instructions committed 3139079SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 3148317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 3159079SAli.Saidi@ARM.comsystem.cpu.commit.refs 2138 # Number of memory references committed 3169079SAli.Saidi@ARM.comsystem.cpu.commit.loads 1200 # Number of loads committed 3178317SN/Asystem.cpu.commit.membars 12 # Number of memory barriers committed 3189079SAli.Saidi@ARM.comsystem.cpu.commit.branches 944 # Number of branches committed 3198317SN/Asystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 3209079SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 4976 # Number of committed integer instructions. 3218317SN/Asystem.cpu.commit.function_calls 82 # Number of function calls committed. 3229096Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached 3238317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 3249096Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 23828 # The number of ROB reads 3259096Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 24602 # The number of ROB writes 3269096Sandreas.hansson@arm.comsystem.cpu.timesIdled 202 # Number of times that the entire CPU went into an idle state and unscheduled itself 3279096Sandreas.hansson@arm.comsystem.cpu.idleCycles 8353 # Total number of cycles that the CPU has spent unscheduled due to idling 3289079SAli.Saidi@ARM.comsystem.cpu.committedInsts 4591 # Number of Instructions Simulated 3299079SAli.Saidi@ARM.comsystem.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 3309079SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 4591 # Number of Instructions Simulated 3319096Sandreas.hansson@arm.comsystem.cpu.cpi 4.723807 # CPI: Cycles Per Instruction 3329096Sandreas.hansson@arm.comsystem.cpu.cpi_total 4.723807 # CPI: Total CPI of All Threads 3339096Sandreas.hansson@arm.comsystem.cpu.ipc 0.211694 # IPC: Instructions Per Cycle 3349096Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.211694 # IPC: Total IPC of All Threads 3359096Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 39657 # number of integer regfile reads 3369096Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 8076 # number of integer regfile writes 3378632SN/Asystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 3389096Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 15863 # number of misc regfile reads 3398317SN/Asystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 3409079SAli.Saidi@ARM.comsystem.cpu.icache.replacements 5 # number of replacements 3419096Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 149.186170 # Cycle average of tags in use 3429096Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 1630 # Total number of references to valid blocks. 3438844SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. 3449096Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 5.506757 # Average number of references to valid blocks. 3458317SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3469096Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 149.186170 # Average occupied blocks per requestor 3479096Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.072845 # Average percentage of cache occupancy 3489096Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.072845 # Average percentage of cache occupancy 3499096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1630 # number of ReadReq hits 3509096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1630 # number of ReadReq hits 3519096Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1630 # number of demand (read+write) hits 3529096Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1630 # number of demand (read+write) hits 3539096Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1630 # number of overall hits 3549096Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1630 # number of overall hits 3559096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses 3569096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses 3579096Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses 3589096Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses 3599096Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses 3609096Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 367 # number of overall misses 3619096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 13154000 # number of ReadReq miss cycles 3629096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 13154000 # number of ReadReq miss cycles 3639096Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 13154000 # number of demand (read+write) miss cycles 3649096Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 13154000 # number of demand (read+write) miss cycles 3659096Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 13154000 # number of overall miss cycles 3669096Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 13154000 # number of overall miss cycles 3679096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1997 # number of ReadReq accesses(hits+misses) 3689096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 1997 # number of ReadReq accesses(hits+misses) 3699096Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1997 # number of demand (read+write) accesses 3709096Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 1997 # number of demand (read+write) accesses 3719096Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1997 # number of overall (read+write) accesses 3729096Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 1997 # number of overall (read+write) accesses 3739096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183776 # miss rate for ReadReq accesses 3749096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.183776 # miss rate for ReadReq accesses 3759096Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.183776 # miss rate for demand accesses 3769096Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.183776 # miss rate for demand accesses 3779096Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.183776 # miss rate for overall accesses 3789096Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.183776 # miss rate for overall accesses 3799096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35841.961853 # average ReadReq miss latency 3809096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 35841.961853 # average ReadReq miss latency 3819096Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency 3829096Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 35841.961853 # average overall miss latency 3839096Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency 3849096Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 35841.961853 # average overall miss latency 3858317SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3868317SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3878317SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3888317SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3898983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3908983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3918317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3928317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3939096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits 3949096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 3959096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits 3969096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits 3979096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits 3989096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits 3998844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses 4008844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses 4018844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses 4028844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses 4038844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses 4048844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses 4059096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10405500 # number of ReadReq MSHR miss cycles 4069096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 10405500 # number of ReadReq MSHR miss cycles 4079096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 10405500 # number of demand (read+write) MSHR miss cycles 4089096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 10405500 # number of demand (read+write) MSHR miss cycles 4099096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 10405500 # number of overall MSHR miss cycles 4109096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 10405500 # number of overall MSHR miss cycles 4119096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for ReadReq accesses 4129096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.148222 # mshr miss rate for ReadReq accesses 4139096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for demand accesses 4149096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.148222 # mshr miss rate for demand accesses 4159096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for overall accesses 4169096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.148222 # mshr miss rate for overall accesses 4179096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35153.716216 # average ReadReq mshr miss latency 4189096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35153.716216 # average ReadReq mshr miss latency 4199096Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35153.716216 # average overall mshr miss latency 4209096Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 35153.716216 # average overall mshr miss latency 4219096Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35153.716216 # average overall mshr miss latency 4229096Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 35153.716216 # average overall mshr miss latency 4238317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4248317SN/Asystem.cpu.dcache.replacements 0 # number of replacements 4259096Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 86.628845 # Cycle average of tags in use 4269096Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 2404 # Total number of references to valid blocks. 4278844SAli.Saidi@ARM.comsystem.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. 4289096Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 16.134228 # Average number of references to valid blocks. 4298317SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4309096Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 86.628845 # Average occupied blocks per requestor 4319096Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.021150 # Average percentage of cache occupancy 4329096Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::total 0.021150 # Average percentage of cache occupancy 4339096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits 4349096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits 4359096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 602 # number of WriteReq hits 4369096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 602 # number of WriteReq hits 4379096Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 4389096Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 4398835SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 4408835SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 4419096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2382 # number of demand (read+write) hits 4429096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2382 # number of demand (read+write) hits 4439096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2382 # number of overall hits 4449096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2382 # number of overall hits 4459096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses 4469096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses 4479096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 311 # number of WriteReq misses 4489096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 311 # number of WriteReq misses 4498835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 4508835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 4519096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses 4529096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses 4539096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses 4549096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 501 # number of overall misses 4559096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 6900500 # number of ReadReq miss cycles 4569096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 6900500 # number of ReadReq miss cycles 4579096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 12710500 # number of WriteReq miss cycles 4589096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 12710500 # number of WriteReq miss cycles 4598835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles 4608835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles 4619096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 19611000 # number of demand (read+write) miss cycles 4629096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 19611000 # number of demand (read+write) miss cycles 4639096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 19611000 # number of overall miss cycles 4649096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 19611000 # number of overall miss cycles 4659096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1970 # number of ReadReq accesses(hits+misses) 4669096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1970 # number of ReadReq accesses(hits+misses) 4678835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 4688835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 4699096Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 4709096Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 4718835SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 4728835SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 4739096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2883 # number of demand (read+write) accesses 4749096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2883 # number of demand (read+write) accesses 4759096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2883 # number of overall (read+write) accesses 4769096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2883 # number of overall (read+write) accesses 4779096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096447 # miss rate for ReadReq accesses 4789096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.096447 # miss rate for ReadReq accesses 4799096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.340635 # miss rate for WriteReq accesses 4809096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.340635 # miss rate for WriteReq accesses 4819096Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 4829096Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 4839096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.173777 # miss rate for demand accesses 4849096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.173777 # miss rate for demand accesses 4859096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.173777 # miss rate for overall accesses 4869096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.173777 # miss rate for overall accesses 4879096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36318.421053 # average ReadReq miss latency 4889096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 36318.421053 # average ReadReq miss latency 4899096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40869.774920 # average WriteReq miss latency 4909096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 40869.774920 # average WriteReq miss latency 4918835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency 4929055Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency 4939096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency 4949096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 39143.712575 # average overall miss latency 4959096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency 4969096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 39143.712575 # average overall miss latency 4978317SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4988317SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4998317SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5008317SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 5018983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5028983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5038317SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 5048317SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 5059096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits 5069096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 5079096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 269 # number of WriteReq MSHR hits 5089096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 269 # number of WriteReq MSHR hits 5098835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 5108835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 5119096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits 5129096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits 5139096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits 5149096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits 5158844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses 5168844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses 5178835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 5188835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 5198844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses 5208844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses 5218844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses 5228844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses 5239096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3667500 # number of ReadReq MSHR miss cycles 5249096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 3667500 # number of ReadReq MSHR miss cycles 5259096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713000 # number of WriteReq MSHR miss cycles 5269096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1713000 # number of WriteReq MSHR miss cycles 5279096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 5380500 # number of demand (read+write) MSHR miss cycles 5289096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 5380500 # number of demand (read+write) MSHR miss cycles 5299096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 5380500 # number of overall MSHR miss cycles 5309096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 5380500 # number of overall MSHR miss cycles 5319096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054315 # mshr miss rate for ReadReq accesses 5329096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054315 # mshr miss rate for ReadReq accesses 5338835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 5349055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 5359096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051682 # mshr miss rate for demand accesses 5369096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.051682 # mshr miss rate for demand accesses 5379096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051682 # mshr miss rate for overall accesses 5389096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.051682 # mshr miss rate for overall accesses 5399096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34275.700935 # average ReadReq mshr miss latency 5409096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34275.700935 # average ReadReq mshr miss latency 5419096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40785.714286 # average WriteReq mshr miss latency 5429096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40785.714286 # average WriteReq mshr miss latency 5439096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36110.738255 # average overall mshr miss latency 5449096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 36110.738255 # average overall mshr miss latency 5459096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36110.738255 # average overall mshr miss latency 5469096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 36110.738255 # average overall mshr miss latency 5478317SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5488317SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5499096Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 186.552400 # Cycle average of tags in use 5509096Sandreas.hansson@arm.comsystem.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. 5519096Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks. 5529096Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs 0.115169 # Average number of references to valid blocks. 5538317SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5549096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 140.494709 # Average occupied blocks per requestor 5559096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 46.057690 # Average occupied blocks per requestor 5569096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004288 # Average percentage of cache occupancy 5579096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001406 # Average percentage of cache occupancy 5589096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.005693 # Average percentage of cache occupancy 5599096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits 5609079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits 5619096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits 5629096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits 5639079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits 5649096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits 5659096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits 5669079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits 5679096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 41 # number of overall hits 5689096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 277 # number of ReadReq misses 5699079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses 5709096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses 5718835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 5728835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 5739096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses 5749079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 5759096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses 5769096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses 5779079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 5789096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404 # number of overall misses 5799096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9973000 # number of ReadReq miss cycles 5809096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 3362000 # number of ReadReq miss cycles 5819096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 13335000 # number of ReadReq miss cycles 5829096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1665500 # number of ReadExReq miss cycles 5839096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1665500 # number of ReadExReq miss cycles 5849096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 9973000 # number of demand (read+write) miss cycles 5859096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 5027500 # number of demand (read+write) miss cycles 5869096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 15000500 # number of demand (read+write) miss cycles 5879096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 9973000 # number of overall miss cycles 5889096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 5027500 # number of overall miss cycles 5899096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 15000500 # number of overall miss cycles 5908844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) 5918844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) 5928844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) 5938835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 5948835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 5958844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses 5968844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses 5978844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses 5988844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses 5998844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses 6008844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses 6019096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935811 # miss rate for ReadReq accesses 6029079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # miss rate for ReadReq accesses 6039096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.898263 # miss rate for ReadReq accesses 6048835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6059055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6069096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.935811 # miss rate for demand accesses 6079079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.852349 # miss rate for demand accesses 6089096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.907865 # miss rate for demand accesses 6099096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.935811 # miss rate for overall accesses 6109079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.852349 # miss rate for overall accesses 6119096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.907865 # miss rate for overall accesses 6129096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36003.610108 # average ReadReq miss latency 6139096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39552.941176 # average ReadReq miss latency 6149096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 36837.016575 # average ReadReq miss latency 6159096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39654.761905 # average ReadExReq miss latency 6169096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 39654.761905 # average ReadExReq miss latency 6179096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36003.610108 # average overall miss latency 6189096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 39586.614173 # average overall miss latency 6199096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 37129.950495 # average overall miss latency 6209096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36003.610108 # average overall miss latency 6219096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 39586.614173 # average overall miss latency 6229096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 37129.950495 # average overall miss latency 6238317SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6248317SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6258317SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6268317SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6278983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6288983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6298317SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6307860SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6319096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 6328844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 6339096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 6349096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 6358844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 6369096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 6379096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 6388844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 6399096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 6409096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses 6419079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 6429096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses 6438835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 6448835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 6459096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses 6469079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses 6479096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses 6489096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses 6499079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses 6509096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses 6519096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9090000 # number of ReadReq MSHR miss cycles 6529096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2983000 # number of ReadReq MSHR miss cycles 6539096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 12073000 # number of ReadReq MSHR miss cycles 6549096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1532500 # number of ReadExReq MSHR miss cycles 6559096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1532500 # number of ReadExReq MSHR miss cycles 6569096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9090000 # number of demand (read+write) MSHR miss cycles 6579096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4515500 # number of demand (read+write) MSHR miss cycles 6589096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 13605500 # number of demand (read+write) MSHR miss cycles 6599096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9090000 # number of overall MSHR miss cycles 6609096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4515500 # number of overall MSHR miss cycles 6619096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 13605500 # number of overall MSHR miss cycles 6629096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for ReadReq accesses 6639079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses 6649096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.883375 # mshr miss rate for ReadReq accesses 6658835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6669055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6679096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for demand accesses 6689079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses 6699096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.894382 # mshr miss rate for demand accesses 6709096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for overall accesses 6719079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses 6729096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.894382 # mshr miss rate for overall accesses 6739096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33054.545455 # average ReadReq mshr miss latency 6749096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36827.160494 # average ReadReq mshr miss latency 6759096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33912.921348 # average ReadReq mshr miss latency 6769096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36488.095238 # average ReadExReq mshr miss latency 6779096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36488.095238 # average ReadExReq mshr miss latency 6789096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency 6799096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency 6809096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency 6819096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency 6829096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency 6839096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency 6847860SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6857860SN/A 6867860SN/A---------- End Simulation Statistics ---------- 687