xref: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000012                       # Number of seconds simulated
sim_ticks                                    11859500                       # Number of ticks simulated
final_tick                                   11859500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  50616                       # Simulator instruction rate (inst/s)
host_op_rate                                    59274                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              130716325                       # Simulator tick rate (ticks/s)
host_mem_usage                                 300356                       # Number of bytes of host memory used
host_seconds                                     0.09                       # Real time elapsed on the host
sim_insts                                        4591                       # Number of instructions simulated
sim_ops                                          5377                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst              3776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              5888                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher        37184                       # Number of bytes read from this memory
system.physmem.bytes_read::total                46848                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst         3776                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total            3776                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                 59                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                 92                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher          581                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   732                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            318394536                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            496479615                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher   3135376702                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              3950250854                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       318394536                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          318394536                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           318394536                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           496479615                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher   3135376702                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             3950250854                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           733                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         733                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    46912                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     46912                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 143                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  90                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  40                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  73                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  58                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  88                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  52                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  18                       # Per bank write bursts
system.physmem.perBankRdBursts::8                  12                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 34                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 47                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 17                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 19                       # Per bank write bursts
system.physmem.perBankRdBursts::14                  0                       # Per bank write bursts
system.physmem.perBankRdBursts::15                 14                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        11846500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     733                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                        96                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       114                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        83                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        79                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        68                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        60                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        51                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        53                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        48                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       17                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples           60                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      712.533333                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     570.872295                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     336.283550                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127              4      6.67%      6.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255            5      8.33%     15.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383            4      6.67%     21.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            1      1.67%     23.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            4      6.67%     30.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           10     16.67%     46.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            4      6.67%     53.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            5      8.33%     61.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           23     38.33%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             60                       # Bytes accessed per row activation
system.physmem.totQLat                       17284989                       # Total ticks spent queuing
system.physmem.totMemAccLat                  31028739                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      3665000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       23581.16                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  42331.16                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                        3955.65                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                     3955.65                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                          30.90                       # Data bus utilization in percentage
system.physmem.busUtilRead                      30.90                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         5.25                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        662                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.31                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        16161.66                       # Average gap between requests
system.physmem.pageHitRate                      90.31                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE             6500                       # Time in different power states
system.physmem.memoryStateTime::REF            260000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT           7800750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.trans_dist::ReadReq                 704                       # Transaction distribution
system.membus.trans_dist::ReadResp                702                       # Transaction distribution
system.membus.trans_dist::ReadExReq                29                       # Transaction distribution
system.membus.trans_dist::ReadExResp               29                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1464                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1464                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        46784                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   46784                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples               733                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     733    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 733                       # Request fanout histogram
system.membus.reqLayer0.occupancy              803724                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               6.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy            6629985                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             55.9                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                    2560                       # Number of BP lookups
system.cpu.branchPred.condPredicted              1531                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               510                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                  939                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     497                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             52.928647                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     297                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 56                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   13                       # Number of system calls
system.cpu.numCycles                            23720                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles               4394                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          12370                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        2560                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches                794                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                         11397                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                    1062                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                   19                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           322                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           84                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                      4117                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   139                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              16747                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.858243                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.204203                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                     9977     59.57%     59.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                     2687     16.04%     75.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      563      3.36%     78.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                     3520     21.02%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                16747                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.107926                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.521501                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                     4535                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                  6577                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      5106                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   160                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                    369                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved                  338                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   165                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts                  10143                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                  1684                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                    369                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                     5681                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                    3207                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           2422                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      4105                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                   963                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                   9048                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts                   426                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents                    49                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                      5                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                    101                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                    748                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands                9432                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 41033                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups             9977                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups                18                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                  5494                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                     3938                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 31                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             29                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                       472                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 1824                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1295                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                       8517                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  40                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                      7242                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued               203                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined            2981                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined         8241                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved              3                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         16747                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.432436                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.833231                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               12501     74.65%     74.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                1960     11.70%     86.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                1628      9.72%     96.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                 606      3.62%     99.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                  52      0.31%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            4                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           16747                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                     437     29.61%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     29.61% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                    482     32.66%     62.26% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                   557     37.74%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                  4533     62.59%     62.59% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    6      0.08%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     62.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.72% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 1613     22.27%     84.99% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1087     15.01%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                   7242                       # Type of FU issued
system.cpu.iq.rate                           0.305312                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                        1476                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.203811                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              32865                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             11527                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses         6638                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                  45                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                 18                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                   8689                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      29                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads               15                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads          797                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores          357                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            7                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            23                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                    369                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                     705                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                   159                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts                8571                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  1824                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 1295                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 28                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                      6                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                   151                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect             68                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          294                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                  362                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                  6828                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                  1428                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               414                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                            14                       # number of nop insts executed
system.cpu.iew.exec_refs                         2449                       # number of memory reference insts executed
system.cpu.iew.exec_branches                     1283                       # Number of branches executed
system.cpu.iew.exec_stores                       1021                       # Number of stores executed
system.cpu.iew.exec_rate                     0.287858                       # Inst execution rate
system.cpu.iew.wb_sent                           6699                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                          6654                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                      3045                       # num instructions producing a value
system.cpu.iew.wb_consumers                      5519                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.280523                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.551730                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts            2714                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts               348                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        16184                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.332242                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     0.986798                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        13581     83.92%     83.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         1345      8.31%     92.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2          599      3.70%     95.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          281      1.74%     97.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          168      1.04%     98.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5           78      0.48%     99.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6           47      0.29%     99.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7           33      0.20%     99.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8           52      0.32%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        16184                       # Number of insts commited each cycle
system.cpu.commit.committedInsts                 4591                       # Number of instructions committed
system.cpu.commit.committedOps                   5377                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                           1965                       # Number of memory references committed
system.cpu.commit.loads                          1027                       # Number of loads committed
system.cpu.commit.membars                          12                       # Number of memory barriers committed
system.cpu.commit.branches                       1007                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                      4624                       # Number of committed integer instructions.
system.cpu.commit.function_calls                   82                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu             3405     63.33%     63.33% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult               4      0.07%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            3      0.06%     63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead            1027     19.10%     82.56% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite            938     17.44%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total              5377                       # Class of committed instruction
system.cpu.commit.bw_lim_events                    52                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                        24066                       # The number of ROB reads
system.cpu.rob.rob_writes                       16749                       # The number of ROB writes
system.cpu.timesIdled                             138                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                            6973                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                        4591                       # Number of Instructions Simulated
system.cpu.committedOps                          5377                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               5.166630                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         5.166630                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.193550                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.193550                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                     6786                       # number of integer regfile reads
system.cpu.int_regfile_writes                    3839                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.cc_regfile_reads                     24301                       # number of cc regfile reads
system.cpu.cc_regfile_writes                     2919                       # number of cc regfile writes
system.cpu.misc_regfile_reads                    2642                       # number of misc regfile reads
system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
system.cpu.toL2Bus.trans_dist::ReadReq            408                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           407                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq         1026                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           40                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           40                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          608                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          287                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               895                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        19456                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9152                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              28608                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                        1026                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples         1474                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        5.696065                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.460111                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5                448     30.39%     30.39% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6               1026     69.61%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total           1474                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         224000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        461250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          3.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        223747                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.9                       # Layer utilization (%)
system.cpu.icache.tags.replacements                47                       # number of replacements
system.cpu.icache.tags.tagsinuse           138.950029                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                3784                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               304                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             12.447368                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   138.950029                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.271387                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.271387                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          257                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          228                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.501953                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              8536                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             8536                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst         3784                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            3784                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          3784                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             3784                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         3784                       # number of overall hits
system.cpu.icache.overall_hits::total            3784                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          332                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           332                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          332                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            332                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          332                       # number of overall misses
system.cpu.icache.overall_misses::total           332                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst      7426247                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total      7426247                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst      7426247                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total      7426247                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst      7426247                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total      7426247                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         4116                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         4116                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         4116                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         4116                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         4116                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         4116                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.080661                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.080661                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.080661                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.080661                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.080661                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.080661                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22368.213855                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22368.213855                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22368.213855                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22368.213855                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22368.213855                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22368.213855                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1112                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                66                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    16.848485                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           28                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           28                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           28                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           28                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           28                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           28                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          304                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          304                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          304                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          304                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          304                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          304                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst      6489997                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total      6489997                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst      6489997                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total      6489997                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst      6489997                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total      6489997                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.073858                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.073858                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.073858                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.073858                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.073858                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.073858                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21348.674342                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21348.674342                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21348.674342                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21348.674342                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21348.674342                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21348.674342                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified         2346                       # number of hwpf identified
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr          489                       # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache         1139                       # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher           86                       # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           29                       # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued          603                       # number of hwpf issued
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page          198                       # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          370.948422                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                270                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              691                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.390738                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst    30.449811                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    36.598805                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   303.899806                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001859                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.002234                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.018549                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.022641                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          570                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024          121                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0          471                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1           99                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.034790                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.007385                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             7899                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            7899                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst          234                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           35                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total            269                       # number of ReadReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           11                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           11                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst          234                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           46                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total             280                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst          234                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           46                       # number of overall hits
system.cpu.l2cache.overall_hits::total            280                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst           70                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           69                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          139                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           29                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           29                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst           70                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data           98                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           168                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst           70                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data           98                       # number of overall misses
system.cpu.l2cache.overall_misses::total          168                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      4724750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5170750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total      9895500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2577500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      2577500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst      4724750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      7748250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     12473000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst      4724750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      7748250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     12473000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          304                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          104                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          408                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           40                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           40                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          304                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          144                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          448                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          304                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          144                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          448                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.230263                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.663462                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.340686                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.725000                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.725000                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.230263                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.680556                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.375000                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.230263                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.680556                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.375000                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67496.428571                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74938.405797                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71190.647482                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88879.310345                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88879.310345                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67496.428571                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79063.775510                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74244.047619                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67496.428571                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79063.775510                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74244.047619                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs          388                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs               17                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs    22.823529                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           11                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            6                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           11                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            6                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           11                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            6                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst           59                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           63                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          122                       # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher          603                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total          603                       # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           29                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           29                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst           59                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data           92                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          151                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst           59                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data           92                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher          603                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          754                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      3978500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4478500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total      8457000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     49457864                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     49457864                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2337500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2337500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      3978500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6816000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     10794500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      3978500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6816000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     49457864                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     60252364                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.194079                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.605769                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.299020                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.725000                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.725000                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.194079                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.638889                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.337054                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.194079                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.638889                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     1.683036                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67432.203390                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71087.301587                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69319.672131                       # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82019.674959                       # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80603.448276                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80603.448276                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67432.203390                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74086.956522                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71486.754967                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67432.203390                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74086.956522                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79910.297082                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements                 1                       # number of replacements
system.cpu.dcache.tags.tagsinuse            82.309019                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                1894                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               143                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             13.244755                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    82.309019                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.160760                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.160760                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          142                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.277344                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              4719                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             4719                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data         1158                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1158                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          715                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            715                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           10                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           10                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data          1873                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             1873                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         1873                       # number of overall hits
system.cpu.dcache.overall_hits::total            1873                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          194                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           194                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          198                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          198                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data          392                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            392                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          392                       # number of overall misses
system.cpu.dcache.overall_misses::total           392                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     10805495                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     10805495                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      8861750                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      8861750                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       152500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       152500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     19667245                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     19667245                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     19667245                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     19667245                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1352                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1352                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           12                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           12                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2265                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2265                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2265                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2265                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.143491                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.143491                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.216867                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.216867                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.166667                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.166667                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.173068                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.173068                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.173068                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.173068                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        76250                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        76250                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 50171.543367                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 50171.543367                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           10                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          617                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              18                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs           10                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    34.277778                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           90                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           90                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          158                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          158                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          248                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          248                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          248                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          248                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          104                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          104                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           40                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           40                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          144                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          144                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          144                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          144                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5492753                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      5492753                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2689000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      2689000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8181753                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      8181753                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8181753                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      8181753                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076923                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076923                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.043812                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.043812                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063576                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.063576                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063576                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.063576                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        67225                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        67225                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------