stats.txt revision 10409
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 11859500 # Number of ticks simulated 5final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 50616 # Simulator instruction rate (inst/s) 8host_op_rate 59274 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 130716325 # Simulator tick rate (ticks/s) 10host_mem_usage 300356 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 3776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 5888 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 37184 # Number of bytes read from this memory 19system.physmem.bytes_read::total 46848 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 3776 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 3776 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 59 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 92 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 581 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 732 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 318394536 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 496479615 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 3135376702 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 3950250854 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 318394536 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 318394536 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 318394536 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 496479615 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 3135376702 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 3950250854 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 733 # Number of read requests accepted 37system.physmem.writeReqs 0 # Number of write requests accepted 38system.physmem.readBursts 733 # Number of DRAM read bursts, including those serviced by the write queue 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 40system.physmem.bytesReadDRAM 46912 # Total number of bytes read from DRAM 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 43system.physmem.bytesReadSys 46912 # Total read bytes from the system interface side 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 48system.physmem.perBankRdBursts::0 143 # Per bank write bursts 49system.physmem.perBankRdBursts::1 90 # Per bank write bursts 50system.physmem.perBankRdBursts::2 40 # Per bank write bursts 51system.physmem.perBankRdBursts::3 73 # Per bank write bursts 52system.physmem.perBankRdBursts::4 58 # Per bank write bursts 53system.physmem.perBankRdBursts::5 88 # Per bank write bursts 54system.physmem.perBankRdBursts::6 52 # Per bank write bursts 55system.physmem.perBankRdBursts::7 18 # Per bank write bursts 56system.physmem.perBankRdBursts::8 12 # Per bank write bursts 57system.physmem.perBankRdBursts::9 28 # Per bank write bursts 58system.physmem.perBankRdBursts::10 34 # Per bank write bursts 59system.physmem.perBankRdBursts::11 47 # Per bank write bursts 60system.physmem.perBankRdBursts::12 17 # Per bank write bursts 61system.physmem.perBankRdBursts::13 19 # Per bank write bursts 62system.physmem.perBankRdBursts::14 0 # Per bank write bursts 63system.physmem.perBankRdBursts::15 14 # Per bank write bursts 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 82system.physmem.totGap 11846500 # Total gap between requests 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) 89system.physmem.readPktSize::6 733 # Read request sizes (log2) 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) 97system.physmem.rdQLenPdf::0 96 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 60 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 51 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 53 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 48 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 17 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 18 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 6 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 129system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 193system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 712.533333 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 570.872295 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 336.283550 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 4 6.67% 6.67% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 5 8.33% 15.00% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 4 6.67% 21.67% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 1 1.67% 23.33% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 4 6.67% 30.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 10 16.67% 46.67% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 4 6.67% 53.33% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 5 8.33% 61.67% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 23 38.33% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation 207system.physmem.totQLat 17284989 # Total ticks spent queuing 208system.physmem.totMemAccLat 31028739 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 3665000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 23581.16 # Average queueing delay per DRAM burst 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 212system.physmem.avgMemAccLat 42331.16 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 3955.65 # Average DRAM read bandwidth in MiByte/s 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 215system.physmem.avgRdBWSys 3955.65 # Average system read bandwidth in MiByte/s 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 218system.physmem.busUtil 30.90 # Data bus utilization in percentage 219system.physmem.busUtilRead 30.90 # Data bus utilization in percentage for reads 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 221system.physmem.avgRdQLen 5.25 # Average read queue length when enqueuing 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 223system.physmem.readRowHits 662 # Number of row buffer hits during reads 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes 225system.physmem.readRowHitRate 90.31 # Row buffer hit rate for reads 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 227system.physmem.avgGap 16161.66 # Average gap between requests 228system.physmem.pageHitRate 90.31 # Row buffer hit rate, read and write combined 229system.physmem.memoryStateTime::IDLE 6500 # Time in different power states 230system.physmem.memoryStateTime::REF 260000 # Time in different power states 231system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 232system.physmem.memoryStateTime::ACT 7800750 # Time in different power states 233system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 234system.membus.trans_dist::ReadReq 704 # Transaction distribution 235system.membus.trans_dist::ReadResp 702 # Transaction distribution 236system.membus.trans_dist::ReadExReq 29 # Transaction distribution 237system.membus.trans_dist::ReadExResp 29 # Transaction distribution 238system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1464 # Packet count per connected master and slave (bytes) 239system.membus.pkt_count::total 1464 # Packet count per connected master and slave (bytes) 240system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46784 # Cumulative packet size per connected master and slave (bytes) 241system.membus.pkt_size::total 46784 # Cumulative packet size per connected master and slave (bytes) 242system.membus.snoops 0 # Total snoops (count) 243system.membus.snoop_fanout::samples 733 # Request fanout histogram 244system.membus.snoop_fanout::mean 0 # Request fanout histogram 245system.membus.snoop_fanout::stdev 0 # Request fanout histogram 246system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 247system.membus.snoop_fanout::0 733 100.00% 100.00% # Request fanout histogram 248system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 249system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 250system.membus.snoop_fanout::min_value 0 # Request fanout histogram 251system.membus.snoop_fanout::max_value 0 # Request fanout histogram 252system.membus.snoop_fanout::total 733 # Request fanout histogram 253system.membus.reqLayer0.occupancy 803724 # Layer occupancy (ticks) 254system.membus.reqLayer0.utilization 6.8 # Layer utilization (%) 255system.membus.respLayer1.occupancy 6629985 # Layer occupancy (ticks) 256system.membus.respLayer1.utilization 55.9 # Layer utilization (%) 257system.cpu_clk_domain.clock 500 # Clock period in ticks 258system.cpu.branchPred.lookups 2560 # Number of BP lookups 259system.cpu.branchPred.condPredicted 1531 # Number of conditional branches predicted 260system.cpu.branchPred.condIncorrect 510 # Number of conditional branches incorrect 261system.cpu.branchPred.BTBLookups 939 # Number of BTB lookups 262system.cpu.branchPred.BTBHits 497 # Number of BTB hits 263system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 264system.cpu.branchPred.BTBHitPct 52.928647 # BTB Hit Percentage 265system.cpu.branchPred.usedRAS 297 # Number of times the RAS was used to get a target. 266system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. 267system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 268system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 269system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 270system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 271system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 272system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 273system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 274system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 275system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 276system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 277system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 278system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 279system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 280system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 281system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 282system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 283system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 284system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 285system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 286system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 287system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 288system.cpu.dtb.inst_hits 0 # ITB inst hits 289system.cpu.dtb.inst_misses 0 # ITB inst misses 290system.cpu.dtb.read_hits 0 # DTB read hits 291system.cpu.dtb.read_misses 0 # DTB read misses 292system.cpu.dtb.write_hits 0 # DTB write hits 293system.cpu.dtb.write_misses 0 # DTB write misses 294system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 295system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 296system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 297system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 298system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 299system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 300system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 301system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 302system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 303system.cpu.dtb.read_accesses 0 # DTB read accesses 304system.cpu.dtb.write_accesses 0 # DTB write accesses 305system.cpu.dtb.inst_accesses 0 # ITB inst accesses 306system.cpu.dtb.hits 0 # DTB hits 307system.cpu.dtb.misses 0 # DTB misses 308system.cpu.dtb.accesses 0 # DTB accesses 309system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 310system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 311system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 312system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 313system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 314system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 315system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 316system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 317system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 318system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 319system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 320system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 321system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 322system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 323system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 324system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 325system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 326system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 327system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 328system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 329system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 330system.cpu.itb.inst_hits 0 # ITB inst hits 331system.cpu.itb.inst_misses 0 # ITB inst misses 332system.cpu.itb.read_hits 0 # DTB read hits 333system.cpu.itb.read_misses 0 # DTB read misses 334system.cpu.itb.write_hits 0 # DTB write hits 335system.cpu.itb.write_misses 0 # DTB write misses 336system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 337system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 338system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 339system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 340system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 341system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 342system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 343system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 344system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 345system.cpu.itb.read_accesses 0 # DTB read accesses 346system.cpu.itb.write_accesses 0 # DTB write accesses 347system.cpu.itb.inst_accesses 0 # ITB inst accesses 348system.cpu.itb.hits 0 # DTB hits 349system.cpu.itb.misses 0 # DTB misses 350system.cpu.itb.accesses 0 # DTB accesses 351system.cpu.workload.num_syscalls 13 # Number of system calls 352system.cpu.numCycles 23720 # number of cpu cycles simulated 353system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 354system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 355system.cpu.fetch.icacheStallCycles 4394 # Number of cycles fetch is stalled on an Icache miss 356system.cpu.fetch.Insts 12370 # Number of instructions fetch has processed 357system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered 358system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken 359system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked 360system.cpu.fetch.SquashCycles 1062 # Number of cycles fetch has spent squashing 361system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 362system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps 363system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR 364system.cpu.fetch.CacheLines 4117 # Number of cache lines fetched 365system.cpu.fetch.IcacheSquashes 139 # Number of outstanding Icache misses that were squashed 366system.cpu.fetch.rateDist::samples 16747 # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::mean 0.858243 # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::stdev 1.204203 # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::0 9977 59.57% 59.57% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::1 2687 16.04% 75.62% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::2 563 3.36% 78.98% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::3 3520 21.02% 100.00% # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::total 16747 # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.branchRate 0.107926 # Number of branch fetches per cycle 379system.cpu.fetch.rate 0.521501 # Number of inst fetches per cycle 380system.cpu.decode.IdleCycles 4535 # Number of cycles decode is idle 381system.cpu.decode.BlockedCycles 6577 # Number of cycles decode is blocked 382system.cpu.decode.RunCycles 5106 # Number of cycles decode is running 383system.cpu.decode.UnblockCycles 160 # Number of cycles decode is unblocking 384system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing 385system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch 386system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction 387system.cpu.decode.DecodedInsts 10143 # Number of instructions handled by decode 388system.cpu.decode.SquashedInsts 1684 # Number of squashed instructions handled by decode 389system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing 390system.cpu.rename.IdleCycles 5681 # Number of cycles rename is idle 391system.cpu.rename.BlockCycles 3207 # Number of cycles rename is blocking 392system.cpu.rename.serializeStallCycles 2422 # count of cycles rename stalled for serializing inst 393system.cpu.rename.RunCycles 4105 # Number of cycles rename is running 394system.cpu.rename.UnblockCycles 963 # Number of cycles rename is unblocking 395system.cpu.rename.RenamedInsts 9048 # Number of instructions processed by rename 396system.cpu.rename.SquashedInsts 426 # Number of squashed instructions processed by rename 397system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full 398system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full 399system.cpu.rename.LQFullEvents 101 # Number of times rename has blocked due to LQ full 400system.cpu.rename.SQFullEvents 748 # Number of times rename has blocked due to SQ full 401system.cpu.rename.RenamedOperands 9432 # Number of destination operands rename has renamed 402system.cpu.rename.RenameLookups 41033 # Number of register rename lookups that rename has made 403system.cpu.rename.int_rename_lookups 9977 # Number of integer rename lookups 404system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups 405system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 406system.cpu.rename.UndoneMaps 3938 # Number of HB maps that are undone due to squashing 407system.cpu.rename.serializingInsts 31 # count of serializing insts renamed 408system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed 409system.cpu.rename.skidInsts 472 # count of insts added to the skid buffer 410system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. 411system.cpu.memDep0.insertedStores 1295 # Number of stores inserted to the mem dependence unit. 412system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 413system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 414system.cpu.iq.iqInstsAdded 8517 # Number of instructions added to the IQ (excludes non-spec) 415system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ 416system.cpu.iq.iqInstsIssued 7242 # Number of instructions issued 417system.cpu.iq.iqSquashedInstsIssued 203 # Number of squashed instructions issued 418system.cpu.iq.iqSquashedInstsExamined 2981 # Number of squashed instructions iterated over during squash; mainly for profiling 419system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph 420system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed 421system.cpu.iq.issued_per_cycle::samples 16747 # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::mean 0.432436 # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::stdev 0.833231 # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::0 12501 74.65% 74.65% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::1 1960 11.70% 86.35% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::2 1628 9.72% 96.07% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::3 606 3.62% 99.69% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::4 52 0.31% 100.00% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 434system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 435system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::total 16747 # Number of insts issued each cycle 438system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 439system.cpu.iq.fu_full::IntAlu 437 29.61% 29.61% # attempts to use FU when none available 440system.cpu.iq.fu_full::IntMult 0 0.00% 29.61% # attempts to use FU when none available 441system.cpu.iq.fu_full::IntDiv 0 0.00% 29.61% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.61% # attempts to use FU when none available 443system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.61% # attempts to use FU when none available 444system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.61% # attempts to use FU when none available 445system.cpu.iq.fu_full::FloatMult 0 0.00% 29.61% # attempts to use FU when none available 446system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.61% # attempts to use FU when none available 447system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.61% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.61% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.61% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.61% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.61% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.61% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.61% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdMult 0 0.00% 29.61% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.61% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdShift 0 0.00% 29.61% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.61% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.61% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.61% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.61% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.61% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.61% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.61% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.61% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.61% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.61% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.61% # attempts to use FU when none available 468system.cpu.iq.fu_full::MemRead 482 32.66% 62.26% # attempts to use FU when none available 469system.cpu.iq.fu_full::MemWrite 557 37.74% 100.00% # attempts to use FU when none available 470system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 471system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 472system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 473system.cpu.iq.FU_type_0::IntAlu 4533 62.59% 62.59% # Type of FU issued 474system.cpu.iq.FU_type_0::IntMult 6 0.08% 62.68% # Type of FU issued 475system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.68% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.68% # Type of FU issued 477system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.68% # Type of FU issued 478system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.68% # Type of FU issued 479system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.68% # Type of FU issued 480system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.68% # Type of FU issued 481system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.72% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued 502system.cpu.iq.FU_type_0::MemRead 1613 22.27% 84.99% # Type of FU issued 503system.cpu.iq.FU_type_0::MemWrite 1087 15.01% 100.00% # Type of FU issued 504system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 505system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 506system.cpu.iq.FU_type_0::total 7242 # Type of FU issued 507system.cpu.iq.rate 0.305312 # Inst issue rate 508system.cpu.iq.fu_busy_cnt 1476 # FU busy when requested 509system.cpu.iq.fu_busy_rate 0.203811 # FU busy rate (busy events/executed inst) 510system.cpu.iq.int_inst_queue_reads 32865 # Number of integer instruction queue reads 511system.cpu.iq.int_inst_queue_writes 11527 # Number of integer instruction queue writes 512system.cpu.iq.int_inst_queue_wakeup_accesses 6638 # Number of integer instruction queue wakeup accesses 513system.cpu.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads 514system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes 515system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 516system.cpu.iq.int_alu_accesses 8689 # Number of integer alu accesses 517system.cpu.iq.fp_alu_accesses 29 # Number of floating point alu accesses 518system.cpu.iew.lsq.thread0.forwLoads 15 # Number of loads that had data forwarded from stores 519system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 520system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed 521system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed 522system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 523system.cpu.iew.lsq.thread0.squashedStores 357 # Number of stores squashed 524system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 525system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 526system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled 527system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked 528system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 529system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing 530system.cpu.iew.iewBlockCycles 705 # Number of cycles IEW is blocking 531system.cpu.iew.iewUnblockCycles 159 # Number of cycles IEW is unblocking 532system.cpu.iew.iewDispatchedInsts 8571 # Number of instructions dispatched to IQ 533system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 534system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions 535system.cpu.iew.iewDispStoreInsts 1295 # Number of dispatched store instructions 536system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions 537system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall 538system.cpu.iew.iewLSQFullEvents 151 # Number of times the LSQ has become full, causing a stall 539system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 540system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly 541system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly 542system.cpu.iew.branchMispredicts 362 # Number of branch mispredicts detected at execute 543system.cpu.iew.iewExecutedInsts 6828 # Number of executed instructions 544system.cpu.iew.iewExecLoadInsts 1428 # Number of load instructions executed 545system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute 546system.cpu.iew.exec_swp 0 # number of swp insts executed 547system.cpu.iew.exec_nop 14 # number of nop insts executed 548system.cpu.iew.exec_refs 2449 # number of memory reference insts executed 549system.cpu.iew.exec_branches 1283 # Number of branches executed 550system.cpu.iew.exec_stores 1021 # Number of stores executed 551system.cpu.iew.exec_rate 0.287858 # Inst execution rate 552system.cpu.iew.wb_sent 6699 # cumulative count of insts sent to commit 553system.cpu.iew.wb_count 6654 # cumulative count of insts written-back 554system.cpu.iew.wb_producers 3045 # num instructions producing a value 555system.cpu.iew.wb_consumers 5519 # num instructions consuming a value 556system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 557system.cpu.iew.wb_rate 0.280523 # insts written-back per cycle 558system.cpu.iew.wb_fanout 0.551730 # average fanout of values written-back 559system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 560system.cpu.commit.commitSquashedInsts 2714 # The number of squashed insts skipped by commit 561system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 562system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted 563system.cpu.commit.committed_per_cycle::samples 16184 # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::mean 0.332242 # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::stdev 0.986798 # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::0 13581 83.92% 83.92% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::1 1345 8.31% 92.23% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::2 599 3.70% 95.93% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::3 281 1.74% 97.66% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::4 168 1.04% 98.70% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::5 78 0.48% 99.18% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::6 47 0.29% 99.47% # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::7 33 0.20% 99.68% # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::8 52 0.32% 100.00% # Number of insts commited each cycle 576system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 579system.cpu.commit.committed_per_cycle::total 16184 # Number of insts commited each cycle 580system.cpu.commit.committedInsts 4591 # Number of instructions committed 581system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed 582system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 583system.cpu.commit.refs 1965 # Number of memory references committed 584system.cpu.commit.loads 1027 # Number of loads committed 585system.cpu.commit.membars 12 # Number of memory barriers committed 586system.cpu.commit.branches 1007 # Number of branches committed 587system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 588system.cpu.commit.int_insts 4624 # Number of committed integer instructions. 589system.cpu.commit.function_calls 82 # Number of function calls committed. 590system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 591system.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction 592system.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction 593system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction 594system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction 595system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction 596system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction 597system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction 598system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction 599system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction 600system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction 601system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction 602system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction 603system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction 604system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction 605system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction 606system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction 607system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction 608system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction 609system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction 610system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction 611system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction 612system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction 614system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction 615system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction 616system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 617system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 618system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 619system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 620system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 621system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 622system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 623system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 624system.cpu.commit.op_class_0::total 5377 # Class of committed instruction 625system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached 626system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 627system.cpu.rob.rob_reads 24066 # The number of ROB reads 628system.cpu.rob.rob_writes 16749 # The number of ROB writes 629system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself 630system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling 631system.cpu.committedInsts 4591 # Number of Instructions Simulated 632system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated 633system.cpu.cpi 5.166630 # CPI: Cycles Per Instruction 634system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads 635system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle 636system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads 637system.cpu.int_regfile_reads 6786 # number of integer regfile reads 638system.cpu.int_regfile_writes 3839 # number of integer regfile writes 639system.cpu.fp_regfile_reads 16 # number of floating regfile reads 640system.cpu.cc_regfile_reads 24301 # number of cc regfile reads 641system.cpu.cc_regfile_writes 2919 # number of cc regfile writes 642system.cpu.misc_regfile_reads 2642 # number of misc regfile reads 643system.cpu.misc_regfile_writes 24 # number of misc regfile writes 644system.cpu.toL2Bus.trans_dist::ReadReq 408 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::HardPFReq 1026 # Transaction distribution 647system.cpu.toL2Bus.trans_dist::ReadExReq 40 # Transaction distribution 648system.cpu.toL2Bus.trans_dist::ReadExResp 40 # Transaction distribution 649system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 608 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) 651system.cpu.toL2Bus.pkt_count::total 895 # Packet count per connected master and slave (bytes) 652system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19456 # Cumulative packet size per connected master and slave (bytes) 653system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) 654system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) 655system.cpu.toL2Bus.snoops 1026 # Total snoops (count) 656system.cpu.toL2Bus.snoop_fanout::samples 1474 # Request fanout histogram 657system.cpu.toL2Bus.snoop_fanout::mean 5.696065 # Request fanout histogram 658system.cpu.toL2Bus.snoop_fanout::stdev 0.460111 # Request fanout histogram 659system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 660system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 661system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 662system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 663system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 664system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 665system.cpu.toL2Bus.snoop_fanout::5 448 30.39% 30.39% # Request fanout histogram 666system.cpu.toL2Bus.snoop_fanout::6 1026 69.61% 100.00% # Request fanout histogram 667system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 668system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 669system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 670system.cpu.toL2Bus.snoop_fanout::total 1474 # Request fanout histogram 671system.cpu.toL2Bus.reqLayer0.occupancy 224000 # Layer occupancy (ticks) 672system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) 673system.cpu.toL2Bus.respLayer0.occupancy 461250 # Layer occupancy (ticks) 674system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) 675system.cpu.toL2Bus.respLayer1.occupancy 223747 # Layer occupancy (ticks) 676system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) 677system.cpu.icache.tags.replacements 47 # number of replacements 678system.cpu.icache.tags.tagsinuse 138.950029 # Cycle average of tags in use 679system.cpu.icache.tags.total_refs 3784 # Total number of references to valid blocks. 680system.cpu.icache.tags.sampled_refs 304 # Sample count of references to valid blocks. 681system.cpu.icache.tags.avg_refs 12.447368 # Average number of references to valid blocks. 682system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 683system.cpu.icache.tags.occ_blocks::cpu.inst 138.950029 # Average occupied blocks per requestor 684system.cpu.icache.tags.occ_percent::cpu.inst 0.271387 # Average percentage of cache occupancy 685system.cpu.icache.tags.occ_percent::total 0.271387 # Average percentage of cache occupancy 686system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id 687system.cpu.icache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id 688system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id 689system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id 690system.cpu.icache.tags.tag_accesses 8536 # Number of tag accesses 691system.cpu.icache.tags.data_accesses 8536 # Number of data accesses 692system.cpu.icache.ReadReq_hits::cpu.inst 3784 # number of ReadReq hits 693system.cpu.icache.ReadReq_hits::total 3784 # number of ReadReq hits 694system.cpu.icache.demand_hits::cpu.inst 3784 # number of demand (read+write) hits 695system.cpu.icache.demand_hits::total 3784 # number of demand (read+write) hits 696system.cpu.icache.overall_hits::cpu.inst 3784 # number of overall hits 697system.cpu.icache.overall_hits::total 3784 # number of overall hits 698system.cpu.icache.ReadReq_misses::cpu.inst 332 # number of ReadReq misses 699system.cpu.icache.ReadReq_misses::total 332 # number of ReadReq misses 700system.cpu.icache.demand_misses::cpu.inst 332 # number of demand (read+write) misses 701system.cpu.icache.demand_misses::total 332 # number of demand (read+write) misses 702system.cpu.icache.overall_misses::cpu.inst 332 # number of overall misses 703system.cpu.icache.overall_misses::total 332 # number of overall misses 704system.cpu.icache.ReadReq_miss_latency::cpu.inst 7426247 # number of ReadReq miss cycles 705system.cpu.icache.ReadReq_miss_latency::total 7426247 # number of ReadReq miss cycles 706system.cpu.icache.demand_miss_latency::cpu.inst 7426247 # number of demand (read+write) miss cycles 707system.cpu.icache.demand_miss_latency::total 7426247 # number of demand (read+write) miss cycles 708system.cpu.icache.overall_miss_latency::cpu.inst 7426247 # number of overall miss cycles 709system.cpu.icache.overall_miss_latency::total 7426247 # number of overall miss cycles 710system.cpu.icache.ReadReq_accesses::cpu.inst 4116 # number of ReadReq accesses(hits+misses) 711system.cpu.icache.ReadReq_accesses::total 4116 # number of ReadReq accesses(hits+misses) 712system.cpu.icache.demand_accesses::cpu.inst 4116 # number of demand (read+write) accesses 713system.cpu.icache.demand_accesses::total 4116 # number of demand (read+write) accesses 714system.cpu.icache.overall_accesses::cpu.inst 4116 # number of overall (read+write) accesses 715system.cpu.icache.overall_accesses::total 4116 # number of overall (read+write) accesses 716system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080661 # miss rate for ReadReq accesses 717system.cpu.icache.ReadReq_miss_rate::total 0.080661 # miss rate for ReadReq accesses 718system.cpu.icache.demand_miss_rate::cpu.inst 0.080661 # miss rate for demand accesses 719system.cpu.icache.demand_miss_rate::total 0.080661 # miss rate for demand accesses 720system.cpu.icache.overall_miss_rate::cpu.inst 0.080661 # miss rate for overall accesses 721system.cpu.icache.overall_miss_rate::total 0.080661 # miss rate for overall accesses 722system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22368.213855 # average ReadReq miss latency 723system.cpu.icache.ReadReq_avg_miss_latency::total 22368.213855 # average ReadReq miss latency 724system.cpu.icache.demand_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency 725system.cpu.icache.demand_avg_miss_latency::total 22368.213855 # average overall miss latency 726system.cpu.icache.overall_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency 727system.cpu.icache.overall_avg_miss_latency::total 22368.213855 # average overall miss latency 728system.cpu.icache.blocked_cycles::no_mshrs 1112 # number of cycles access was blocked 729system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 730system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked 731system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 732system.cpu.icache.avg_blocked_cycles::no_mshrs 16.848485 # average number of cycles each access was blocked 733system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 734system.cpu.icache.fast_writes 0 # number of fast writes performed 735system.cpu.icache.cache_copies 0 # number of cache copies performed 736system.cpu.icache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits 737system.cpu.icache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits 738system.cpu.icache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits 739system.cpu.icache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits 740system.cpu.icache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits 741system.cpu.icache.overall_mshr_hits::total 28 # number of overall MSHR hits 742system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses 743system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses 744system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses 745system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses 746system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses 747system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses 748system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6489997 # number of ReadReq MSHR miss cycles 749system.cpu.icache.ReadReq_mshr_miss_latency::total 6489997 # number of ReadReq MSHR miss cycles 750system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6489997 # number of demand (read+write) MSHR miss cycles 751system.cpu.icache.demand_mshr_miss_latency::total 6489997 # number of demand (read+write) MSHR miss cycles 752system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6489997 # number of overall MSHR miss cycles 753system.cpu.icache.overall_mshr_miss_latency::total 6489997 # number of overall MSHR miss cycles 754system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for ReadReq accesses 755system.cpu.icache.ReadReq_mshr_miss_rate::total 0.073858 # mshr miss rate for ReadReq accesses 756system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for demand accesses 757system.cpu.icache.demand_mshr_miss_rate::total 0.073858 # mshr miss rate for demand accesses 758system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for overall accesses 759system.cpu.icache.overall_mshr_miss_rate::total 0.073858 # mshr miss rate for overall accesses 760system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21348.674342 # average ReadReq mshr miss latency 761system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21348.674342 # average ReadReq mshr miss latency 762system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency 763system.cpu.icache.demand_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency 764system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency 765system.cpu.icache.overall_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency 766system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 767system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 2346 # number of hwpf identified 768system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 489 # number of hwpf that were already in mshr 769system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 1139 # number of hwpf that were already in the cache 770system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86 # number of hwpf that were already in the prefetch queue 771system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 772system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 29 # number of hwpf removed because MSHR allocated 773system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 603 # number of hwpf issued 774system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 198 # number of hwpf spanning a virtual page 775system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 776system.cpu.l2cache.tags.replacements 0 # number of replacements 777system.cpu.l2cache.tags.tagsinuse 370.948422 # Cycle average of tags in use 778system.cpu.l2cache.tags.total_refs 270 # Total number of references to valid blocks. 779system.cpu.l2cache.tags.sampled_refs 691 # Sample count of references to valid blocks. 780system.cpu.l2cache.tags.avg_refs 0.390738 # Average number of references to valid blocks. 781system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 782system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.449811 # Average occupied blocks per requestor 783system.cpu.l2cache.tags.occ_blocks::cpu.data 36.598805 # Average occupied blocks per requestor 784system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 303.899806 # Average occupied blocks per requestor 785system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001859 # Average percentage of cache occupancy 786system.cpu.l2cache.tags.occ_percent::cpu.data 0.002234 # Average percentage of cache occupancy 787system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.018549 # Average percentage of cache occupancy 788system.cpu.l2cache.tags.occ_percent::total 0.022641 # Average percentage of cache occupancy 789system.cpu.l2cache.tags.occ_task_id_blocks::1022 570 # Occupied blocks per task id 790system.cpu.l2cache.tags.occ_task_id_blocks::1024 121 # Occupied blocks per task id 791system.cpu.l2cache.tags.age_task_id_blocks_1022::0 471 # Occupied blocks per task id 792system.cpu.l2cache.tags.age_task_id_blocks_1022::1 99 # Occupied blocks per task id 793system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 794system.cpu.l2cache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id 795system.cpu.l2cache.tags.occ_task_id_percent::1022 0.034790 # Percentage of cache occupancy per task id 796system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007385 # Percentage of cache occupancy per task id 797system.cpu.l2cache.tags.tag_accesses 7899 # Number of tag accesses 798system.cpu.l2cache.tags.data_accesses 7899 # Number of data accesses 799system.cpu.l2cache.ReadReq_hits::cpu.inst 234 # number of ReadReq hits 800system.cpu.l2cache.ReadReq_hits::cpu.data 35 # number of ReadReq hits 801system.cpu.l2cache.ReadReq_hits::total 269 # number of ReadReq hits 802system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 803system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 804system.cpu.l2cache.demand_hits::cpu.inst 234 # number of demand (read+write) hits 805system.cpu.l2cache.demand_hits::cpu.data 46 # number of demand (read+write) hits 806system.cpu.l2cache.demand_hits::total 280 # number of demand (read+write) hits 807system.cpu.l2cache.overall_hits::cpu.inst 234 # number of overall hits 808system.cpu.l2cache.overall_hits::cpu.data 46 # number of overall hits 809system.cpu.l2cache.overall_hits::total 280 # number of overall hits 810system.cpu.l2cache.ReadReq_misses::cpu.inst 70 # number of ReadReq misses 811system.cpu.l2cache.ReadReq_misses::cpu.data 69 # number of ReadReq misses 812system.cpu.l2cache.ReadReq_misses::total 139 # number of ReadReq misses 813system.cpu.l2cache.ReadExReq_misses::cpu.data 29 # number of ReadExReq misses 814system.cpu.l2cache.ReadExReq_misses::total 29 # number of ReadExReq misses 815system.cpu.l2cache.demand_misses::cpu.inst 70 # number of demand (read+write) misses 816system.cpu.l2cache.demand_misses::cpu.data 98 # number of demand (read+write) misses 817system.cpu.l2cache.demand_misses::total 168 # number of demand (read+write) misses 818system.cpu.l2cache.overall_misses::cpu.inst 70 # number of overall misses 819system.cpu.l2cache.overall_misses::cpu.data 98 # number of overall misses 820system.cpu.l2cache.overall_misses::total 168 # number of overall misses 821system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 4724750 # number of ReadReq miss cycles 822system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5170750 # number of ReadReq miss cycles 823system.cpu.l2cache.ReadReq_miss_latency::total 9895500 # number of ReadReq miss cycles 824system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2577500 # number of ReadExReq miss cycles 825system.cpu.l2cache.ReadExReq_miss_latency::total 2577500 # number of ReadExReq miss cycles 826system.cpu.l2cache.demand_miss_latency::cpu.inst 4724750 # number of demand (read+write) miss cycles 827system.cpu.l2cache.demand_miss_latency::cpu.data 7748250 # number of demand (read+write) miss cycles 828system.cpu.l2cache.demand_miss_latency::total 12473000 # number of demand (read+write) miss cycles 829system.cpu.l2cache.overall_miss_latency::cpu.inst 4724750 # number of overall miss cycles 830system.cpu.l2cache.overall_miss_latency::cpu.data 7748250 # number of overall miss cycles 831system.cpu.l2cache.overall_miss_latency::total 12473000 # number of overall miss cycles 832system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) 833system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) 834system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) 835system.cpu.l2cache.ReadExReq_accesses::cpu.data 40 # number of ReadExReq accesses(hits+misses) 836system.cpu.l2cache.ReadExReq_accesses::total 40 # number of ReadExReq accesses(hits+misses) 837system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses 838system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses 839system.cpu.l2cache.demand_accesses::total 448 # number of demand (read+write) accesses 840system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses 841system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses 842system.cpu.l2cache.overall_accesses::total 448 # number of overall (read+write) accesses 843system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.230263 # miss rate for ReadReq accesses 844system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.663462 # miss rate for ReadReq accesses 845system.cpu.l2cache.ReadReq_miss_rate::total 0.340686 # miss rate for ReadReq accesses 846system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.725000 # miss rate for ReadExReq accesses 847system.cpu.l2cache.ReadExReq_miss_rate::total 0.725000 # miss rate for ReadExReq accesses 848system.cpu.l2cache.demand_miss_rate::cpu.inst 0.230263 # miss rate for demand accesses 849system.cpu.l2cache.demand_miss_rate::cpu.data 0.680556 # miss rate for demand accesses 850system.cpu.l2cache.demand_miss_rate::total 0.375000 # miss rate for demand accesses 851system.cpu.l2cache.overall_miss_rate::cpu.inst 0.230263 # miss rate for overall accesses 852system.cpu.l2cache.overall_miss_rate::cpu.data 0.680556 # miss rate for overall accesses 853system.cpu.l2cache.overall_miss_rate::total 0.375000 # miss rate for overall accesses 854system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67496.428571 # average ReadReq miss latency 855system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74938.405797 # average ReadReq miss latency 856system.cpu.l2cache.ReadReq_avg_miss_latency::total 71190.647482 # average ReadReq miss latency 857system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88879.310345 # average ReadExReq miss latency 858system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88879.310345 # average ReadExReq miss latency 859system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67496.428571 # average overall miss latency 860system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79063.775510 # average overall miss latency 861system.cpu.l2cache.demand_avg_miss_latency::total 74244.047619 # average overall miss latency 862system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67496.428571 # average overall miss latency 863system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79063.775510 # average overall miss latency 864system.cpu.l2cache.overall_avg_miss_latency::total 74244.047619 # average overall miss latency 865system.cpu.l2cache.blocked_cycles::no_mshrs 388 # number of cycles access was blocked 866system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 867system.cpu.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked 868system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 869system.cpu.l2cache.avg_blocked_cycles::no_mshrs 22.823529 # average number of cycles each access was blocked 870system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 871system.cpu.l2cache.fast_writes 0 # number of fast writes performed 872system.cpu.l2cache.cache_copies 0 # number of cache copies performed 873system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 874system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 875system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 876system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 877system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 878system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 879system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 880system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 881system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 882system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 59 # number of ReadReq MSHR misses 883system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses 884system.cpu.l2cache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses 885system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 603 # number of HardPFReq MSHR misses 886system.cpu.l2cache.HardPFReq_mshr_misses::total 603 # number of HardPFReq MSHR misses 887system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29 # number of ReadExReq MSHR misses 888system.cpu.l2cache.ReadExReq_mshr_misses::total 29 # number of ReadExReq MSHR misses 889system.cpu.l2cache.demand_mshr_misses::cpu.inst 59 # number of demand (read+write) MSHR misses 890system.cpu.l2cache.demand_mshr_misses::cpu.data 92 # number of demand (read+write) MSHR misses 891system.cpu.l2cache.demand_mshr_misses::total 151 # number of demand (read+write) MSHR misses 892system.cpu.l2cache.overall_mshr_misses::cpu.inst 59 # number of overall MSHR misses 893system.cpu.l2cache.overall_mshr_misses::cpu.data 92 # number of overall MSHR misses 894system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 603 # number of overall MSHR misses 895system.cpu.l2cache.overall_mshr_misses::total 754 # number of overall MSHR misses 896system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 3978500 # number of ReadReq MSHR miss cycles 897system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4478500 # number of ReadReq MSHR miss cycles 898system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8457000 # number of ReadReq MSHR miss cycles 899system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of HardPFReq MSHR miss cycles 900system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 49457864 # number of HardPFReq MSHR miss cycles 901system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2337500 # number of ReadExReq MSHR miss cycles 902system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2337500 # number of ReadExReq MSHR miss cycles 903system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 3978500 # number of demand (read+write) MSHR miss cycles 904system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6816000 # number of demand (read+write) MSHR miss cycles 905system.cpu.l2cache.demand_mshr_miss_latency::total 10794500 # number of demand (read+write) MSHR miss cycles 906system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 3978500 # number of overall MSHR miss cycles 907system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6816000 # number of overall MSHR miss cycles 908system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of overall MSHR miss cycles 909system.cpu.l2cache.overall_mshr_miss_latency::total 60252364 # number of overall MSHR miss cycles 910system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for ReadReq accesses 911system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.605769 # mshr miss rate for ReadReq accesses 912system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299020 # mshr miss rate for ReadReq accesses 913system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 914system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 915system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for ReadExReq accesses 916system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.725000 # mshr miss rate for ReadExReq accesses 917system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for demand accesses 918system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for demand accesses 919system.cpu.l2cache.demand_mshr_miss_rate::total 0.337054 # mshr miss rate for demand accesses 920system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for overall accesses 921system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for overall accesses 922system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 923system.cpu.l2cache.overall_mshr_miss_rate::total 1.683036 # mshr miss rate for overall accesses 924system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67432.203390 # average ReadReq mshr miss latency 925system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71087.301587 # average ReadReq mshr miss latency 926system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69319.672131 # average ReadReq mshr miss latency 927system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average HardPFReq mshr miss latency 928system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82019.674959 # average HardPFReq mshr miss latency 929system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80603.448276 # average ReadExReq mshr miss latency 930system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80603.448276 # average ReadExReq mshr miss latency 931system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency 932system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency 933system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71486.754967 # average overall mshr miss latency 934system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency 935system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency 936system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average overall mshr miss latency 937system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79910.297082 # average overall mshr miss latency 938system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 939system.cpu.dcache.tags.replacements 1 # number of replacements 940system.cpu.dcache.tags.tagsinuse 82.309019 # Cycle average of tags in use 941system.cpu.dcache.tags.total_refs 1894 # Total number of references to valid blocks. 942system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. 943system.cpu.dcache.tags.avg_refs 13.244755 # Average number of references to valid blocks. 944system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 945system.cpu.dcache.tags.occ_blocks::cpu.data 82.309019 # Average occupied blocks per requestor 946system.cpu.dcache.tags.occ_percent::cpu.data 0.160760 # Average percentage of cache occupancy 947system.cpu.dcache.tags.occ_percent::total 0.160760 # Average percentage of cache occupancy 948system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 949system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 950system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 951system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id 952system.cpu.dcache.tags.tag_accesses 4719 # Number of tag accesses 953system.cpu.dcache.tags.data_accesses 4719 # Number of data accesses 954system.cpu.dcache.ReadReq_hits::cpu.data 1158 # number of ReadReq hits 955system.cpu.dcache.ReadReq_hits::total 1158 # number of ReadReq hits 956system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits 957system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits 958system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 959system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 960system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 961system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 962system.cpu.dcache.demand_hits::cpu.data 1873 # number of demand (read+write) hits 963system.cpu.dcache.demand_hits::total 1873 # number of demand (read+write) hits 964system.cpu.dcache.overall_hits::cpu.data 1873 # number of overall hits 965system.cpu.dcache.overall_hits::total 1873 # number of overall hits 966system.cpu.dcache.ReadReq_misses::cpu.data 194 # number of ReadReq misses 967system.cpu.dcache.ReadReq_misses::total 194 # number of ReadReq misses 968system.cpu.dcache.WriteReq_misses::cpu.data 198 # number of WriteReq misses 969system.cpu.dcache.WriteReq_misses::total 198 # number of WriteReq misses 970system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 971system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 972system.cpu.dcache.demand_misses::cpu.data 392 # number of demand (read+write) misses 973system.cpu.dcache.demand_misses::total 392 # number of demand (read+write) misses 974system.cpu.dcache.overall_misses::cpu.data 392 # number of overall misses 975system.cpu.dcache.overall_misses::total 392 # number of overall misses 976system.cpu.dcache.ReadReq_miss_latency::cpu.data 10805495 # number of ReadReq miss cycles 977system.cpu.dcache.ReadReq_miss_latency::total 10805495 # number of ReadReq miss cycles 978system.cpu.dcache.WriteReq_miss_latency::cpu.data 8861750 # number of WriteReq miss cycles 979system.cpu.dcache.WriteReq_miss_latency::total 8861750 # number of WriteReq miss cycles 980system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 152500 # number of LoadLockedReq miss cycles 981system.cpu.dcache.LoadLockedReq_miss_latency::total 152500 # number of LoadLockedReq miss cycles 982system.cpu.dcache.demand_miss_latency::cpu.data 19667245 # number of demand (read+write) miss cycles 983system.cpu.dcache.demand_miss_latency::total 19667245 # number of demand (read+write) miss cycles 984system.cpu.dcache.overall_miss_latency::cpu.data 19667245 # number of overall miss cycles 985system.cpu.dcache.overall_miss_latency::total 19667245 # number of overall miss cycles 986system.cpu.dcache.ReadReq_accesses::cpu.data 1352 # number of ReadReq accesses(hits+misses) 987system.cpu.dcache.ReadReq_accesses::total 1352 # number of ReadReq accesses(hits+misses) 988system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 989system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 990system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 991system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 992system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 993system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 994system.cpu.dcache.demand_accesses::cpu.data 2265 # number of demand (read+write) accesses 995system.cpu.dcache.demand_accesses::total 2265 # number of demand (read+write) accesses 996system.cpu.dcache.overall_accesses::cpu.data 2265 # number of overall (read+write) accesses 997system.cpu.dcache.overall_accesses::total 2265 # number of overall (read+write) accesses 998system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.143491 # miss rate for ReadReq accesses 999system.cpu.dcache.ReadReq_miss_rate::total 0.143491 # miss rate for ReadReq accesses 1000system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.216867 # miss rate for WriteReq accesses 1001system.cpu.dcache.WriteReq_miss_rate::total 0.216867 # miss rate for WriteReq accesses 1002system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 1003system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 1004system.cpu.dcache.demand_miss_rate::cpu.data 0.173068 # miss rate for demand accesses 1005system.cpu.dcache.demand_miss_rate::total 0.173068 # miss rate for demand accesses 1006system.cpu.dcache.overall_miss_rate::cpu.data 0.173068 # miss rate for overall accesses 1007system.cpu.dcache.overall_miss_rate::total 0.173068 # miss rate for overall accesses 1008system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835 # average ReadReq miss latency 1009system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835 # average ReadReq miss latency 1010system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131 # average WriteReq miss latency 1011system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131 # average WriteReq miss latency 1012system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76250 # average LoadLockedReq miss latency 1013system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76250 # average LoadLockedReq miss latency 1014system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency 1015system.cpu.dcache.demand_avg_miss_latency::total 50171.543367 # average overall miss latency 1016system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency 1017system.cpu.dcache.overall_avg_miss_latency::total 50171.543367 # average overall miss latency 1018system.cpu.dcache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked 1019system.cpu.dcache.blocked_cycles::no_targets 617 # number of cycles access was blocked 1020system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked 1021system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 1022system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked 1023system.cpu.dcache.avg_blocked_cycles::no_targets 34.277778 # average number of cycles each access was blocked 1024system.cpu.dcache.fast_writes 0 # number of fast writes performed 1025system.cpu.dcache.cache_copies 0 # number of cache copies performed 1026system.cpu.dcache.ReadReq_mshr_hits::cpu.data 90 # number of ReadReq MSHR hits 1027system.cpu.dcache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits 1028system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158 # number of WriteReq MSHR hits 1029system.cpu.dcache.WriteReq_mshr_hits::total 158 # number of WriteReq MSHR hits 1030system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1031system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 1032system.cpu.dcache.demand_mshr_hits::cpu.data 248 # number of demand (read+write) MSHR hits 1033system.cpu.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits 1034system.cpu.dcache.overall_mshr_hits::cpu.data 248 # number of overall MSHR hits 1035system.cpu.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits 1036system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses 1037system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses 1038system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40 # number of WriteReq MSHR misses 1039system.cpu.dcache.WriteReq_mshr_misses::total 40 # number of WriteReq MSHR misses 1040system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses 1041system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses 1042system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses 1043system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses 1044system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5492753 # number of ReadReq MSHR miss cycles 1045system.cpu.dcache.ReadReq_mshr_miss_latency::total 5492753 # number of ReadReq MSHR miss cycles 1046system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689000 # number of WriteReq MSHR miss cycles 1047system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689000 # number of WriteReq MSHR miss cycles 1048system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8181753 # number of demand (read+write) MSHR miss cycles 1049system.cpu.dcache.demand_mshr_miss_latency::total 8181753 # number of demand (read+write) MSHR miss cycles 1050system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8181753 # number of overall MSHR miss cycles 1051system.cpu.dcache.overall_mshr_miss_latency::total 8181753 # number of overall MSHR miss cycles 1052system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for ReadReq accesses 1053system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076923 # mshr miss rate for ReadReq accesses 1054system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.043812 # mshr miss rate for WriteReq accesses 1055system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.043812 # mshr miss rate for WriteReq accesses 1056system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for demand accesses 1057system.cpu.dcache.demand_mshr_miss_rate::total 0.063576 # mshr miss rate for demand accesses 1058system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for overall accesses 1059system.cpu.dcache.overall_mshr_miss_rate::total 0.063576 # mshr miss rate for overall accesses 1060system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692 # average ReadReq mshr miss latency 1061system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692 # average ReadReq mshr miss latency 1062system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67225 # average WriteReq mshr miss latency 1063system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67225 # average WriteReq mshr miss latency 1064system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency 1065system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency 1066system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency 1067system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency 1068system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1069 1070---------- End Simulation Statistics ---------- 1071