1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred 68cacheStorePorts=200 69checker=system.cpu.checker 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dstage2_mmu=system.cpu.dstage2_mmu 86dtb=system.cpu.dtb 87eventq_index=0 88fetchBufferSize=64 89fetchQueueSize=32 90fetchToDecodeDelay=1 91fetchTrapLatency=1 92fetchWidth=8 93forwardComSize=5 94fuPool=system.cpu.fuPool 95function_trace=false 96function_trace_start=0 97iewToCommitDelay=1 98iewToDecodeDelay=1 99iewToFetchDelay=1 100iewToRenameDelay=1 101interrupts=system.cpu.interrupts 102isa=system.cpu.isa 103issueToExecuteDelay=1 104issueWidth=8 105istage2_mmu=system.cpu.istage2_mmu 106itb=system.cpu.itb 107max_insts_all_threads=0 108max_insts_any_thread=0 109max_loads_all_threads=0 110max_loads_any_thread=0 111needsTSO=false 112numIQEntries=64 113numPhysCCRegs=1280 114numPhysFloatRegs=256 115numPhysIntRegs=256 116numROBEntries=192 117numRobs=1 118numThreads=1 119p_state_clk_gate_bins=20 120p_state_clk_gate_max=1000000000000 121p_state_clk_gate_min=1000 122power_model=Null 123profile=0 124progress_interval=0 125renameToDecodeDelay=1 126renameToFetchDelay=1 127renameToIEWDelay=2 128renameToROBDelay=1 129renameWidth=8 130simpoint_start_insts= 131smtCommitPolicy=RoundRobin 132smtFetchPolicy=SingleThread 133smtIQPolicy=Partitioned 134smtIQThreshold=100 135smtLSQPolicy=Partitioned 136smtLSQThreshold=100 137smtNumFetchingThreads=1 138smtROBPolicy=Partitioned 139smtROBThreshold=100 140socket_id=0 141squashWidth=8 142store_set_clear_period=250000 143switched_out=false 144syscallRetryLatency=10000 145system=system 146tracer=system.cpu.tracer 147trapLatency=13 148wbWidth=8 149workload=system.cpu.workload 150dcache_port=system.cpu.dcache.cpu_side 151icache_port=system.cpu.icache.cpu_side 152 153[system.cpu.branchPred] 154type=TournamentBP 155BTBEntries=4096 156BTBTagSize=16 157RASSize=16 158choiceCtrBits=2 159choicePredictorSize=8192 160eventq_index=0 161globalCtrBits=2 162globalPredictorSize=8192 163indirectHashGHR=true 164indirectHashTargets=true 165indirectPathLength=3 166indirectSets=256 167indirectTagSize=16 168indirectWays=2 169instShiftAmt=2 170localCtrBits=2 171localHistoryTableSize=2048 172localPredictorSize=2048 173numThreads=1 174useIndirect=true 175 176[system.cpu.checker] 177type=O3Checker 178children=dstage2_mmu dtb isa istage2_mmu itb tracer 179checker=Null 180clk_domain=system.cpu_clk_domain 181cpu_id=0 182default_p_state=UNDEFINED 183do_checkpoint_insts=true 184do_quiesce=true 185do_statistics_insts=true 186dstage2_mmu=system.cpu.checker.dstage2_mmu 187dtb=system.cpu.checker.dtb 188eventq_index=0 189exitOnError=false 190function_trace=false 191function_trace_start=0 192interrupts= 193isa=system.cpu.checker.isa 194istage2_mmu=system.cpu.checker.istage2_mmu 195itb=system.cpu.checker.itb 196max_insts_all_threads=0 197max_insts_any_thread=0 198max_loads_all_threads=0 199max_loads_any_thread=0 200numThreads=1 201p_state_clk_gate_bins=20 202p_state_clk_gate_max=1000000000000 203p_state_clk_gate_min=1000 204power_model=Null 205profile=0 206progress_interval=0 207simpoint_start_insts= 208socket_id=0 209switched_out=false 210syscallRetryLatency=10000 211system=system 212tracer=system.cpu.checker.tracer 213updateOnError=true 214warnOnlyOnLoadError=true 215workload=system.cpu.workload 216 217[system.cpu.checker.dstage2_mmu] 218type=ArmStage2MMU 219children=stage2_tlb 220eventq_index=0 221stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 222sys=system 223tlb=system.cpu.checker.dtb 224 225[system.cpu.checker.dstage2_mmu.stage2_tlb] 226type=ArmTLB 227children=walker 228eventq_index=0 229is_stage2=true 230size=32 231walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 232 233[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 234type=ArmTableWalker 235clk_domain=system.cpu_clk_domain 236default_p_state=UNDEFINED 237eventq_index=0 238is_stage2=true 239num_squash_per_cycle=2 240p_state_clk_gate_bins=20 241p_state_clk_gate_max=1000000000000 242p_state_clk_gate_min=1000 243power_model=Null 244sys=system 245 246[system.cpu.checker.dtb] 247type=ArmTLB 248children=walker 249eventq_index=0 250is_stage2=false 251size=64 252walker=system.cpu.checker.dtb.walker 253 254[system.cpu.checker.dtb.walker] 255type=ArmTableWalker 256clk_domain=system.cpu_clk_domain 257default_p_state=UNDEFINED 258eventq_index=0 259is_stage2=false 260num_squash_per_cycle=2 261p_state_clk_gate_bins=20 262p_state_clk_gate_max=1000000000000 263p_state_clk_gate_min=1000 264power_model=Null 265sys=system 266port=system.cpu.toL2Bus.slave[5] 267 268[system.cpu.checker.isa] 269type=ArmISA 270decoderFlavour=Generic 271eventq_index=0 272fpsid=1090793632 273id_aa64afr0_el1=0 274id_aa64afr1_el1=0 275id_aa64dfr0_el1=1052678 276id_aa64dfr1_el1=0 277id_aa64isar0_el1=0 278id_aa64isar1_el1=0 279id_aa64mmfr0_el1=15728642 280id_aa64mmfr1_el1=0 281id_isar0=34607377 282id_isar1=34677009 283id_isar2=555950401 284id_isar3=17899825 285id_isar4=268501314 286id_isar5=0 287id_mmfr0=270536963 288id_mmfr1=0 289id_mmfr2=19070976 290id_mmfr3=34611729 291midr=1091551472 292pmu=Null 293system=system 294 295[system.cpu.checker.istage2_mmu] 296type=ArmStage2MMU 297children=stage2_tlb 298eventq_index=0 299stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 300sys=system 301tlb=system.cpu.checker.itb 302 303[system.cpu.checker.istage2_mmu.stage2_tlb] 304type=ArmTLB 305children=walker 306eventq_index=0 307is_stage2=true 308size=32 309walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 310 311[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 312type=ArmTableWalker 313clk_domain=system.cpu_clk_domain 314default_p_state=UNDEFINED 315eventq_index=0 316is_stage2=true 317num_squash_per_cycle=2 318p_state_clk_gate_bins=20 319p_state_clk_gate_max=1000000000000 320p_state_clk_gate_min=1000 321power_model=Null 322sys=system 323 324[system.cpu.checker.itb] 325type=ArmTLB 326children=walker 327eventq_index=0 328is_stage2=false 329size=64 330walker=system.cpu.checker.itb.walker 331 332[system.cpu.checker.itb.walker] 333type=ArmTableWalker 334clk_domain=system.cpu_clk_domain 335default_p_state=UNDEFINED 336eventq_index=0 337is_stage2=false 338num_squash_per_cycle=2 339p_state_clk_gate_bins=20 340p_state_clk_gate_max=1000000000000 341p_state_clk_gate_min=1000 342power_model=Null 343sys=system 344port=system.cpu.toL2Bus.slave[4] 345 346[system.cpu.checker.tracer] 347type=ExeTracer 348eventq_index=0 349 350[system.cpu.dcache] 351type=Cache 352children=tags 353addr_ranges=0:18446744073709551615:0:0:0:0 354assoc=2 355clk_domain=system.cpu_clk_domain 356clusivity=mostly_incl 357data_latency=2 358default_p_state=UNDEFINED 359demand_mshr_reserve=1 360eventq_index=0 361is_read_only=false 362max_miss_count=0 363mshrs=4 364p_state_clk_gate_bins=20 365p_state_clk_gate_max=1000000000000 366p_state_clk_gate_min=1000 367power_model=Null 368prefetch_on_access=false 369prefetcher=Null 370response_latency=2 371sequential_access=false 372size=262144 373system=system 374tag_latency=2 375tags=system.cpu.dcache.tags 376tgts_per_mshr=20 377write_buffers=8 378writeback_clean=false 379cpu_side=system.cpu.dcache_port 380mem_side=system.cpu.toL2Bus.slave[1] 381 382[system.cpu.dcache.tags] 383type=LRU 384assoc=2 385block_size=64 386clk_domain=system.cpu_clk_domain 387data_latency=2 388default_p_state=UNDEFINED 389eventq_index=0 390p_state_clk_gate_bins=20 391p_state_clk_gate_max=1000000000000 392p_state_clk_gate_min=1000 393power_model=Null 394sequential_access=false 395size=262144 396tag_latency=2 397 398[system.cpu.dstage2_mmu] 399type=ArmStage2MMU 400children=stage2_tlb 401eventq_index=0 402stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 403sys=system 404tlb=system.cpu.dtb 405 406[system.cpu.dstage2_mmu.stage2_tlb] 407type=ArmTLB 408children=walker 409eventq_index=0 410is_stage2=true 411size=32 412walker=system.cpu.dstage2_mmu.stage2_tlb.walker 413 414[system.cpu.dstage2_mmu.stage2_tlb.walker] 415type=ArmTableWalker 416clk_domain=system.cpu_clk_domain 417default_p_state=UNDEFINED 418eventq_index=0 419is_stage2=true 420num_squash_per_cycle=2 421p_state_clk_gate_bins=20 422p_state_clk_gate_max=1000000000000 423p_state_clk_gate_min=1000 424power_model=Null 425sys=system 426 427[system.cpu.dtb] 428type=ArmTLB 429children=walker 430eventq_index=0 431is_stage2=false 432size=64 433walker=system.cpu.dtb.walker 434 435[system.cpu.dtb.walker] 436type=ArmTableWalker 437clk_domain=system.cpu_clk_domain 438default_p_state=UNDEFINED 439eventq_index=0 440is_stage2=false 441num_squash_per_cycle=2 442p_state_clk_gate_bins=20 443p_state_clk_gate_max=1000000000000 444p_state_clk_gate_min=1000 445power_model=Null 446sys=system 447port=system.cpu.toL2Bus.slave[3] 448 449[system.cpu.fuPool] 450type=FUPool 451children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 452FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 453eventq_index=0 454 455[system.cpu.fuPool.FUList0] 456type=FUDesc 457children=opList 458count=6 459eventq_index=0 460opList=system.cpu.fuPool.FUList0.opList 461 462[system.cpu.fuPool.FUList0.opList] 463type=OpDesc 464eventq_index=0 465opClass=IntAlu 466opLat=1 467pipelined=true 468 469[system.cpu.fuPool.FUList1] 470type=FUDesc 471children=opList0 opList1 472count=2 473eventq_index=0 474opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 475 476[system.cpu.fuPool.FUList1.opList0] 477type=OpDesc 478eventq_index=0 479opClass=IntMult 480opLat=3 481pipelined=true 482 483[system.cpu.fuPool.FUList1.opList1] 484type=OpDesc 485eventq_index=0 486opClass=IntDiv 487opLat=20 488pipelined=false 489 490[system.cpu.fuPool.FUList2] 491type=FUDesc 492children=opList0 opList1 opList2 493count=4 494eventq_index=0 495opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 496 497[system.cpu.fuPool.FUList2.opList0] 498type=OpDesc 499eventq_index=0 500opClass=FloatAdd 501opLat=2 502pipelined=true 503 504[system.cpu.fuPool.FUList2.opList1] 505type=OpDesc 506eventq_index=0 507opClass=FloatCmp 508opLat=2 509pipelined=true 510 511[system.cpu.fuPool.FUList2.opList2] 512type=OpDesc 513eventq_index=0 514opClass=FloatCvt 515opLat=2 516pipelined=true 517 518[system.cpu.fuPool.FUList3] 519type=FUDesc 520children=opList0 opList1 opList2 opList3 opList4 521count=2 522eventq_index=0 523opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 524 525[system.cpu.fuPool.FUList3.opList0] 526type=OpDesc 527eventq_index=0 528opClass=FloatMult 529opLat=4 530pipelined=true 531 532[system.cpu.fuPool.FUList3.opList1] 533type=OpDesc 534eventq_index=0 535opClass=FloatMultAcc 536opLat=5 537pipelined=true 538 539[system.cpu.fuPool.FUList3.opList2] 540type=OpDesc 541eventq_index=0 542opClass=FloatMisc 543opLat=3 544pipelined=true 545 546[system.cpu.fuPool.FUList3.opList3] 547type=OpDesc 548eventq_index=0 549opClass=FloatDiv 550opLat=12 551pipelined=false 552 553[system.cpu.fuPool.FUList3.opList4] 554type=OpDesc 555eventq_index=0 556opClass=FloatSqrt 557opLat=24 558pipelined=false 559 560[system.cpu.fuPool.FUList4] 561type=FUDesc 562children=opList0 opList1 563count=0 564eventq_index=0 565opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 566 567[system.cpu.fuPool.FUList4.opList0] 568type=OpDesc 569eventq_index=0 570opClass=MemRead 571opLat=1 572pipelined=true 573 574[system.cpu.fuPool.FUList4.opList1] 575type=OpDesc 576eventq_index=0 577opClass=FloatMemRead 578opLat=1 579pipelined=true 580 581[system.cpu.fuPool.FUList5] 582type=FUDesc 583children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 584count=4 585eventq_index=0 586opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 587 588[system.cpu.fuPool.FUList5.opList00] 589type=OpDesc 590eventq_index=0 591opClass=SimdAdd 592opLat=1 593pipelined=true 594 595[system.cpu.fuPool.FUList5.opList01] 596type=OpDesc 597eventq_index=0 598opClass=SimdAddAcc 599opLat=1 600pipelined=true 601 602[system.cpu.fuPool.FUList5.opList02] 603type=OpDesc 604eventq_index=0 605opClass=SimdAlu 606opLat=1 607pipelined=true 608 609[system.cpu.fuPool.FUList5.opList03] 610type=OpDesc 611eventq_index=0 612opClass=SimdCmp 613opLat=1 614pipelined=true 615 616[system.cpu.fuPool.FUList5.opList04] 617type=OpDesc 618eventq_index=0 619opClass=SimdCvt 620opLat=1 621pipelined=true 622 623[system.cpu.fuPool.FUList5.opList05] 624type=OpDesc 625eventq_index=0 626opClass=SimdMisc 627opLat=1 628pipelined=true 629 630[system.cpu.fuPool.FUList5.opList06] 631type=OpDesc 632eventq_index=0 633opClass=SimdMult 634opLat=1 635pipelined=true 636 637[system.cpu.fuPool.FUList5.opList07] 638type=OpDesc 639eventq_index=0 640opClass=SimdMultAcc 641opLat=1 642pipelined=true 643 644[system.cpu.fuPool.FUList5.opList08] 645type=OpDesc 646eventq_index=0 647opClass=SimdShift 648opLat=1 649pipelined=true 650 651[system.cpu.fuPool.FUList5.opList09] 652type=OpDesc 653eventq_index=0 654opClass=SimdShiftAcc 655opLat=1 656pipelined=true 657 658[system.cpu.fuPool.FUList5.opList10] 659type=OpDesc 660eventq_index=0 661opClass=SimdSqrt 662opLat=1 663pipelined=true 664 665[system.cpu.fuPool.FUList5.opList11] 666type=OpDesc 667eventq_index=0 668opClass=SimdFloatAdd 669opLat=1 670pipelined=true 671 672[system.cpu.fuPool.FUList5.opList12] 673type=OpDesc 674eventq_index=0 675opClass=SimdFloatAlu 676opLat=1 677pipelined=true 678 679[system.cpu.fuPool.FUList5.opList13] 680type=OpDesc 681eventq_index=0 682opClass=SimdFloatCmp 683opLat=1 684pipelined=true 685 686[system.cpu.fuPool.FUList5.opList14] 687type=OpDesc 688eventq_index=0 689opClass=SimdFloatCvt 690opLat=1 691pipelined=true 692 693[system.cpu.fuPool.FUList5.opList15] 694type=OpDesc 695eventq_index=0 696opClass=SimdFloatDiv 697opLat=1 698pipelined=true 699 700[system.cpu.fuPool.FUList5.opList16] 701type=OpDesc 702eventq_index=0 703opClass=SimdFloatMisc 704opLat=1 705pipelined=true 706 707[system.cpu.fuPool.FUList5.opList17] 708type=OpDesc 709eventq_index=0 710opClass=SimdFloatMult 711opLat=1 712pipelined=true 713 714[system.cpu.fuPool.FUList5.opList18] 715type=OpDesc 716eventq_index=0 717opClass=SimdFloatMultAcc 718opLat=1 719pipelined=true 720 721[system.cpu.fuPool.FUList5.opList19] 722type=OpDesc 723eventq_index=0 724opClass=SimdFloatSqrt 725opLat=1 726pipelined=true 727 728[system.cpu.fuPool.FUList6] 729type=FUDesc 730children=opList0 opList1 731count=0 732eventq_index=0 733opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 734 735[system.cpu.fuPool.FUList6.opList0] 736type=OpDesc 737eventq_index=0 738opClass=MemWrite 739opLat=1 740pipelined=true 741 742[system.cpu.fuPool.FUList6.opList1] 743type=OpDesc 744eventq_index=0 745opClass=FloatMemWrite 746opLat=1 747pipelined=true 748 749[system.cpu.fuPool.FUList7] 750type=FUDesc 751children=opList0 opList1 opList2 opList3 752count=4 753eventq_index=0 754opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 755 756[system.cpu.fuPool.FUList7.opList0] 757type=OpDesc 758eventq_index=0 759opClass=MemRead 760opLat=1 761pipelined=true 762 763[system.cpu.fuPool.FUList7.opList1] 764type=OpDesc 765eventq_index=0 766opClass=MemWrite 767opLat=1 768pipelined=true 769 770[system.cpu.fuPool.FUList7.opList2] 771type=OpDesc 772eventq_index=0 773opClass=FloatMemRead 774opLat=1 775pipelined=true 776 777[system.cpu.fuPool.FUList7.opList3] 778type=OpDesc 779eventq_index=0 780opClass=FloatMemWrite 781opLat=1 782pipelined=true 783 784[system.cpu.fuPool.FUList8] 785type=FUDesc 786children=opList 787count=1 788eventq_index=0 789opList=system.cpu.fuPool.FUList8.opList 790 791[system.cpu.fuPool.FUList8.opList] 792type=OpDesc 793eventq_index=0 794opClass=IprAccess 795opLat=3 796pipelined=false 797 798[system.cpu.icache] 799type=Cache 800children=tags 801addr_ranges=0:18446744073709551615:0:0:0:0 802assoc=2 803clk_domain=system.cpu_clk_domain 804clusivity=mostly_incl 805data_latency=2 806default_p_state=UNDEFINED 807demand_mshr_reserve=1 808eventq_index=0 809is_read_only=true 810max_miss_count=0 811mshrs=4 812p_state_clk_gate_bins=20 813p_state_clk_gate_max=1000000000000 814p_state_clk_gate_min=1000 815power_model=Null 816prefetch_on_access=false 817prefetcher=Null 818response_latency=2 819sequential_access=false 820size=131072 821system=system 822tag_latency=2 823tags=system.cpu.icache.tags 824tgts_per_mshr=20 825write_buffers=8 826writeback_clean=true 827cpu_side=system.cpu.icache_port 828mem_side=system.cpu.toL2Bus.slave[0] 829 830[system.cpu.icache.tags] 831type=LRU 832assoc=2 833block_size=64 834clk_domain=system.cpu_clk_domain 835data_latency=2 836default_p_state=UNDEFINED 837eventq_index=0 838p_state_clk_gate_bins=20 839p_state_clk_gate_max=1000000000000 840p_state_clk_gate_min=1000 841power_model=Null 842sequential_access=false 843size=131072 844tag_latency=2 845 846[system.cpu.interrupts] 847type=ArmInterrupts 848eventq_index=0 849 850[system.cpu.isa] 851type=ArmISA 852decoderFlavour=Generic 853eventq_index=0 854fpsid=1090793632 855id_aa64afr0_el1=0 856id_aa64afr1_el1=0 857id_aa64dfr0_el1=1052678 858id_aa64dfr1_el1=0 859id_aa64isar0_el1=0 860id_aa64isar1_el1=0 861id_aa64mmfr0_el1=15728642 862id_aa64mmfr1_el1=0 863id_isar0=34607377 864id_isar1=34677009 865id_isar2=555950401 866id_isar3=17899825 867id_isar4=268501314 868id_isar5=0 869id_mmfr0=270536963 870id_mmfr1=0 871id_mmfr2=19070976 872id_mmfr3=34611729 873midr=1091551472 874pmu=Null 875system=system 876 877[system.cpu.istage2_mmu] 878type=ArmStage2MMU 879children=stage2_tlb 880eventq_index=0 881stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 882sys=system 883tlb=system.cpu.itb 884 885[system.cpu.istage2_mmu.stage2_tlb] 886type=ArmTLB 887children=walker 888eventq_index=0 889is_stage2=true 890size=32 891walker=system.cpu.istage2_mmu.stage2_tlb.walker 892 893[system.cpu.istage2_mmu.stage2_tlb.walker] 894type=ArmTableWalker 895clk_domain=system.cpu_clk_domain 896default_p_state=UNDEFINED 897eventq_index=0 898is_stage2=true 899num_squash_per_cycle=2 900p_state_clk_gate_bins=20 901p_state_clk_gate_max=1000000000000 902p_state_clk_gate_min=1000 903power_model=Null 904sys=system 905 906[system.cpu.itb] 907type=ArmTLB 908children=walker 909eventq_index=0 910is_stage2=false 911size=64 912walker=system.cpu.itb.walker 913 914[system.cpu.itb.walker] 915type=ArmTableWalker 916clk_domain=system.cpu_clk_domain 917default_p_state=UNDEFINED 918eventq_index=0 919is_stage2=false 920num_squash_per_cycle=2 921p_state_clk_gate_bins=20 922p_state_clk_gate_max=1000000000000 923p_state_clk_gate_min=1000 924power_model=Null 925sys=system 926port=system.cpu.toL2Bus.slave[2] 927 928[system.cpu.l2cache] 929type=Cache 930children=tags 931addr_ranges=0:18446744073709551615:0:0:0:0 932assoc=8 933clk_domain=system.cpu_clk_domain 934clusivity=mostly_incl 935data_latency=20 936default_p_state=UNDEFINED 937demand_mshr_reserve=1 938eventq_index=0 939is_read_only=false 940max_miss_count=0 941mshrs=20 942p_state_clk_gate_bins=20 943p_state_clk_gate_max=1000000000000 944p_state_clk_gate_min=1000 945power_model=Null 946prefetch_on_access=false 947prefetcher=Null 948response_latency=20 949sequential_access=false 950size=2097152 951system=system 952tag_latency=20 953tags=system.cpu.l2cache.tags 954tgts_per_mshr=12 955write_buffers=8 956writeback_clean=false 957cpu_side=system.cpu.toL2Bus.master[0] 958mem_side=system.membus.slave[1] 959 960[system.cpu.l2cache.tags] 961type=LRU 962assoc=8 963block_size=64 964clk_domain=system.cpu_clk_domain 965data_latency=20 966default_p_state=UNDEFINED 967eventq_index=0 968p_state_clk_gate_bins=20 969p_state_clk_gate_max=1000000000000 970p_state_clk_gate_min=1000 971power_model=Null 972sequential_access=false 973size=2097152 974tag_latency=20 975 976[system.cpu.toL2Bus] 977type=CoherentXBar 978children=snoop_filter 979clk_domain=system.cpu_clk_domain 980default_p_state=UNDEFINED 981eventq_index=0 982forward_latency=0 983frontend_latency=1 984p_state_clk_gate_bins=20 985p_state_clk_gate_max=1000000000000 986p_state_clk_gate_min=1000 987point_of_coherency=false 988power_model=Null 989response_latency=1 990snoop_filter=system.cpu.toL2Bus.snoop_filter 991snoop_response_latency=1 992system=system 993use_default_range=false 994width=32 995master=system.cpu.l2cache.cpu_side 996slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 997 998[system.cpu.toL2Bus.snoop_filter] 999type=SnoopFilter 1000eventq_index=0 1001lookup_latency=0 1002max_capacity=8388608 1003system=system 1004 1005[system.cpu.tracer] 1006type=ExeTracer 1007eventq_index=0 1008 1009[system.cpu.workload] 1010type=Process 1011cmd=hello 1012cwd= 1013drivers= 1014egid=100 1015env= 1016errout=cerr 1017euid=100 1018eventq_index=0 1019executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello 1020gid=100 1021input=cin 1022kvmInSE=false 1023maxStackSize=67108864 1024output=cout 1025pgid=100 1026pid=100 1027ppid=0 1028simpoint=0 1029system=system 1030uid=100 1031useArchPT=false 1032 1033[system.cpu_clk_domain] 1034type=SrcClockDomain 1035clock=500 1036domain_id=-1 1037eventq_index=0 1038init_perf_level=0 1039voltage_domain=system.voltage_domain 1040 1041[system.dvfs_handler] 1042type=DVFSHandler 1043domains= 1044enable=false 1045eventq_index=0 1046sys_clk_domain=system.clk_domain 1047transition_latency=100000000 1048 1049[system.membus] 1050type=CoherentXBar 1051children=snoop_filter 1052clk_domain=system.clk_domain 1053default_p_state=UNDEFINED 1054eventq_index=0 1055forward_latency=4 1056frontend_latency=3 1057p_state_clk_gate_bins=20 1058p_state_clk_gate_max=1000000000000 1059p_state_clk_gate_min=1000 1060point_of_coherency=true 1061power_model=Null 1062response_latency=2 1063snoop_filter=system.membus.snoop_filter 1064snoop_response_latency=4 1065system=system 1066use_default_range=false 1067width=16 1068master=system.physmem.port 1069slave=system.system_port system.cpu.l2cache.mem_side 1070 1071[system.membus.snoop_filter] 1072type=SnoopFilter 1073eventq_index=0 1074lookup_latency=1 1075max_capacity=8388608 1076system=system 1077 1078[system.physmem] 1079type=DRAMCtrl 1080IDD0=0.055000 1081IDD02=0.000000 1082IDD2N=0.032000 1083IDD2N2=0.000000 1084IDD2P0=0.000000 1085IDD2P02=0.000000 1086IDD2P1=0.032000 1087IDD2P12=0.000000 1088IDD3N=0.038000 1089IDD3N2=0.000000 1090IDD3P0=0.000000 1091IDD3P02=0.000000 1092IDD3P1=0.038000 1093IDD3P12=0.000000 1094IDD4R=0.157000 1095IDD4R2=0.000000 1096IDD4W=0.125000 1097IDD4W2=0.000000 1098IDD5=0.235000 1099IDD52=0.000000 1100IDD6=0.020000 1101IDD62=0.000000 1102VDD=1.500000 1103VDD2=0.000000 1104activation_limit=4 1105addr_mapping=RoRaBaCoCh 1106bank_groups_per_rank=0 1107banks_per_rank=8 1108burst_length=8 1109channels=1 1110clk_domain=system.clk_domain 1111conf_table_reported=true 1112default_p_state=UNDEFINED 1113device_bus_width=8 1114device_rowbuffer_size=1024 1115device_size=536870912 1116devices_per_rank=8 1117dll=true 1118eventq_index=0 1119in_addr_map=true 1120kvm_map=true 1121max_accesses_per_row=16 1122mem_sched_policy=frfcfs 1123min_writes_per_switch=16 1124null=false 1125p_state_clk_gate_bins=20 1126p_state_clk_gate_max=1000000000000 1127p_state_clk_gate_min=1000 1128page_policy=open_adaptive 1129power_model=Null 1130range=0:134217727:0:0:0:0 1131ranks_per_channel=2 1132read_buffer_size=32 1133static_backend_latency=10000 1134static_frontend_latency=10000 1135tBURST=5000 1136tCCD_L=0 1137tCK=1250 1138tCL=13750 1139tCS=2500 1140tRAS=35000 1141tRCD=13750 1142tREFI=7800000 1143tRFC=260000 1144tRP=13750 1145tRRD=6000 1146tRRD_L=0 1147tRTP=7500 1148tRTW=2500 1149tWR=15000 1150tWTR=7500 1151tXAW=30000 1152tXP=6000 1153tXPDLL=0 1154tXS=270000 1155tXSDLL=0 1156write_buffer_size=64 1157write_high_thresh_perc=85 1158write_low_thresh_perc=50 1159port=system.membus.master[0] 1160 1161[system.voltage_domain] 1162type=VoltageDomain 1163eventq_index=0 1164voltage=1.000000 1165 1166