stats.txt revision 9838:43d22d746e7a
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.196173 # Number of seconds simulated 4sim_ticks 5196173457000 # Number of ticks simulated 5final_tick 5196173457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 457062 # Simulator instruction rate (inst/s) 8host_op_rate 881101 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18514311716 # Simulator tick rate (ticks/s) 10host_mem_usage 585140 # Number of bytes of host memory used 11host_seconds 280.66 # Real time elapsed on the host 12sim_insts 128277551 # Number of instructions simulated 13sim_ops 247287193 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2879808 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 826368 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8990464 # Number of bytes read from this memory 19system.physmem.bytes_read::total 12697024 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 826368 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 826368 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 8117888 # Number of bytes written to this memory 23system.physmem.bytes_written::total 8117888 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 44997 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 12912 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 140476 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 198391 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 126842 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 126842 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 554217 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 159034 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 1730209 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2443534 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 159034 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 159034 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1562282 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1562282 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1562282 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 554217 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 159034 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 1730209 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4005815 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 198391 # Total number of read requests accepted by DRAM controller 50system.physmem.writeReqs 126842 # Total number of write requests accepted by DRAM controller 51system.physmem.readBursts 198391 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 52system.physmem.writeBursts 126842 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 53system.physmem.bytesRead 12697024 # Total number of bytes read from memory 54system.physmem.bytesWritten 8117888 # Total number of bytes written to memory 55system.physmem.bytesConsumedRd 12697024 # bytesRead derated as per pkt->getSize() 56system.physmem.bytesConsumedWr 8117888 # bytesWritten derated as per pkt->getSize() 57system.physmem.servicedByWrQ 80 # Number of DRAM read bursts serviced by write Q 58system.physmem.neitherReadNorWrite 1638 # Reqs where no action is needed 59system.physmem.perBankRdReqs::0 12755 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::1 12192 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::2 12372 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::3 12296 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::4 12564 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::5 12318 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::6 12219 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::7 12027 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::8 12046 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::9 12112 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::10 12490 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::11 12561 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::12 12978 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::13 12970 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::14 12385 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::15 12026 # Track reads on a per bank basis 75system.physmem.perBankWrReqs::0 8334 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::1 7768 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::2 7804 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::3 7872 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::4 8132 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::5 7928 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::6 7689 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::7 7630 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::8 7475 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::9 7683 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::10 8127 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::11 7959 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::12 8470 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::13 8471 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::14 7991 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::15 7509 # Track writes on a per bank basis 91system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 92system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry 93system.physmem.totGap 5196173392500 # Total gap between requests 94system.physmem.readPktSize::0 0 # Categorize read packet sizes 95system.physmem.readPktSize::1 0 # Categorize read packet sizes 96system.physmem.readPktSize::2 0 # Categorize read packet sizes 97system.physmem.readPktSize::3 0 # Categorize read packet sizes 98system.physmem.readPktSize::4 0 # Categorize read packet sizes 99system.physmem.readPktSize::5 0 # Categorize read packet sizes 100system.physmem.readPktSize::6 198391 # Categorize read packet sizes 101system.physmem.writePktSize::0 0 # Categorize write packet sizes 102system.physmem.writePktSize::1 0 # Categorize write packet sizes 103system.physmem.writePktSize::2 0 # Categorize write packet sizes 104system.physmem.writePktSize::3 0 # Categorize write packet sizes 105system.physmem.writePktSize::4 0 # Categorize write packet sizes 106system.physmem.writePktSize::5 0 # Categorize write packet sizes 107system.physmem.writePktSize::6 126842 # Categorize write packet sizes 108system.physmem.rdQLenPdf::0 155016 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 13333 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 7466 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 2991 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 2873 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 2490 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 1473 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 1327 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 1269 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 1177 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 1109 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 1086 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 1030 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 1124 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 1206 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 1161 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 914 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 651 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 362 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 223 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.wrQLenPdf::0 4302 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::1 4658 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::2 5452 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::3 5504 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::4 5507 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::5 5510 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::6 5511 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::7 5512 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::8 5513 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::9 5515 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::10 5515 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::11 5515 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::12 5515 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::13 5515 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::14 5515 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::15 5515 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::16 5515 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::17 5515 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::18 5515 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::19 5515 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::20 5514 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::21 5514 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::22 5514 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::23 1213 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::24 857 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::25 63 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see 172system.physmem.bytesPerActivate::samples 45212 # Bytes accessed per row activation 173system.physmem.bytesPerActivate::mean 459.873662 # Bytes accessed per row activation 174system.physmem.bytesPerActivate::gmean 169.351443 # Bytes accessed per row activation 175system.physmem.bytesPerActivate::stdev 1570.406469 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::64-67 18373 40.64% 40.64% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::128-131 7212 15.95% 56.59% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::192-195 4299 9.51% 66.10% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::256-259 2899 6.41% 72.51% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::320-323 2036 4.50% 77.01% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::384-387 1645 3.64% 80.65% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::448-451 1210 2.68% 83.33% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::512-515 976 2.16% 85.49% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::576-579 783 1.73% 87.22% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::640-643 608 1.34% 88.56% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::704-707 508 1.12% 89.69% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::768-771 473 1.05% 90.73% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::832-835 299 0.66% 91.39% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::896-899 322 0.71% 92.11% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::960-963 227 0.50% 92.61% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1024-1027 394 0.87% 93.48% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1088-1091 154 0.34% 93.82% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1152-1155 143 0.32% 94.14% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1216-1219 136 0.30% 94.44% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1280-1283 125 0.28% 94.71% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1344-1347 123 0.27% 94.99% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1408-1411 132 0.29% 95.28% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1472-1475 601 1.33% 96.61% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1536-1539 193 0.43% 97.03% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1600-1603 92 0.20% 97.24% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1664-1667 79 0.17% 97.41% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1728-1731 66 0.15% 97.56% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1792-1795 49 0.11% 97.67% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1856-1859 20 0.04% 97.71% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1920-1923 25 0.06% 97.77% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1984-1987 17 0.04% 97.80% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2048-2051 28 0.06% 97.87% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2112-2115 17 0.04% 97.90% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2176-2179 13 0.03% 97.93% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2240-2243 13 0.03% 97.96% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2304-2307 10 0.02% 97.98% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2368-2371 13 0.03% 98.01% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2432-2435 7 0.02% 98.03% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2496-2499 10 0.02% 98.05% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2560-2563 19 0.04% 98.09% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.10% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2688-2691 2 0.00% 98.10% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2752-2755 5 0.01% 98.12% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2816-2819 2 0.00% 98.12% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2880-2883 2 0.00% 98.12% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2944-2947 3 0.01% 98.13% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3008-3011 6 0.01% 98.14% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3072-3075 4 0.01% 98.15% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3136-3139 5 0.01% 98.16% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3200-3203 3 0.01% 98.17% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3328-3331 2 0.00% 98.18% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.18% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3456-3459 8 0.02% 98.20% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3648-3651 1 0.00% 98.20% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3712-3715 2 0.00% 98.20% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3776-3779 15 0.03% 98.24% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3904-3907 3 0.01% 98.24% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3968-3971 1 0.00% 98.25% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4032-4035 2 0.00% 98.25% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4096-4099 13 0.03% 98.28% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.29% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4224-4227 3 0.01% 98.30% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.30% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.31% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4416-4419 3 0.01% 98.32% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4480-4483 3 0.01% 98.33% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4544-4547 3 0.01% 98.33% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4608-4611 1 0.00% 98.33% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.34% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.34% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.35% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.35% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5056-5059 4 0.01% 98.36% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5120-5123 3 0.01% 98.36% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.37% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5248-5251 3 0.01% 98.37% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.37% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.38% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.38% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5504-5507 3 0.01% 98.39% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.39% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5760-5763 2 0.00% 98.39% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.39% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.40% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::6016-6019 1 0.00% 98.40% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::6080-6083 2 0.00% 98.40% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.41% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6336-6339 1 0.00% 98.41% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6400-6403 1 0.00% 98.41% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.41% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6592-6595 2 0.00% 98.42% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6720-6723 5 0.01% 98.43% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6784-6787 1 0.00% 98.43% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6848-6851 8 0.02% 98.45% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6912-6915 2 0.00% 98.45% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::7040-7043 4 0.01% 98.46% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.47% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::7424-7427 2 0.00% 98.47% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.48% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.48% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.48% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.48% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.49% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.49% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::8192-8195 342 0.76% 99.25% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::8320-8323 2 0.00% 99.25% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::8384-8387 3 0.01% 99.26% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::8448-8451 2 0.00% 99.26% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::8512-8515 2 0.00% 99.27% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.27% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.28% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.28% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::9408-9411 2 0.00% 99.29% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.29% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.29% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.29% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.30% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.30% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.30% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.30% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.31% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.31% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.31% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.31% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.32% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.32% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.32% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.32% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.33% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.33% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.33% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::14912-14915 6 0.01% 99.35% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.35% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::15040-15043 2 0.00% 99.35% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::15104-15107 2 0.00% 99.36% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.36% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::15360-15363 5 0.01% 99.37% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.37% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::16384-16387 241 0.53% 99.90% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::16448-16451 16 0.04% 99.94% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::16512-16515 8 0.02% 99.96% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.96% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::16640-16643 6 0.01% 99.98% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.99% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.99% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.99% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.99% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::17408-17411 1 0.00% 100.00% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::17472-17475 1 0.00% 100.00% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::total 45212 # Bytes accessed per row activation 327system.physmem.totQLat 3446222750 # Total cycles spent in queuing delays 328system.physmem.totMemAccLat 7081229000 # Sum of mem lat for all requests 329system.physmem.totBusLat 991555000 # Total cycles spent in databus access 330system.physmem.totBankLat 2643451250 # Total cycles spent in bank access 331system.physmem.avgQLat 17377.87 # Average queueing delay per request 332system.physmem.avgBankLat 13329.83 # Average bank access latency per request 333system.physmem.avgBusLat 5000.00 # Average bus latency per request 334system.physmem.avgMemAccLat 35707.70 # Average memory access latency 335system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s 336system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s 337system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s 338system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s 339system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 340system.physmem.busUtil 0.03 # Data bus utilization in percentage 341system.physmem.avgRdQLen 0.00 # Average read queue length over time 342system.physmem.avgWrQLen 12.20 # Average write queue length over time 343system.physmem.readRowHits 181450 # Number of row buffer hits during reads 344system.physmem.writeRowHits 98471 # Number of row buffer hits during writes 345system.physmem.readRowHitRate 91.50 # Row buffer hit rate for reads 346system.physmem.writeRowHitRate 77.63 # Row buffer hit rate for writes 347system.physmem.avgGap 15976771.71 # Average gap between requests 348system.membus.throughput 4367376 # Throughput (bytes/s) 349system.membus.trans_dist::ReadReq 623405 # Transaction distribution 350system.membus.trans_dist::ReadResp 623405 # Transaction distribution 351system.membus.trans_dist::WriteReq 13711 # Transaction distribution 352system.membus.trans_dist::WriteResp 13711 # Transaction distribution 353system.membus.trans_dist::Writeback 126842 # Transaction distribution 354system.membus.trans_dist::UpgradeReq 2139 # Transaction distribution 355system.membus.trans_dist::UpgradeResp 1656 # Transaction distribution 356system.membus.trans_dist::ReadExReq 159580 # Transaction distribution 357system.membus.trans_dist::ReadExResp 159580 # Transaction distribution 358system.membus.trans_dist::MessageReq 1655 # Transaction distribution 359system.membus.trans_dist::MessageResp 1655 # Transaction distribution 360system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) 361system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) 362system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480072 # Packet count per connected master and slave (bytes) 363system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) 364system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391390 # Packet count per connected master and slave (bytes) 365system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581576 # Packet count per connected master and slave (bytes) 366system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139223 # Packet count per connected master and slave (bytes) 367system.membus.pkt_count_system.iocache.mem_side::total 139223 # Packet count per connected master and slave (bytes) 368system.membus.pkt_count::total 1724109 # Packet count per connected master and slave (bytes) 369system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) 370system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) 371system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes) 372system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) 373system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14948416 # Cumulative packet size per connected master and slave (bytes) 374system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16614957 # Cumulative packet size per connected master and slave (bytes) 375system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5866496 # Cumulative packet size per connected master and slave (bytes) 376system.membus.tot_pkt_size_system.iocache.mem_side::total 5866496 # Cumulative packet size per connected master and slave (bytes) 377system.membus.tot_pkt_size::total 22488073 # Cumulative packet size per connected master and slave (bytes) 378system.membus.data_through_bus 22488073 # Total data (bytes) 379system.membus.snoop_data_through_bus 205568 # Total snoop data (bytes) 380system.membus.reqLayer0.occupancy 256571500 # Layer occupancy (ticks) 381system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 382system.membus.reqLayer1.occupancy 359320500 # Layer occupancy (ticks) 383system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 384system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) 385system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 386system.membus.reqLayer3.occupancy 1351024000 # Layer occupancy (ticks) 387system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 388system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) 389system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 390system.membus.respLayer2.occupancy 2612485256 # Layer occupancy (ticks) 391system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 392system.membus.respLayer4.occupancy 428859500 # Layer occupancy (ticks) 393system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 394system.iocache.tags.replacements 47504 # number of replacements 395system.iocache.tags.tagsinuse 0.125284 # Cycle average of tags in use 396system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 397system.iocache.tags.sampled_refs 47520 # Sample count of references to valid blocks. 398system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 399system.iocache.tags.warmup_cycle 5049571138000 # Cycle when the warmup percentage was hit. 400system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.125284 # Average occupied blocks per requestor 401system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007830 # Average percentage of cache occupancy 402system.iocache.tags.occ_percent::total 0.007830 # Average percentage of cache occupancy 403system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses 404system.iocache.ReadReq_misses::total 839 # number of ReadReq misses 405system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 406system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 407system.iocache.demand_misses::pc.south_bridge.ide 47559 # number of demand (read+write) misses 408system.iocache.demand_misses::total 47559 # number of demand (read+write) misses 409system.iocache.overall_misses::pc.south_bridge.ide 47559 # number of overall misses 410system.iocache.overall_misses::total 47559 # number of overall misses 411system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142400936 # number of ReadReq miss cycles 412system.iocache.ReadReq_miss_latency::total 142400936 # number of ReadReq miss cycles 413system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10875044083 # number of WriteReq miss cycles 414system.iocache.WriteReq_miss_latency::total 10875044083 # number of WriteReq miss cycles 415system.iocache.demand_miss_latency::pc.south_bridge.ide 11017445019 # number of demand (read+write) miss cycles 416system.iocache.demand_miss_latency::total 11017445019 # number of demand (read+write) miss cycles 417system.iocache.overall_miss_latency::pc.south_bridge.ide 11017445019 # number of overall miss cycles 418system.iocache.overall_miss_latency::total 11017445019 # number of overall miss cycles 419system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses) 420system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses) 421system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 422system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 423system.iocache.demand_accesses::pc.south_bridge.ide 47559 # number of demand (read+write) accesses 424system.iocache.demand_accesses::total 47559 # number of demand (read+write) accesses 425system.iocache.overall_accesses::pc.south_bridge.ide 47559 # number of overall (read+write) accesses 426system.iocache.overall_accesses::total 47559 # number of overall (read+write) accesses 427system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 428system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 429system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 430system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 431system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 432system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 433system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 434system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 435system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 169726.979738 # average ReadReq miss latency 436system.iocache.ReadReq_avg_miss_latency::total 169726.979738 # average ReadReq miss latency 437system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 232770.635338 # average WriteReq miss latency 438system.iocache.WriteReq_avg_miss_latency::total 232770.635338 # average WriteReq miss latency 439system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 231658.466726 # average overall miss latency 440system.iocache.demand_avg_miss_latency::total 231658.466726 # average overall miss latency 441system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 231658.466726 # average overall miss latency 442system.iocache.overall_avg_miss_latency::total 231658.466726 # average overall miss latency 443system.iocache.blocked_cycles::no_mshrs 178608 # number of cycles access was blocked 444system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 445system.iocache.blocked::no_mshrs 16401 # number of cycles access was blocked 446system.iocache.blocked::no_targets 0 # number of cycles access was blocked 447system.iocache.avg_blocked_cycles::no_mshrs 10.890068 # average number of cycles each access was blocked 448system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 449system.iocache.fast_writes 0 # number of fast writes performed 450system.iocache.cache_copies 0 # number of cache copies performed 451system.iocache.writebacks::writebacks 46667 # number of writebacks 452system.iocache.writebacks::total 46667 # number of writebacks 453system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses 454system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses 455system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 456system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 457system.iocache.demand_mshr_misses::pc.south_bridge.ide 47559 # number of demand (read+write) MSHR misses 458system.iocache.demand_mshr_misses::total 47559 # number of demand (read+write) MSHR misses 459system.iocache.overall_mshr_misses::pc.south_bridge.ide 47559 # number of overall MSHR misses 460system.iocache.overall_mshr_misses::total 47559 # number of overall MSHR misses 461system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98742936 # number of ReadReq MSHR miss cycles 462system.iocache.ReadReq_mshr_miss_latency::total 98742936 # number of ReadReq MSHR miss cycles 463system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8443977083 # number of WriteReq MSHR miss cycles 464system.iocache.WriteReq_mshr_miss_latency::total 8443977083 # number of WriteReq MSHR miss cycles 465system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8542720019 # number of demand (read+write) MSHR miss cycles 466system.iocache.demand_mshr_miss_latency::total 8542720019 # number of demand (read+write) MSHR miss cycles 467system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8542720019 # number of overall MSHR miss cycles 468system.iocache.overall_mshr_miss_latency::total 8542720019 # number of overall MSHR miss cycles 469system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 470system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 471system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 472system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 473system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 474system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 475system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 476system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 477system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117691.222884 # average ReadReq mshr miss latency 478system.iocache.ReadReq_avg_mshr_miss_latency::total 117691.222884 # average ReadReq mshr miss latency 479system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 180735.810852 # average WriteReq mshr miss latency 480system.iocache.WriteReq_avg_mshr_miss_latency::total 180735.810852 # average WriteReq mshr miss latency 481system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 179623.625791 # average overall mshr miss latency 482system.iocache.demand_avg_mshr_miss_latency::total 179623.625791 # average overall mshr miss latency 483system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 179623.625791 # average overall mshr miss latency 484system.iocache.overall_avg_mshr_miss_latency::total 179623.625791 # average overall mshr miss latency 485system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 486system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 487system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 488system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 489system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 490system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 491system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 492system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 493system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 494system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 495system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 496system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 497system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 498system.iobus.throughput 631271 # Throughput (bytes/s) 499system.iobus.trans_dist::ReadReq 230080 # Transaction distribution 500system.iobus.trans_dist::ReadResp 230080 # Transaction distribution 501system.iobus.trans_dist::WriteReq 57515 # Transaction distribution 502system.iobus.trans_dist::WriteResp 57515 # Transaction distribution 503system.iobus.trans_dist::MessageReq 1655 # Transaction distribution 504system.iobus.trans_dist::MessageResp 1655 # Transaction distribution 505system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 506system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 507system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 508system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 509system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 510system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 511system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 512system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 513system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) 514system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 515system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 516system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 517system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) 518system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 519system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 520system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 521system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 522system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 523system.iobus.pkt_count_system.bridge.master::total 480072 # Packet count per connected master and slave (bytes) 524system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes) 525system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes) 526system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) 527system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) 528system.iobus.pkt_count::total 578500 # Packet count per connected master and slave (bytes) 529system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 530system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 531system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 532system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 533system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 534system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 535system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 536system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 537system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 538system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 539system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 540system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 541system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) 542system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 543system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 544system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 545system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 546system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 547system.iobus.tot_pkt_size_system.bridge.master::total 246316 # Cumulative packet size per connected master and slave (bytes) 548system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes) 549system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes) 550system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) 551system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) 552system.iobus.tot_pkt_size::total 3280192 # Cumulative packet size per connected master and slave (bytes) 553system.iobus.data_through_bus 3280192 # Total data (bytes) 554system.iobus.reqLayer0.occupancy 3949164 # Layer occupancy (ticks) 555system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 556system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 557system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 558system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 559system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 560system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 561system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 562system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 563system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 564system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 565system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 566system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) 567system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 568system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 569system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 570system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 571system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 572system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) 573system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 574system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 575system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 576system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 577system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 578system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 579system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 580system.iobus.reqLayer13.occupancy 20182000 # Layer occupancy (ticks) 581system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 582system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 583system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 584system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 585system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 586system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 587system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 588system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 589system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 590system.iobus.reqLayer18.occupancy 424368519 # Layer occupancy (ticks) 591system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 592system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 593system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 594system.iobus.respLayer0.occupancy 469277000 # Layer occupancy (ticks) 595system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 596system.iobus.respLayer1.occupancy 53493500 # Layer occupancy (ticks) 597system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 598system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) 599system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 600system.cpu.numCycles 10392346914 # number of cpu cycles simulated 601system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 602system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 603system.cpu.committedInsts 128277551 # Number of instructions committed 604system.cpu.committedOps 247287193 # Number of ops (including micro ops) committed 605system.cpu.num_int_alu_accesses 232021751 # Number of integer alu accesses 606system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 607system.cpu.num_func_calls 2299501 # number of times a function call or return occured 608system.cpu.num_conditional_control_insts 23156792 # number of instructions that are conditional controls 609system.cpu.num_int_insts 232021751 # number of integer instructions 610system.cpu.num_fp_insts 0 # number of float instructions 611system.cpu.num_int_register_reads 567075946 # number of times the integer registers were read 612system.cpu.num_int_register_writes 293251743 # number of times the integer registers were written 613system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 614system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 615system.cpu.num_mem_refs 22231243 # number of memory refs 616system.cpu.num_load_insts 13871494 # Number of load instructions 617system.cpu.num_store_insts 8359749 # Number of store instructions 618system.cpu.num_idle_cycles 9785544869.998116 # Number of idle cycles 619system.cpu.num_busy_cycles 606802044.001883 # Number of busy cycles 620system.cpu.not_idle_fraction 0.058389 # Percentage of non-idle cycles 621system.cpu.idle_fraction 0.941611 # Percentage of idle cycles 622system.cpu.kern.inst.arm 0 # number of arm instructions executed 623system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 624system.cpu.icache.tags.replacements 791620 # number of replacements 625system.cpu.icache.tags.tagsinuse 510.364411 # Cycle average of tags in use 626system.cpu.icache.tags.total_refs 144498695 # Total number of references to valid blocks. 627system.cpu.icache.tags.sampled_refs 792132 # Sample count of references to valid blocks. 628system.cpu.icache.tags.avg_refs 182.417444 # Average number of references to valid blocks. 629system.cpu.icache.tags.warmup_cycle 161170792250 # Cycle when the warmup percentage was hit. 630system.cpu.icache.tags.occ_blocks::cpu.inst 510.364411 # Average occupied blocks per requestor 631system.cpu.icache.tags.occ_percent::cpu.inst 0.996805 # Average percentage of cache occupancy 632system.cpu.icache.tags.occ_percent::total 0.996805 # Average percentage of cache occupancy 633system.cpu.icache.ReadReq_hits::cpu.inst 144498695 # number of ReadReq hits 634system.cpu.icache.ReadReq_hits::total 144498695 # number of ReadReq hits 635system.cpu.icache.demand_hits::cpu.inst 144498695 # number of demand (read+write) hits 636system.cpu.icache.demand_hits::total 144498695 # number of demand (read+write) hits 637system.cpu.icache.overall_hits::cpu.inst 144498695 # number of overall hits 638system.cpu.icache.overall_hits::total 144498695 # number of overall hits 639system.cpu.icache.ReadReq_misses::cpu.inst 792139 # number of ReadReq misses 640system.cpu.icache.ReadReq_misses::total 792139 # number of ReadReq misses 641system.cpu.icache.demand_misses::cpu.inst 792139 # number of demand (read+write) misses 642system.cpu.icache.demand_misses::total 792139 # number of demand (read+write) misses 643system.cpu.icache.overall_misses::cpu.inst 792139 # number of overall misses 644system.cpu.icache.overall_misses::total 792139 # number of overall misses 645system.cpu.icache.ReadReq_miss_latency::cpu.inst 11198521009 # number of ReadReq miss cycles 646system.cpu.icache.ReadReq_miss_latency::total 11198521009 # number of ReadReq miss cycles 647system.cpu.icache.demand_miss_latency::cpu.inst 11198521009 # number of demand (read+write) miss cycles 648system.cpu.icache.demand_miss_latency::total 11198521009 # number of demand (read+write) miss cycles 649system.cpu.icache.overall_miss_latency::cpu.inst 11198521009 # number of overall miss cycles 650system.cpu.icache.overall_miss_latency::total 11198521009 # number of overall miss cycles 651system.cpu.icache.ReadReq_accesses::cpu.inst 145290834 # number of ReadReq accesses(hits+misses) 652system.cpu.icache.ReadReq_accesses::total 145290834 # number of ReadReq accesses(hits+misses) 653system.cpu.icache.demand_accesses::cpu.inst 145290834 # number of demand (read+write) accesses 654system.cpu.icache.demand_accesses::total 145290834 # number of demand (read+write) accesses 655system.cpu.icache.overall_accesses::cpu.inst 145290834 # number of overall (read+write) accesses 656system.cpu.icache.overall_accesses::total 145290834 # number of overall (read+write) accesses 657system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005452 # miss rate for ReadReq accesses 658system.cpu.icache.ReadReq_miss_rate::total 0.005452 # miss rate for ReadReq accesses 659system.cpu.icache.demand_miss_rate::cpu.inst 0.005452 # miss rate for demand accesses 660system.cpu.icache.demand_miss_rate::total 0.005452 # miss rate for demand accesses 661system.cpu.icache.overall_miss_rate::cpu.inst 0.005452 # miss rate for overall accesses 662system.cpu.icache.overall_miss_rate::total 0.005452 # miss rate for overall accesses 663system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14137.065602 # average ReadReq miss latency 664system.cpu.icache.ReadReq_avg_miss_latency::total 14137.065602 # average ReadReq miss latency 665system.cpu.icache.demand_avg_miss_latency::cpu.inst 14137.065602 # average overall miss latency 666system.cpu.icache.demand_avg_miss_latency::total 14137.065602 # average overall miss latency 667system.cpu.icache.overall_avg_miss_latency::cpu.inst 14137.065602 # average overall miss latency 668system.cpu.icache.overall_avg_miss_latency::total 14137.065602 # average overall miss latency 669system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 670system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 671system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 672system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 673system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 674system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 675system.cpu.icache.fast_writes 0 # number of fast writes performed 676system.cpu.icache.cache_copies 0 # number of cache copies performed 677system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792139 # number of ReadReq MSHR misses 678system.cpu.icache.ReadReq_mshr_misses::total 792139 # number of ReadReq MSHR misses 679system.cpu.icache.demand_mshr_misses::cpu.inst 792139 # number of demand (read+write) MSHR misses 680system.cpu.icache.demand_mshr_misses::total 792139 # number of demand (read+write) MSHR misses 681system.cpu.icache.overall_mshr_misses::cpu.inst 792139 # number of overall MSHR misses 682system.cpu.icache.overall_mshr_misses::total 792139 # number of overall MSHR misses 683system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9607971991 # number of ReadReq MSHR miss cycles 684system.cpu.icache.ReadReq_mshr_miss_latency::total 9607971991 # number of ReadReq MSHR miss cycles 685system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9607971991 # number of demand (read+write) MSHR miss cycles 686system.cpu.icache.demand_mshr_miss_latency::total 9607971991 # number of demand (read+write) MSHR miss cycles 687system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9607971991 # number of overall MSHR miss cycles 688system.cpu.icache.overall_mshr_miss_latency::total 9607971991 # number of overall MSHR miss cycles 689system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005452 # mshr miss rate for ReadReq accesses 690system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005452 # mshr miss rate for ReadReq accesses 691system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005452 # mshr miss rate for demand accesses 692system.cpu.icache.demand_mshr_miss_rate::total 0.005452 # mshr miss rate for demand accesses 693system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005452 # mshr miss rate for overall accesses 694system.cpu.icache.overall_mshr_miss_rate::total 0.005452 # mshr miss rate for overall accesses 695system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12129.149039 # average ReadReq mshr miss latency 696system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12129.149039 # average ReadReq mshr miss latency 697system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12129.149039 # average overall mshr miss latency 698system.cpu.icache.demand_avg_mshr_miss_latency::total 12129.149039 # average overall mshr miss latency 699system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12129.149039 # average overall mshr miss latency 700system.cpu.icache.overall_avg_mshr_miss_latency::total 12129.149039 # average overall mshr miss latency 701system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 702system.cpu.itb_walker_cache.tags.replacements 3473 # number of replacements 703system.cpu.itb_walker_cache.tags.tagsinuse 3.080805 # Cycle average of tags in use 704system.cpu.itb_walker_cache.tags.total_refs 7889 # Total number of references to valid blocks. 705system.cpu.itb_walker_cache.tags.sampled_refs 3486 # Sample count of references to valid blocks. 706system.cpu.itb_walker_cache.tags.avg_refs 2.263052 # Average number of references to valid blocks. 707system.cpu.itb_walker_cache.tags.warmup_cycle 5163044300000 # Cycle when the warmup percentage was hit. 708system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.080805 # Average occupied blocks per requestor 709system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192550 # Average percentage of cache occupancy 710system.cpu.itb_walker_cache.tags.occ_percent::total 0.192550 # Average percentage of cache occupancy 711system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7889 # number of ReadReq hits 712system.cpu.itb_walker_cache.ReadReq_hits::total 7889 # number of ReadReq hits 713system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 714system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 715system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7891 # number of demand (read+write) hits 716system.cpu.itb_walker_cache.demand_hits::total 7891 # number of demand (read+write) hits 717system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7891 # number of overall hits 718system.cpu.itb_walker_cache.overall_hits::total 7891 # number of overall hits 719system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4335 # number of ReadReq misses 720system.cpu.itb_walker_cache.ReadReq_misses::total 4335 # number of ReadReq misses 721system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4335 # number of demand (read+write) misses 722system.cpu.itb_walker_cache.demand_misses::total 4335 # number of demand (read+write) misses 723system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4335 # number of overall misses 724system.cpu.itb_walker_cache.overall_misses::total 4335 # number of overall misses 725system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44091250 # number of ReadReq miss cycles 726system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44091250 # number of ReadReq miss cycles 727system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44091250 # number of demand (read+write) miss cycles 728system.cpu.itb_walker_cache.demand_miss_latency::total 44091250 # number of demand (read+write) miss cycles 729system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44091250 # number of overall miss cycles 730system.cpu.itb_walker_cache.overall_miss_latency::total 44091250 # number of overall miss cycles 731system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) 732system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) 733system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 734system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 735system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses 736system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses 737system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses 738system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses 739system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354630 # miss rate for ReadReq accesses 740system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354630 # miss rate for ReadReq accesses 741system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354572 # miss rate for demand accesses 742system.cpu.itb_walker_cache.demand_miss_rate::total 0.354572 # miss rate for demand accesses 743system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354572 # miss rate for overall accesses 744system.cpu.itb_walker_cache.overall_miss_rate::total 0.354572 # miss rate for overall accesses 745system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10170.991926 # average ReadReq miss latency 746system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10170.991926 # average ReadReq miss latency 747system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10170.991926 # average overall miss latency 748system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10170.991926 # average overall miss latency 749system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10170.991926 # average overall miss latency 750system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10170.991926 # average overall miss latency 751system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 752system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 753system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 754system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 755system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 756system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 757system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 758system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 759system.cpu.itb_walker_cache.writebacks::writebacks 892 # number of writebacks 760system.cpu.itb_walker_cache.writebacks::total 892 # number of writebacks 761system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4335 # number of ReadReq MSHR misses 762system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4335 # number of ReadReq MSHR misses 763system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4335 # number of demand (read+write) MSHR misses 764system.cpu.itb_walker_cache.demand_mshr_misses::total 4335 # number of demand (read+write) MSHR misses 765system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4335 # number of overall MSHR misses 766system.cpu.itb_walker_cache.overall_mshr_misses::total 4335 # number of overall MSHR misses 767system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35418750 # number of ReadReq MSHR miss cycles 768system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35418750 # number of ReadReq MSHR miss cycles 769system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35418750 # number of demand (read+write) MSHR miss cycles 770system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35418750 # number of demand (read+write) MSHR miss cycles 771system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35418750 # number of overall MSHR miss cycles 772system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35418750 # number of overall MSHR miss cycles 773system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.354630 # mshr miss rate for ReadReq accesses 774system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.354630 # mshr miss rate for ReadReq accesses 775system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.354572 # mshr miss rate for demand accesses 776system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.354572 # mshr miss rate for demand accesses 777system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.354572 # mshr miss rate for overall accesses 778system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.354572 # mshr miss rate for overall accesses 779system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8170.415225 # average ReadReq mshr miss latency 780system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8170.415225 # average ReadReq mshr miss latency 781system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8170.415225 # average overall mshr miss latency 782system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8170.415225 # average overall mshr miss latency 783system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8170.415225 # average overall mshr miss latency 784system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8170.415225 # average overall mshr miss latency 785system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 786system.cpu.dtb_walker_cache.tags.replacements 7524 # number of replacements 787system.cpu.dtb_walker_cache.tags.tagsinuse 5.060120 # Cycle average of tags in use 788system.cpu.dtb_walker_cache.tags.total_refs 13176 # Total number of references to valid blocks. 789system.cpu.dtb_walker_cache.tags.sampled_refs 7539 # Sample count of references to valid blocks. 790system.cpu.dtb_walker_cache.tags.avg_refs 1.747712 # Average number of references to valid blocks. 791system.cpu.dtb_walker_cache.tags.warmup_cycle 5163729602000 # Cycle when the warmup percentage was hit. 792system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.060120 # Average occupied blocks per requestor 793system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316258 # Average percentage of cache occupancy 794system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316258 # Average percentage of cache occupancy 795system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13177 # number of ReadReq hits 796system.cpu.dtb_walker_cache.ReadReq_hits::total 13177 # number of ReadReq hits 797system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13177 # number of demand (read+write) hits 798system.cpu.dtb_walker_cache.demand_hits::total 13177 # number of demand (read+write) hits 799system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13177 # number of overall hits 800system.cpu.dtb_walker_cache.overall_hits::total 13177 # number of overall hits 801system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8707 # number of ReadReq misses 802system.cpu.dtb_walker_cache.ReadReq_misses::total 8707 # number of ReadReq misses 803system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8707 # number of demand (read+write) misses 804system.cpu.dtb_walker_cache.demand_misses::total 8707 # number of demand (read+write) misses 805system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8707 # number of overall misses 806system.cpu.dtb_walker_cache.overall_misses::total 8707 # number of overall misses 807system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 93129000 # number of ReadReq miss cycles 808system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 93129000 # number of ReadReq miss cycles 809system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 93129000 # number of demand (read+write) miss cycles 810system.cpu.dtb_walker_cache.demand_miss_latency::total 93129000 # number of demand (read+write) miss cycles 811system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 93129000 # number of overall miss cycles 812system.cpu.dtb_walker_cache.overall_miss_latency::total 93129000 # number of overall miss cycles 813system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21884 # number of ReadReq accesses(hits+misses) 814system.cpu.dtb_walker_cache.ReadReq_accesses::total 21884 # number of ReadReq accesses(hits+misses) 815system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21884 # number of demand (read+write) accesses 816system.cpu.dtb_walker_cache.demand_accesses::total 21884 # number of demand (read+write) accesses 817system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21884 # number of overall (read+write) accesses 818system.cpu.dtb_walker_cache.overall_accesses::total 21884 # number of overall (read+write) accesses 819system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.397871 # miss rate for ReadReq accesses 820system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.397871 # miss rate for ReadReq accesses 821system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.397871 # miss rate for demand accesses 822system.cpu.dtb_walker_cache.demand_miss_rate::total 0.397871 # miss rate for demand accesses 823system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.397871 # miss rate for overall accesses 824system.cpu.dtb_walker_cache.overall_miss_rate::total 0.397871 # miss rate for overall accesses 825system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10695.876881 # average ReadReq miss latency 826system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10695.876881 # average ReadReq miss latency 827system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10695.876881 # average overall miss latency 828system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10695.876881 # average overall miss latency 829system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10695.876881 # average overall miss latency 830system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10695.876881 # average overall miss latency 831system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 832system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 833system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 834system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 835system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 836system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 837system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 838system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 839system.cpu.dtb_walker_cache.writebacks::writebacks 3011 # number of writebacks 840system.cpu.dtb_walker_cache.writebacks::total 3011 # number of writebacks 841system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8707 # number of ReadReq MSHR misses 842system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8707 # number of ReadReq MSHR misses 843system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8707 # number of demand (read+write) MSHR misses 844system.cpu.dtb_walker_cache.demand_mshr_misses::total 8707 # number of demand (read+write) MSHR misses 845system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8707 # number of overall MSHR misses 846system.cpu.dtb_walker_cache.overall_mshr_misses::total 8707 # number of overall MSHR misses 847system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 75714500 # number of ReadReq MSHR miss cycles 848system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 75714500 # number of ReadReq MSHR miss cycles 849system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 75714500 # number of demand (read+write) MSHR miss cycles 850system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 75714500 # number of demand (read+write) MSHR miss cycles 851system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 75714500 # number of overall MSHR miss cycles 852system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 75714500 # number of overall MSHR miss cycles 853system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.397871 # mshr miss rate for ReadReq accesses 854system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.397871 # mshr miss rate for ReadReq accesses 855system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.397871 # mshr miss rate for demand accesses 856system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.397871 # mshr miss rate for demand accesses 857system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.397871 # mshr miss rate for overall accesses 858system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397871 # mshr miss rate for overall accesses 859system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8695.819456 # average ReadReq mshr miss latency 860system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8695.819456 # average ReadReq mshr miss latency 861system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8695.819456 # average overall mshr miss latency 862system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8695.819456 # average overall mshr miss latency 863system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8695.819456 # average overall mshr miss latency 864system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8695.819456 # average overall mshr miss latency 865system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 866system.cpu.dcache.tags.replacements 1620395 # number of replacements 867system.cpu.dcache.tags.tagsinuse 511.997299 # Cycle average of tags in use 868system.cpu.dcache.tags.total_refs 20022949 # Total number of references to valid blocks. 869system.cpu.dcache.tags.sampled_refs 1620907 # Sample count of references to valid blocks. 870system.cpu.dcache.tags.avg_refs 12.352929 # Average number of references to valid blocks. 871system.cpu.dcache.tags.warmup_cycle 49459250 # Cycle when the warmup percentage was hit. 872system.cpu.dcache.tags.occ_blocks::cpu.data 511.997299 # Average occupied blocks per requestor 873system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy 874system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy 875system.cpu.dcache.ReadReq_hits::cpu.data 11985789 # number of ReadReq hits 876system.cpu.dcache.ReadReq_hits::total 11985789 # number of ReadReq hits 877system.cpu.dcache.WriteReq_hits::cpu.data 8034970 # number of WriteReq hits 878system.cpu.dcache.WriteReq_hits::total 8034970 # number of WriteReq hits 879system.cpu.dcache.demand_hits::cpu.data 20020759 # number of demand (read+write) hits 880system.cpu.dcache.demand_hits::total 20020759 # number of demand (read+write) hits 881system.cpu.dcache.overall_hits::cpu.data 20020759 # number of overall hits 882system.cpu.dcache.overall_hits::total 20020759 # number of overall hits 883system.cpu.dcache.ReadReq_misses::cpu.data 1308577 # number of ReadReq misses 884system.cpu.dcache.ReadReq_misses::total 1308577 # number of ReadReq misses 885system.cpu.dcache.WriteReq_misses::cpu.data 314536 # number of WriteReq misses 886system.cpu.dcache.WriteReq_misses::total 314536 # number of WriteReq misses 887system.cpu.dcache.demand_misses::cpu.data 1623113 # number of demand (read+write) misses 888system.cpu.dcache.demand_misses::total 1623113 # number of demand (read+write) misses 889system.cpu.dcache.overall_misses::cpu.data 1623113 # number of overall misses 890system.cpu.dcache.overall_misses::total 1623113 # number of overall misses 891system.cpu.dcache.ReadReq_miss_latency::cpu.data 18867836541 # number of ReadReq miss cycles 892system.cpu.dcache.ReadReq_miss_latency::total 18867836541 # number of ReadReq miss cycles 893system.cpu.dcache.WriteReq_miss_latency::cpu.data 10715308194 # number of WriteReq miss cycles 894system.cpu.dcache.WriteReq_miss_latency::total 10715308194 # number of WriteReq miss cycles 895system.cpu.dcache.demand_miss_latency::cpu.data 29583144735 # number of demand (read+write) miss cycles 896system.cpu.dcache.demand_miss_latency::total 29583144735 # number of demand (read+write) miss cycles 897system.cpu.dcache.overall_miss_latency::cpu.data 29583144735 # number of overall miss cycles 898system.cpu.dcache.overall_miss_latency::total 29583144735 # number of overall miss cycles 899system.cpu.dcache.ReadReq_accesses::cpu.data 13294366 # number of ReadReq accesses(hits+misses) 900system.cpu.dcache.ReadReq_accesses::total 13294366 # number of ReadReq accesses(hits+misses) 901system.cpu.dcache.WriteReq_accesses::cpu.data 8349506 # number of WriteReq accesses(hits+misses) 902system.cpu.dcache.WriteReq_accesses::total 8349506 # number of WriteReq accesses(hits+misses) 903system.cpu.dcache.demand_accesses::cpu.data 21643872 # number of demand (read+write) accesses 904system.cpu.dcache.demand_accesses::total 21643872 # number of demand (read+write) accesses 905system.cpu.dcache.overall_accesses::cpu.data 21643872 # number of overall (read+write) accesses 906system.cpu.dcache.overall_accesses::total 21643872 # number of overall (read+write) accesses 907system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098431 # miss rate for ReadReq accesses 908system.cpu.dcache.ReadReq_miss_rate::total 0.098431 # miss rate for ReadReq accesses 909system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037671 # miss rate for WriteReq accesses 910system.cpu.dcache.WriteReq_miss_rate::total 0.037671 # miss rate for WriteReq accesses 911system.cpu.dcache.demand_miss_rate::cpu.data 0.074992 # miss rate for demand accesses 912system.cpu.dcache.demand_miss_rate::total 0.074992 # miss rate for demand accesses 913system.cpu.dcache.overall_miss_rate::cpu.data 0.074992 # miss rate for overall accesses 914system.cpu.dcache.overall_miss_rate::total 0.074992 # miss rate for overall accesses 915system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14418.590989 # average ReadReq miss latency 916system.cpu.dcache.ReadReq_avg_miss_latency::total 14418.590989 # average ReadReq miss latency 917system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34067.032689 # average WriteReq miss latency 918system.cpu.dcache.WriteReq_avg_miss_latency::total 34067.032689 # average WriteReq miss latency 919system.cpu.dcache.demand_avg_miss_latency::cpu.data 18226.176942 # average overall miss latency 920system.cpu.dcache.demand_avg_miss_latency::total 18226.176942 # average overall miss latency 921system.cpu.dcache.overall_avg_miss_latency::cpu.data 18226.176942 # average overall miss latency 922system.cpu.dcache.overall_avg_miss_latency::total 18226.176942 # average overall miss latency 923system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 924system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 925system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 926system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 927system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 928system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 929system.cpu.dcache.fast_writes 0 # number of fast writes performed 930system.cpu.dcache.cache_copies 0 # number of cache copies performed 931system.cpu.dcache.writebacks::writebacks 1537197 # number of writebacks 932system.cpu.dcache.writebacks::total 1537197 # number of writebacks 933system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308577 # number of ReadReq MSHR misses 934system.cpu.dcache.ReadReq_mshr_misses::total 1308577 # number of ReadReq MSHR misses 935system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314536 # number of WriteReq MSHR misses 936system.cpu.dcache.WriteReq_mshr_misses::total 314536 # number of WriteReq MSHR misses 937system.cpu.dcache.demand_mshr_misses::cpu.data 1623113 # number of demand (read+write) MSHR misses 938system.cpu.dcache.demand_mshr_misses::total 1623113 # number of demand (read+write) MSHR misses 939system.cpu.dcache.overall_mshr_misses::cpu.data 1623113 # number of overall MSHR misses 940system.cpu.dcache.overall_mshr_misses::total 1623113 # number of overall MSHR misses 941system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16237300459 # number of ReadReq MSHR miss cycles 942system.cpu.dcache.ReadReq_mshr_miss_latency::total 16237300459 # number of ReadReq MSHR miss cycles 943system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10031005806 # number of WriteReq MSHR miss cycles 944system.cpu.dcache.WriteReq_mshr_miss_latency::total 10031005806 # number of WriteReq MSHR miss cycles 945system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26268306265 # number of demand (read+write) MSHR miss cycles 946system.cpu.dcache.demand_mshr_miss_latency::total 26268306265 # number of demand (read+write) MSHR miss cycles 947system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26268306265 # number of overall MSHR miss cycles 948system.cpu.dcache.overall_mshr_miss_latency::total 26268306265 # number of overall MSHR miss cycles 949system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94200368500 # number of ReadReq MSHR uncacheable cycles 950system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94200368500 # number of ReadReq MSHR uncacheable cycles 951system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2523287500 # number of WriteReq MSHR uncacheable cycles 952system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2523287500 # number of WriteReq MSHR uncacheable cycles 953system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96723656000 # number of overall MSHR uncacheable cycles 954system.cpu.dcache.overall_mshr_uncacheable_latency::total 96723656000 # number of overall MSHR uncacheable cycles 955system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098431 # mshr miss rate for ReadReq accesses 956system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098431 # mshr miss rate for ReadReq accesses 957system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037671 # mshr miss rate for WriteReq accesses 958system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037671 # mshr miss rate for WriteReq accesses 959system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074992 # mshr miss rate for demand accesses 960system.cpu.dcache.demand_mshr_miss_rate::total 0.074992 # mshr miss rate for demand accesses 961system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074992 # mshr miss rate for overall accesses 962system.cpu.dcache.overall_mshr_miss_rate::total 0.074992 # mshr miss rate for overall accesses 963system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12408.364551 # average ReadReq mshr miss latency 964system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12408.364551 # average ReadReq mshr miss latency 965system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31891.439473 # average WriteReq mshr miss latency 966system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31891.439473 # average WriteReq mshr miss latency 967system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16183.904796 # average overall mshr miss latency 968system.cpu.dcache.demand_avg_mshr_miss_latency::total 16183.904796 # average overall mshr miss latency 969system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16183.904796 # average overall mshr miss latency 970system.cpu.dcache.overall_avg_mshr_miss_latency::total 16183.904796 # average overall mshr miss latency 971system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 972system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 973system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 974system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 975system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 976system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 977system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 978system.cpu.toL2Bus.throughput 49187749 # Throughput (bytes/s) 979system.cpu.toL2Bus.trans_dist::ReadReq 2695979 # Transaction distribution 980system.cpu.toL2Bus.trans_dist::ReadResp 2695445 # Transaction distribution 981system.cpu.toL2Bus.trans_dist::WriteReq 13711 # Transaction distribution 982system.cpu.toL2Bus.trans_dist::WriteResp 13711 # Transaction distribution 983system.cpu.toL2Bus.trans_dist::Writeback 1541100 # Transaction distribution 984system.cpu.toL2Bus.trans_dist::UpgradeReq 2190 # Transaction distribution 985system.cpu.toL2Bus.trans_dist::UpgradeResp 2190 # Transaction distribution 986system.cpu.toL2Bus.trans_dist::ReadExReq 359066 # Transaction distribution 987system.cpu.toL2Bus.trans_dist::ReadExResp 312361 # Transaction distribution 988system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584265 # Packet count per connected master and slave (bytes) 989system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5972620 # Packet count per connected master and slave (bytes) 990system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8122 # Packet count per connected master and slave (bytes) 991system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18187 # Packet count per connected master and slave (bytes) 992system.cpu.toL2Bus.pkt_count::total 7583194 # Packet count per connected master and slave (bytes) 993system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50696064 # Cumulative packet size per connected master and slave (bytes) 994system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203753837 # Cumulative packet size per connected master and slave (bytes) 995system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 242368 # Cumulative packet size per connected master and slave (bytes) 996system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 606720 # Cumulative packet size per connected master and slave (bytes) 997system.cpu.toL2Bus.tot_pkt_size::total 255298989 # Cumulative packet size per connected master and slave (bytes) 998system.cpu.toL2Bus.data_through_bus 255278509 # Total data (bytes) 999system.cpu.toL2Bus.snoop_data_through_bus 309568 # Total snoop data (bytes) 1000system.cpu.toL2Bus.reqLayer0.occupancy 3830199000 # Layer occupancy (ticks) 1001system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1002system.cpu.toL2Bus.snoopLayer0.occupancy 480000 # Layer occupancy (ticks) 1003system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1004system.cpu.toL2Bus.respLayer0.occupancy 1191344009 # Layer occupancy (ticks) 1005system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1006system.cpu.toL2Bus.respLayer1.occupancy 3055023235 # Layer occupancy (ticks) 1007system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1008system.cpu.toL2Bus.respLayer2.occupancy 6503750 # Layer occupancy (ticks) 1009system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1010system.cpu.toL2Bus.respLayer3.occupancy 13060750 # Layer occupancy (ticks) 1011system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1012system.cpu.l2cache.tags.replacements 86901 # number of replacements 1013system.cpu.l2cache.tags.tagsinuse 64732.450740 # Cycle average of tags in use 1014system.cpu.l2cache.tags.total_refs 3488744 # Total number of references to valid blocks. 1015system.cpu.l2cache.tags.sampled_refs 151586 # Sample count of references to valid blocks. 1016system.cpu.l2cache.tags.avg_refs 23.014949 # Average number of references to valid blocks. 1017system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1018system.cpu.l2cache.tags.occ_blocks::writebacks 50263.095698 # Average occupied blocks per requestor 1019system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.027390 # Average occupied blocks per requestor 1020system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141416 # Average occupied blocks per requestor 1021system.cpu.l2cache.tags.occ_blocks::cpu.inst 3383.648694 # Average occupied blocks per requestor 1022system.cpu.l2cache.tags.occ_blocks::cpu.data 11085.537541 # Average occupied blocks per requestor 1023system.cpu.l2cache.tags.occ_percent::writebacks 0.766954 # Average percentage of cache occupancy 1024system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 1025system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 1026system.cpu.l2cache.tags.occ_percent::cpu.inst 0.051630 # Average percentage of cache occupancy 1027system.cpu.l2cache.tags.occ_percent::cpu.data 0.169152 # Average percentage of cache occupancy 1028system.cpu.l2cache.tags.occ_percent::total 0.987739 # Average percentage of cache occupancy 1029system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6468 # number of ReadReq hits 1030system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2890 # number of ReadReq hits 1031system.cpu.l2cache.ReadReq_hits::cpu.inst 779213 # number of ReadReq hits 1032system.cpu.l2cache.ReadReq_hits::cpu.data 1279490 # number of ReadReq hits 1033system.cpu.l2cache.ReadReq_hits::total 2068061 # number of ReadReq hits 1034system.cpu.l2cache.Writeback_hits::writebacks 1541100 # number of Writeback hits 1035system.cpu.l2cache.Writeback_hits::total 1541100 # number of Writeback hits 1036system.cpu.l2cache.UpgradeReq_hits::cpu.data 295 # number of UpgradeReq hits 1037system.cpu.l2cache.UpgradeReq_hits::total 295 # number of UpgradeReq hits 1038system.cpu.l2cache.ReadExReq_hits::cpu.data 199238 # number of ReadExReq hits 1039system.cpu.l2cache.ReadExReq_hits::total 199238 # number of ReadExReq hits 1040system.cpu.l2cache.demand_hits::cpu.dtb.walker 6468 # number of demand (read+write) hits 1041system.cpu.l2cache.demand_hits::cpu.itb.walker 2890 # number of demand (read+write) hits 1042system.cpu.l2cache.demand_hits::cpu.inst 779213 # number of demand (read+write) hits 1043system.cpu.l2cache.demand_hits::cpu.data 1478728 # number of demand (read+write) hits 1044system.cpu.l2cache.demand_hits::total 2267299 # number of demand (read+write) hits 1045system.cpu.l2cache.overall_hits::cpu.dtb.walker 6468 # number of overall hits 1046system.cpu.l2cache.overall_hits::cpu.itb.walker 2890 # number of overall hits 1047system.cpu.l2cache.overall_hits::cpu.inst 779213 # number of overall hits 1048system.cpu.l2cache.overall_hits::cpu.data 1478728 # number of overall hits 1049system.cpu.l2cache.overall_hits::total 2267299 # number of overall hits 1050system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 1051system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 1052system.cpu.l2cache.ReadReq_misses::cpu.inst 12913 # number of ReadReq misses 1053system.cpu.l2cache.ReadReq_misses::cpu.data 28265 # number of ReadReq misses 1054system.cpu.l2cache.ReadReq_misses::total 41184 # number of ReadReq misses 1055system.cpu.l2cache.UpgradeReq_misses::cpu.data 1412 # number of UpgradeReq misses 1056system.cpu.l2cache.UpgradeReq_misses::total 1412 # number of UpgradeReq misses 1057system.cpu.l2cache.ReadExReq_misses::cpu.data 113104 # number of ReadExReq misses 1058system.cpu.l2cache.ReadExReq_misses::total 113104 # number of ReadExReq misses 1059system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 1060system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 1061system.cpu.l2cache.demand_misses::cpu.inst 12913 # number of demand (read+write) misses 1062system.cpu.l2cache.demand_misses::cpu.data 141369 # number of demand (read+write) misses 1063system.cpu.l2cache.demand_misses::total 154288 # number of demand (read+write) misses 1064system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 1065system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 1066system.cpu.l2cache.overall_misses::cpu.inst 12913 # number of overall misses 1067system.cpu.l2cache.overall_misses::cpu.data 141369 # number of overall misses 1068system.cpu.l2cache.overall_misses::total 154288 # number of overall misses 1069system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles 1070system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 743250 # number of ReadReq miss cycles 1071system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1023689491 # number of ReadReq miss cycles 1072system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2132999959 # number of ReadReq miss cycles 1073system.cpu.l2cache.ReadReq_miss_latency::total 3157521950 # number of ReadReq miss cycles 1074system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16111372 # number of UpgradeReq miss cycles 1075system.cpu.l2cache.UpgradeReq_miss_latency::total 16111372 # number of UpgradeReq miss cycles 1076system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7687296700 # number of ReadExReq miss cycles 1077system.cpu.l2cache.ReadExReq_miss_latency::total 7687296700 # number of ReadExReq miss cycles 1078system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles 1079system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 743250 # number of demand (read+write) miss cycles 1080system.cpu.l2cache.demand_miss_latency::cpu.inst 1023689491 # number of demand (read+write) miss cycles 1081system.cpu.l2cache.demand_miss_latency::cpu.data 9820296659 # number of demand (read+write) miss cycles 1082system.cpu.l2cache.demand_miss_latency::total 10844818650 # number of demand (read+write) miss cycles 1083system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles 1084system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 743250 # number of overall miss cycles 1085system.cpu.l2cache.overall_miss_latency::cpu.inst 1023689491 # number of overall miss cycles 1086system.cpu.l2cache.overall_miss_latency::cpu.data 9820296659 # number of overall miss cycles 1087system.cpu.l2cache.overall_miss_latency::total 10844818650 # number of overall miss cycles 1088system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6469 # number of ReadReq accesses(hits+misses) 1089system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2895 # number of ReadReq accesses(hits+misses) 1090system.cpu.l2cache.ReadReq_accesses::cpu.inst 792126 # number of ReadReq accesses(hits+misses) 1091system.cpu.l2cache.ReadReq_accesses::cpu.data 1307755 # number of ReadReq accesses(hits+misses) 1092system.cpu.l2cache.ReadReq_accesses::total 2109245 # number of ReadReq accesses(hits+misses) 1093system.cpu.l2cache.Writeback_accesses::writebacks 1541100 # number of Writeback accesses(hits+misses) 1094system.cpu.l2cache.Writeback_accesses::total 1541100 # number of Writeback accesses(hits+misses) 1095system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1707 # number of UpgradeReq accesses(hits+misses) 1096system.cpu.l2cache.UpgradeReq_accesses::total 1707 # number of UpgradeReq accesses(hits+misses) 1097system.cpu.l2cache.ReadExReq_accesses::cpu.data 312342 # number of ReadExReq accesses(hits+misses) 1098system.cpu.l2cache.ReadExReq_accesses::total 312342 # number of ReadExReq accesses(hits+misses) 1099system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6469 # number of demand (read+write) accesses 1100system.cpu.l2cache.demand_accesses::cpu.itb.walker 2895 # number of demand (read+write) accesses 1101system.cpu.l2cache.demand_accesses::cpu.inst 792126 # number of demand (read+write) accesses 1102system.cpu.l2cache.demand_accesses::cpu.data 1620097 # number of demand (read+write) accesses 1103system.cpu.l2cache.demand_accesses::total 2421587 # number of demand (read+write) accesses 1104system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6469 # number of overall (read+write) accesses 1105system.cpu.l2cache.overall_accesses::cpu.itb.walker 2895 # number of overall (read+write) accesses 1106system.cpu.l2cache.overall_accesses::cpu.inst 792126 # number of overall (read+write) accesses 1107system.cpu.l2cache.overall_accesses::cpu.data 1620097 # number of overall (read+write) accesses 1108system.cpu.l2cache.overall_accesses::total 2421587 # number of overall (read+write) accesses 1109system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000155 # miss rate for ReadReq accesses 1110system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001727 # miss rate for ReadReq accesses 1111system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016302 # miss rate for ReadReq accesses 1112system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021613 # miss rate for ReadReq accesses 1113system.cpu.l2cache.ReadReq_miss_rate::total 0.019525 # miss rate for ReadReq accesses 1114system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.827182 # miss rate for UpgradeReq accesses 1115system.cpu.l2cache.UpgradeReq_miss_rate::total 0.827182 # miss rate for UpgradeReq accesses 1116system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362116 # miss rate for ReadExReq accesses 1117system.cpu.l2cache.ReadExReq_miss_rate::total 0.362116 # miss rate for ReadExReq accesses 1118system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000155 # miss rate for demand accesses 1119system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001727 # miss rate for demand accesses 1120system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016302 # miss rate for demand accesses 1121system.cpu.l2cache.demand_miss_rate::cpu.data 0.087260 # miss rate for demand accesses 1122system.cpu.l2cache.demand_miss_rate::total 0.063714 # miss rate for demand accesses 1123system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000155 # miss rate for overall accesses 1124system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001727 # miss rate for overall accesses 1125system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016302 # miss rate for overall accesses 1126system.cpu.l2cache.overall_miss_rate::cpu.data 0.087260 # miss rate for overall accesses 1127system.cpu.l2cache.overall_miss_rate::total 0.063714 # miss rate for overall accesses 1128system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency 1129system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 148650 # average ReadReq miss latency 1130system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79275.884070 # average ReadReq miss latency 1131system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75464.353759 # average ReadReq miss latency 1132system.cpu.l2cache.ReadReq_avg_miss_latency::total 76668.656517 # average ReadReq miss latency 1133system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11410.320113 # average UpgradeReq miss latency 1134system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11410.320113 # average UpgradeReq miss latency 1135system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67966.620986 # average ReadExReq miss latency 1136system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67966.620986 # average ReadExReq miss latency 1137system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency 1138system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 148650 # average overall miss latency 1139system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79275.884070 # average overall miss latency 1140system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69465.700818 # average overall miss latency 1141system.cpu.l2cache.demand_avg_miss_latency::total 70289.449925 # average overall miss latency 1142system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency 1143system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 148650 # average overall miss latency 1144system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79275.884070 # average overall miss latency 1145system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69465.700818 # average overall miss latency 1146system.cpu.l2cache.overall_avg_miss_latency::total 70289.449925 # average overall miss latency 1147system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1148system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1149system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1150system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1151system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1152system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1153system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1154system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1155system.cpu.l2cache.writebacks::writebacks 80175 # number of writebacks 1156system.cpu.l2cache.writebacks::total 80175 # number of writebacks 1157system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses 1158system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 1159system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12913 # number of ReadReq MSHR misses 1160system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28265 # number of ReadReq MSHR misses 1161system.cpu.l2cache.ReadReq_mshr_misses::total 41184 # number of ReadReq MSHR misses 1162system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1412 # number of UpgradeReq MSHR misses 1163system.cpu.l2cache.UpgradeReq_mshr_misses::total 1412 # number of UpgradeReq MSHR misses 1164system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113104 # number of ReadExReq MSHR misses 1165system.cpu.l2cache.ReadExReq_mshr_misses::total 113104 # number of ReadExReq MSHR misses 1166system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses 1167system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 1168system.cpu.l2cache.demand_mshr_misses::cpu.inst 12913 # number of demand (read+write) MSHR misses 1169system.cpu.l2cache.demand_mshr_misses::cpu.data 141369 # number of demand (read+write) MSHR misses 1170system.cpu.l2cache.demand_mshr_misses::total 154288 # number of demand (read+write) MSHR misses 1171system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses 1172system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 1173system.cpu.l2cache.overall_mshr_misses::cpu.inst 12913 # number of overall MSHR misses 1174system.cpu.l2cache.overall_mshr_misses::cpu.data 141369 # number of overall MSHR misses 1175system.cpu.l2cache.overall_mshr_misses::total 154288 # number of overall MSHR misses 1176system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles 1177system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 679250 # number of ReadReq MSHR miss cycles 1178system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 860763509 # number of ReadReq MSHR miss cycles 1179system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1776510041 # number of ReadReq MSHR miss cycles 1180system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2638029050 # number of ReadReq MSHR miss cycles 1181system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15111394 # number of UpgradeReq MSHR miss cycles 1182system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15111394 # number of UpgradeReq MSHR miss cycles 1183system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6272468800 # number of ReadExReq MSHR miss cycles 1184system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6272468800 # number of ReadExReq MSHR miss cycles 1185system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles 1186system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 679250 # number of demand (read+write) MSHR miss cycles 1187system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 860763509 # number of demand (read+write) MSHR miss cycles 1188system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8048978841 # number of demand (read+write) MSHR miss cycles 1189system.cpu.l2cache.demand_mshr_miss_latency::total 8910497850 # number of demand (read+write) MSHR miss cycles 1190system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles 1191system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 679250 # number of overall MSHR miss cycles 1192system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 860763509 # number of overall MSHR miss cycles 1193system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8048978841 # number of overall MSHR miss cycles 1194system.cpu.l2cache.overall_mshr_miss_latency::total 8910497850 # number of overall MSHR miss cycles 1195system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86642397000 # number of ReadReq MSHR uncacheable cycles 1196system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86642397000 # number of ReadReq MSHR uncacheable cycles 1197system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2357413500 # number of WriteReq MSHR uncacheable cycles 1198system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2357413500 # number of WriteReq MSHR uncacheable cycles 1199system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88999810500 # number of overall MSHR uncacheable cycles 1200system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88999810500 # number of overall MSHR uncacheable cycles 1201system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for ReadReq accesses 1202system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001727 # mshr miss rate for ReadReq accesses 1203system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for ReadReq accesses 1204system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021613 # mshr miss rate for ReadReq accesses 1205system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019525 # mshr miss rate for ReadReq accesses 1206system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.827182 # mshr miss rate for UpgradeReq accesses 1207system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.827182 # mshr miss rate for UpgradeReq accesses 1208system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362116 # mshr miss rate for ReadExReq accesses 1209system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362116 # mshr miss rate for ReadExReq accesses 1210system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for demand accesses 1211system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001727 # mshr miss rate for demand accesses 1212system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for demand accesses 1213system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087260 # mshr miss rate for demand accesses 1214system.cpu.l2cache.demand_mshr_miss_rate::total 0.063714 # mshr miss rate for demand accesses 1215system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for overall accesses 1216system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001727 # mshr miss rate for overall accesses 1217system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for overall accesses 1218system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087260 # mshr miss rate for overall accesses 1219system.cpu.l2cache.overall_mshr_miss_rate::total 0.063714 # mshr miss rate for overall accesses 1220system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency 1221system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 135850 # average ReadReq mshr miss latency 1222system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66658.677999 # average ReadReq mshr miss latency 1223system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62851.938475 # average ReadReq mshr miss latency 1224system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64054.706925 # average ReadReq mshr miss latency 1225system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10702.120397 # average UpgradeReq mshr miss latency 1226system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10702.120397 # average UpgradeReq mshr miss latency 1227system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55457.532890 # average ReadExReq mshr miss latency 1228system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55457.532890 # average ReadExReq mshr miss latency 1229system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency 1230system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 135850 # average overall mshr miss latency 1231system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66658.677999 # average overall mshr miss latency 1232system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56935.953717 # average overall mshr miss latency 1233system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57752.371215 # average overall mshr miss latency 1234system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency 1235system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 135850 # average overall mshr miss latency 1236system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66658.677999 # average overall mshr miss latency 1237system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56935.953717 # average overall mshr miss latency 1238system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57752.371215 # average overall mshr miss latency 1239system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1240system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1241system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1242system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1243system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1244system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1245system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1246 1247---------- End Simulation Statistics ---------- 1248