stats.txt revision 9283:490958b032d6
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.196023 # Number of seconds simulated 4sim_ticks 5196022575000 # Number of ticks simulated 5final_tick 5196022575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1315892 # Simulator instruction rate (inst/s) 8host_op_rate 2536713 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53344387183 # Simulator tick rate (ticks/s) 10host_mem_usage 354072 # Number of bytes of host memory used 11host_seconds 97.41 # Real time elapsed on the host 12sim_insts 128174734 # Number of instructions simulated 13sim_ops 247089109 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2880320 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.inst 824192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8956288 # Number of bytes read from this memory 18system.physmem.bytes_read::total 12661120 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 824192 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 824192 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 8085888 # Number of bytes written to this memory 22system.physmem.bytes_written::total 8085888 # Number of bytes written to this memory 23system.physmem.num_reads::pc.south_bridge.ide 45005 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.inst 12878 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 139942 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 197830 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 126342 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 126342 # Number of write requests responded to by this memory 30system.physmem.bw_read::pc.south_bridge.ide 554332 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.inst 158620 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.data 1723682 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 2436695 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 158620 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 158620 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 1556169 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 1556169 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 1556169 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::pc.south_bridge.ide 554332 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 158620 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 1723682 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::total 3992863 # Total bandwidth to/from this memory (bytes/s) 45system.cpu.l2cache.replacements 86330 # number of replacements 46system.cpu.l2cache.tagsinuse 64759.737076 # Cycle average of tags in use 47system.cpu.l2cache.total_refs 3491284 # Total number of references to valid blocks. 48system.cpu.l2cache.sampled_refs 151054 # Sample count of references to valid blocks. 49system.cpu.l2cache.avg_refs 23.112821 # Average number of references to valid blocks. 50system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 51system.cpu.l2cache.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor 52system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor 53system.cpu.l2cache.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor 54system.cpu.l2cache.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor 55system.cpu.l2cache.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy 56system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 57system.cpu.l2cache.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy 58system.cpu.l2cache.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy 59system.cpu.l2cache.occ_percent::total 0.988155 # Average percentage of cache occupancy 60system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits 61system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits 62system.cpu.l2cache.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits 63system.cpu.l2cache.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits 64system.cpu.l2cache.ReadReq_hits::total 2068208 # number of ReadReq hits 65system.cpu.l2cache.Writeback_hits::writebacks 1543462 # number of Writeback hits 66system.cpu.l2cache.Writeback_hits::total 1543462 # number of Writeback hits 67system.cpu.l2cache.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits 68system.cpu.l2cache.UpgradeReq_hits::total 302 # number of UpgradeReq hits 69system.cpu.l2cache.ReadExReq_hits::cpu.data 200678 # number of ReadExReq hits 70system.cpu.l2cache.ReadExReq_hits::total 200678 # number of ReadExReq hits 71system.cpu.l2cache.demand_hits::cpu.dtb.walker 6719 # number of demand (read+write) hits 72system.cpu.l2cache.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits 73system.cpu.l2cache.demand_hits::cpu.inst 778172 # number of demand (read+write) hits 74system.cpu.l2cache.demand_hits::cpu.data 1481001 # number of demand (read+write) hits 75system.cpu.l2cache.demand_hits::total 2268886 # number of demand (read+write) hits 76system.cpu.l2cache.overall_hits::cpu.dtb.walker 6719 # number of overall hits 77system.cpu.l2cache.overall_hits::cpu.itb.walker 2994 # number of overall hits 78system.cpu.l2cache.overall_hits::cpu.inst 778172 # number of overall hits 79system.cpu.l2cache.overall_hits::cpu.data 1481001 # number of overall hits 80system.cpu.l2cache.overall_hits::total 2268886 # number of overall hits 81system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 82system.cpu.l2cache.ReadReq_misses::cpu.inst 12879 # number of ReadReq misses 83system.cpu.l2cache.ReadReq_misses::cpu.data 28353 # number of ReadReq misses 84system.cpu.l2cache.ReadReq_misses::total 41237 # number of ReadReq misses 85system.cpu.l2cache.UpgradeReq_misses::cpu.data 1338 # number of UpgradeReq misses 86system.cpu.l2cache.UpgradeReq_misses::total 1338 # number of UpgradeReq misses 87system.cpu.l2cache.ReadExReq_misses::cpu.data 112514 # number of ReadExReq misses 88system.cpu.l2cache.ReadExReq_misses::total 112514 # number of ReadExReq misses 89system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 90system.cpu.l2cache.demand_misses::cpu.inst 12879 # number of demand (read+write) misses 91system.cpu.l2cache.demand_misses::cpu.data 140867 # number of demand (read+write) misses 92system.cpu.l2cache.demand_misses::total 153751 # number of demand (read+write) misses 93system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 94system.cpu.l2cache.overall_misses::cpu.inst 12879 # number of overall misses 95system.cpu.l2cache.overall_misses::cpu.data 140867 # number of overall misses 96system.cpu.l2cache.overall_misses::total 153751 # number of overall misses 97system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles 98system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 670083000 # number of ReadReq miss cycles 99system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1488776500 # number of ReadReq miss cycles 100system.cpu.l2cache.ReadReq_miss_latency::total 2159119500 # number of ReadReq miss cycles 101system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 33785000 # number of UpgradeReq miss cycles 102system.cpu.l2cache.UpgradeReq_miss_latency::total 33785000 # number of UpgradeReq miss cycles 103system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5852520000 # number of ReadExReq miss cycles 104system.cpu.l2cache.ReadExReq_miss_latency::total 5852520000 # number of ReadExReq miss cycles 105system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles 106system.cpu.l2cache.demand_miss_latency::cpu.inst 670083000 # number of demand (read+write) miss cycles 107system.cpu.l2cache.demand_miss_latency::cpu.data 7341296500 # number of demand (read+write) miss cycles 108system.cpu.l2cache.demand_miss_latency::total 8011639500 # number of demand (read+write) miss cycles 109system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles 110system.cpu.l2cache.overall_miss_latency::cpu.inst 670083000 # number of overall miss cycles 111system.cpu.l2cache.overall_miss_latency::cpu.data 7341296500 # number of overall miss cycles 112system.cpu.l2cache.overall_miss_latency::total 8011639500 # number of overall miss cycles 113system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6719 # number of ReadReq accesses(hits+misses) 114system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2999 # number of ReadReq accesses(hits+misses) 115system.cpu.l2cache.ReadReq_accesses::cpu.inst 791051 # number of ReadReq accesses(hits+misses) 116system.cpu.l2cache.ReadReq_accesses::cpu.data 1308676 # number of ReadReq accesses(hits+misses) 117system.cpu.l2cache.ReadReq_accesses::total 2109445 # number of ReadReq accesses(hits+misses) 118system.cpu.l2cache.Writeback_accesses::writebacks 1543462 # number of Writeback accesses(hits+misses) 119system.cpu.l2cache.Writeback_accesses::total 1543462 # number of Writeback accesses(hits+misses) 120system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1640 # number of UpgradeReq accesses(hits+misses) 121system.cpu.l2cache.UpgradeReq_accesses::total 1640 # number of UpgradeReq accesses(hits+misses) 122system.cpu.l2cache.ReadExReq_accesses::cpu.data 313192 # number of ReadExReq accesses(hits+misses) 123system.cpu.l2cache.ReadExReq_accesses::total 313192 # number of ReadExReq accesses(hits+misses) 124system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6719 # number of demand (read+write) accesses 125system.cpu.l2cache.demand_accesses::cpu.itb.walker 2999 # number of demand (read+write) accesses 126system.cpu.l2cache.demand_accesses::cpu.inst 791051 # number of demand (read+write) accesses 127system.cpu.l2cache.demand_accesses::cpu.data 1621868 # number of demand (read+write) accesses 128system.cpu.l2cache.demand_accesses::total 2422637 # number of demand (read+write) accesses 129system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6719 # number of overall (read+write) accesses 130system.cpu.l2cache.overall_accesses::cpu.itb.walker 2999 # number of overall (read+write) accesses 131system.cpu.l2cache.overall_accesses::cpu.inst 791051 # number of overall (read+write) accesses 132system.cpu.l2cache.overall_accesses::cpu.data 1621868 # number of overall (read+write) accesses 133system.cpu.l2cache.overall_accesses::total 2422637 # number of overall (read+write) accesses 134system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses 135system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016281 # miss rate for ReadReq accesses 136system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021665 # miss rate for ReadReq accesses 137system.cpu.l2cache.ReadReq_miss_rate::total 0.019549 # miss rate for ReadReq accesses 138system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.815854 # miss rate for UpgradeReq accesses 139system.cpu.l2cache.UpgradeReq_miss_rate::total 0.815854 # miss rate for UpgradeReq accesses 140system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359249 # miss rate for ReadExReq accesses 141system.cpu.l2cache.ReadExReq_miss_rate::total 0.359249 # miss rate for ReadExReq accesses 142system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses 143system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016281 # miss rate for demand accesses 144system.cpu.l2cache.demand_miss_rate::cpu.data 0.086855 # miss rate for demand accesses 145system.cpu.l2cache.demand_miss_rate::total 0.063464 # miss rate for demand accesses 146system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses 147system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016281 # miss rate for overall accesses 148system.cpu.l2cache.overall_miss_rate::cpu.data 0.086855 # miss rate for overall accesses 149system.cpu.l2cache.overall_miss_rate::total 0.063464 # miss rate for overall accesses 150system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency 151system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.117167 # average ReadReq miss latency 152system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52508.605791 # average ReadReq miss latency 153system.cpu.l2cache.ReadReq_avg_miss_latency::total 52358.791862 # average ReadReq miss latency 154system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 25250.373692 # average UpgradeReq miss latency 155system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 25250.373692 # average UpgradeReq miss latency 156system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52015.926907 # average ReadExReq miss latency 157system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52015.926907 # average ReadExReq miss latency 158system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 159system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency 160system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency 161system.cpu.l2cache.demand_avg_miss_latency::total 52107.885477 # average overall miss latency 162system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 163system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency 164system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency 165system.cpu.l2cache.overall_avg_miss_latency::total 52107.885477 # average overall miss latency 166system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 167system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 168system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 169system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 170system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 171system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172system.cpu.l2cache.fast_writes 0 # number of fast writes performed 173system.cpu.l2cache.cache_copies 0 # number of cache copies performed 174system.cpu.l2cache.writebacks::writebacks 79675 # number of writebacks 175system.cpu.l2cache.writebacks::total 79675 # number of writebacks 176system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 177system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12879 # number of ReadReq MSHR misses 178system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28353 # number of ReadReq MSHR misses 179system.cpu.l2cache.ReadReq_mshr_misses::total 41237 # number of ReadReq MSHR misses 180system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1338 # number of UpgradeReq MSHR misses 181system.cpu.l2cache.UpgradeReq_mshr_misses::total 1338 # number of UpgradeReq MSHR misses 182system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112514 # number of ReadExReq MSHR misses 183system.cpu.l2cache.ReadExReq_mshr_misses::total 112514 # number of ReadExReq MSHR misses 184system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 185system.cpu.l2cache.demand_mshr_misses::cpu.inst 12879 # number of demand (read+write) MSHR misses 186system.cpu.l2cache.demand_mshr_misses::cpu.data 140867 # number of demand (read+write) MSHR misses 187system.cpu.l2cache.demand_mshr_misses::total 153751 # number of demand (read+write) MSHR misses 188system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 189system.cpu.l2cache.overall_mshr_misses::cpu.inst 12879 # number of overall MSHR misses 190system.cpu.l2cache.overall_mshr_misses::cpu.data 140867 # number of overall MSHR misses 191system.cpu.l2cache.overall_mshr_misses::total 153751 # number of overall MSHR misses 192system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles 193system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 515526000 # number of ReadReq MSHR miss cycles 194system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1148536000 # number of ReadReq MSHR miss cycles 195system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1664262000 # number of ReadReq MSHR miss cycles 196system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 53936000 # number of UpgradeReq MSHR miss cycles 197system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 53936000 # number of UpgradeReq MSHR miss cycles 198system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4502349000 # number of ReadExReq MSHR miss cycles 199system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4502349000 # number of ReadExReq MSHR miss cycles 200system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles 201system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 515526000 # number of demand (read+write) MSHR miss cycles 202system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5650885000 # number of demand (read+write) MSHR miss cycles 203system.cpu.l2cache.demand_mshr_miss_latency::total 6166611000 # number of demand (read+write) MSHR miss cycles 204system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles 205system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 515526000 # number of overall MSHR miss cycles 206system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5650885000 # number of overall MSHR miss cycles 207system.cpu.l2cache.overall_mshr_miss_latency::total 6166611000 # number of overall MSHR miss cycles 208system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles 209system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles 210system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2306155000 # number of WriteReq MSHR uncacheable cycles 211system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2306155000 # number of WriteReq MSHR uncacheable cycles 212system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88423605000 # number of overall MSHR uncacheable cycles 213system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88423605000 # number of overall MSHR uncacheable cycles 214system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses 215system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses 216system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses 217system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses 218system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses 219system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses 220system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.359249 # mshr miss rate for ReadExReq accesses 221system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses 222system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses 223system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses 224system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses 225system.cpu.l2cache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses 226system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses 227system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses 228system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses 229system.cpu.l2cache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses 230system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 231system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency 232system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency 233system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency 234system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency 235system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency 236system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency 237system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency 238system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 239system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency 240system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency 241system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency 242system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 243system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency 244system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency 245system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency 246system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 247system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 248system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 249system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 250system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 251system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 252system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 253system.iocache.replacements 47503 # number of replacements 254system.iocache.tagsinuse 0.108744 # Cycle average of tags in use 255system.iocache.total_refs 0 # Total number of references to valid blocks. 256system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. 257system.iocache.avg_refs 0 # Average number of references to valid blocks. 258system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit. 259system.iocache.occ_blocks::pc.south_bridge.ide 0.108744 # Average occupied blocks per requestor 260system.iocache.occ_percent::pc.south_bridge.ide 0.006796 # Average percentage of cache occupancy 261system.iocache.occ_percent::total 0.006796 # Average percentage of cache occupancy 262system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses 263system.iocache.ReadReq_misses::total 838 # number of ReadReq misses 264system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 265system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 266system.iocache.demand_misses::pc.south_bridge.ide 47558 # number of demand (read+write) misses 267system.iocache.demand_misses::total 47558 # number of demand (read+write) misses 268system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses 269system.iocache.overall_misses::total 47558 # number of overall misses 270system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129993932 # number of ReadReq miss cycles 271system.iocache.ReadReq_miss_latency::total 129993932 # number of ReadReq miss cycles 272system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10714208160 # number of WriteReq miss cycles 273system.iocache.WriteReq_miss_latency::total 10714208160 # number of WriteReq miss cycles 274system.iocache.demand_miss_latency::pc.south_bridge.ide 10844202092 # number of demand (read+write) miss cycles 275system.iocache.demand_miss_latency::total 10844202092 # number of demand (read+write) miss cycles 276system.iocache.overall_miss_latency::pc.south_bridge.ide 10844202092 # number of overall miss cycles 277system.iocache.overall_miss_latency::total 10844202092 # number of overall miss cycles 278system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) 279system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) 280system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 281system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 282system.iocache.demand_accesses::pc.south_bridge.ide 47558 # number of demand (read+write) accesses 283system.iocache.demand_accesses::total 47558 # number of demand (read+write) accesses 284system.iocache.overall_accesses::pc.south_bridge.ide 47558 # number of overall (read+write) accesses 285system.iocache.overall_accesses::total 47558 # number of overall (read+write) accesses 286system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 287system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 288system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 289system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 290system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 291system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 292system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 293system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 294system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155124.023866 # average ReadReq miss latency 295system.iocache.ReadReq_avg_miss_latency::total 155124.023866 # average ReadReq miss latency 296system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229328.085616 # average WriteReq miss latency 297system.iocache.WriteReq_avg_miss_latency::total 229328.085616 # average WriteReq miss latency 298system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency 299system.iocache.demand_avg_miss_latency::total 228020.566298 # average overall miss latency 300system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency 301system.iocache.overall_avg_miss_latency::total 228020.566298 # average overall miss latency 302system.iocache.blocked_cycles::no_mshrs 89624012 # number of cycles access was blocked 303system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 304system.iocache.blocked::no_mshrs 10977 # number of cycles access was blocked 305system.iocache.blocked::no_targets 0 # number of cycles access was blocked 306system.iocache.avg_blocked_cycles::no_mshrs 8164.709119 # average number of cycles each access was blocked 307system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 308system.iocache.fast_writes 0 # number of fast writes performed 309system.iocache.cache_copies 0 # number of cache copies performed 310system.iocache.writebacks::writebacks 46667 # number of writebacks 311system.iocache.writebacks::total 46667 # number of writebacks 312system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 838 # number of ReadReq MSHR misses 313system.iocache.ReadReq_mshr_misses::total 838 # number of ReadReq MSHR misses 314system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 315system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 316system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 # number of demand (read+write) MSHR misses 317system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses 318system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses 319system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses 320system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86387000 # number of ReadReq MSHR miss cycles 321system.iocache.ReadReq_mshr_miss_latency::total 86387000 # number of ReadReq MSHR miss cycles 322system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8284511992 # number of WriteReq MSHR miss cycles 323system.iocache.WriteReq_mshr_miss_latency::total 8284511992 # number of WriteReq MSHR miss cycles 324system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of demand (read+write) MSHR miss cycles 325system.iocache.demand_mshr_miss_latency::total 8370898992 # number of demand (read+write) MSHR miss cycles 326system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of overall MSHR miss cycles 327system.iocache.overall_mshr_miss_latency::total 8370898992 # number of overall MSHR miss cycles 328system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 329system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 330system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 331system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 332system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 333system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 334system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 335system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 336system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103087.112172 # average ReadReq mshr miss latency 337system.iocache.ReadReq_avg_mshr_miss_latency::total 103087.112172 # average ReadReq mshr miss latency 338system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177322.602568 # average WriteReq mshr miss latency 339system.iocache.WriteReq_avg_mshr_miss_latency::total 177322.602568 # average WriteReq mshr miss latency 340system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency 341system.iocache.demand_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency 342system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency 343system.iocache.overall_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency 344system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 345system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 346system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 347system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 348system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 349system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 350system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 351system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 352system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 353system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 354system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 355system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 356system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 357system.cpu.numCycles 10392045150 # number of cpu cycles simulated 358system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 359system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 360system.cpu.committedInsts 128174734 # Number of instructions committed 361system.cpu.committedOps 247089109 # Number of ops (including micro ops) committed 362system.cpu.num_int_alu_accesses 231827885 # Number of integer alu accesses 363system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 364system.cpu.num_func_calls 0 # number of times a function call or return occured 365system.cpu.num_conditional_control_insts 23138722 # number of instructions that are conditional controls 366system.cpu.num_int_insts 231827885 # number of integer instructions 367system.cpu.num_fp_insts 0 # number of float instructions 368system.cpu.num_int_register_reads 566609561 # number of times the integer registers were read 369system.cpu.num_int_register_writes 292994515 # number of times the integer registers were written 370system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 371system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 372system.cpu.num_mem_refs 22210252 # number of memory refs 373system.cpu.num_load_insts 13855140 # Number of load instructions 374system.cpu.num_store_insts 8355112 # Number of store instructions 375system.cpu.num_idle_cycles 9776628704.958118 # Number of idle cycles 376system.cpu.num_busy_cycles 615416445.041882 # Number of busy cycles 377system.cpu.not_idle_fraction 0.059220 # Percentage of non-idle cycles 378system.cpu.idle_fraction 0.940780 # Percentage of idle cycles 379system.cpu.kern.inst.arm 0 # number of arm instructions executed 380system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 381system.cpu.icache.replacements 790545 # number of replacements 382system.cpu.icache.tagsinuse 510.338891 # Cycle average of tags in use 383system.cpu.icache.total_refs 144363546 # Total number of references to valid blocks. 384system.cpu.icache.sampled_refs 791057 # Sample count of references to valid blocks. 385system.cpu.icache.avg_refs 182.494493 # Average number of references to valid blocks. 386system.cpu.icache.warmup_cycle 160970951000 # Cycle when the warmup percentage was hit. 387system.cpu.icache.occ_blocks::cpu.inst 510.338891 # Average occupied blocks per requestor 388system.cpu.icache.occ_percent::cpu.inst 0.996756 # Average percentage of cache occupancy 389system.cpu.icache.occ_percent::total 0.996756 # Average percentage of cache occupancy 390system.cpu.icache.ReadReq_hits::cpu.inst 144363546 # number of ReadReq hits 391system.cpu.icache.ReadReq_hits::total 144363546 # number of ReadReq hits 392system.cpu.icache.demand_hits::cpu.inst 144363546 # number of demand (read+write) hits 393system.cpu.icache.demand_hits::total 144363546 # number of demand (read+write) hits 394system.cpu.icache.overall_hits::cpu.inst 144363546 # number of overall hits 395system.cpu.icache.overall_hits::total 144363546 # number of overall hits 396system.cpu.icache.ReadReq_misses::cpu.inst 791064 # number of ReadReq misses 397system.cpu.icache.ReadReq_misses::total 791064 # number of ReadReq misses 398system.cpu.icache.demand_misses::cpu.inst 791064 # number of demand (read+write) misses 399system.cpu.icache.demand_misses::total 791064 # number of demand (read+write) misses 400system.cpu.icache.overall_misses::cpu.inst 791064 # number of overall misses 401system.cpu.icache.overall_misses::total 791064 # number of overall misses 402system.cpu.icache.ReadReq_miss_latency::cpu.inst 11792673000 # number of ReadReq miss cycles 403system.cpu.icache.ReadReq_miss_latency::total 11792673000 # number of ReadReq miss cycles 404system.cpu.icache.demand_miss_latency::cpu.inst 11792673000 # number of demand (read+write) miss cycles 405system.cpu.icache.demand_miss_latency::total 11792673000 # number of demand (read+write) miss cycles 406system.cpu.icache.overall_miss_latency::cpu.inst 11792673000 # number of overall miss cycles 407system.cpu.icache.overall_miss_latency::total 11792673000 # number of overall miss cycles 408system.cpu.icache.ReadReq_accesses::cpu.inst 145154610 # number of ReadReq accesses(hits+misses) 409system.cpu.icache.ReadReq_accesses::total 145154610 # number of ReadReq accesses(hits+misses) 410system.cpu.icache.demand_accesses::cpu.inst 145154610 # number of demand (read+write) accesses 411system.cpu.icache.demand_accesses::total 145154610 # number of demand (read+write) accesses 412system.cpu.icache.overall_accesses::cpu.inst 145154610 # number of overall (read+write) accesses 413system.cpu.icache.overall_accesses::total 145154610 # number of overall (read+write) accesses 414system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005450 # miss rate for ReadReq accesses 415system.cpu.icache.ReadReq_miss_rate::total 0.005450 # miss rate for ReadReq accesses 416system.cpu.icache.demand_miss_rate::cpu.inst 0.005450 # miss rate for demand accesses 417system.cpu.icache.demand_miss_rate::total 0.005450 # miss rate for demand accesses 418system.cpu.icache.overall_miss_rate::cpu.inst 0.005450 # miss rate for overall accesses 419system.cpu.icache.overall_miss_rate::total 0.005450 # miss rate for overall accesses 420system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14907.356421 # average ReadReq miss latency 421system.cpu.icache.ReadReq_avg_miss_latency::total 14907.356421 # average ReadReq miss latency 422system.cpu.icache.demand_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency 423system.cpu.icache.demand_avg_miss_latency::total 14907.356421 # average overall miss latency 424system.cpu.icache.overall_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency 425system.cpu.icache.overall_avg_miss_latency::total 14907.356421 # average overall miss latency 426system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 427system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 428system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 429system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 430system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 431system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 432system.cpu.icache.fast_writes 0 # number of fast writes performed 433system.cpu.icache.cache_copies 0 # number of cache copies performed 434system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791064 # number of ReadReq MSHR misses 435system.cpu.icache.ReadReq_mshr_misses::total 791064 # number of ReadReq MSHR misses 436system.cpu.icache.demand_mshr_misses::cpu.inst 791064 # number of demand (read+write) MSHR misses 437system.cpu.icache.demand_mshr_misses::total 791064 # number of demand (read+write) MSHR misses 438system.cpu.icache.overall_mshr_misses::cpu.inst 791064 # number of overall MSHR misses 439system.cpu.icache.overall_mshr_misses::total 791064 # number of overall MSHR misses 440system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9418462000 # number of ReadReq MSHR miss cycles 441system.cpu.icache.ReadReq_mshr_miss_latency::total 9418462000 # number of ReadReq MSHR miss cycles 442system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9418462000 # number of demand (read+write) MSHR miss cycles 443system.cpu.icache.demand_mshr_miss_latency::total 9418462000 # number of demand (read+write) MSHR miss cycles 444system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9418462000 # number of overall MSHR miss cycles 445system.cpu.icache.overall_mshr_miss_latency::total 9418462000 # number of overall MSHR miss cycles 446system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for ReadReq accesses 447system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005450 # mshr miss rate for ReadReq accesses 448system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for demand accesses 449system.cpu.icache.demand_mshr_miss_rate::total 0.005450 # mshr miss rate for demand accesses 450system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for overall accesses 451system.cpu.icache.overall_mshr_miss_rate::total 0.005450 # mshr miss rate for overall accesses 452system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11906.068283 # average ReadReq mshr miss latency 453system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11906.068283 # average ReadReq mshr miss latency 454system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency 455system.cpu.icache.demand_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency 456system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency 457system.cpu.icache.overall_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency 458system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 459system.cpu.itb_walker_cache.replacements 3550 # number of replacements 460system.cpu.itb_walker_cache.tagsinuse 3.065778 # Cycle average of tags in use 461system.cpu.itb_walker_cache.total_refs 7809 # Total number of references to valid blocks. 462system.cpu.itb_walker_cache.sampled_refs 3562 # Sample count of references to valid blocks. 463system.cpu.itb_walker_cache.avg_refs 2.192308 # Average number of references to valid blocks. 464system.cpu.itb_walker_cache.warmup_cycle 5171078849000 # Cycle when the warmup percentage was hit. 465system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.065778 # Average occupied blocks per requestor 466system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191611 # Average percentage of cache occupancy 467system.cpu.itb_walker_cache.occ_percent::total 0.191611 # Average percentage of cache occupancy 468system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7809 # number of ReadReq hits 469system.cpu.itb_walker_cache.ReadReq_hits::total 7809 # number of ReadReq hits 470system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 471system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 472system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7811 # number of demand (read+write) hits 473system.cpu.itb_walker_cache.demand_hits::total 7811 # number of demand (read+write) hits 474system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7811 # number of overall hits 475system.cpu.itb_walker_cache.overall_hits::total 7811 # number of overall hits 476system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4415 # number of ReadReq misses 477system.cpu.itb_walker_cache.ReadReq_misses::total 4415 # number of ReadReq misses 478system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4415 # number of demand (read+write) misses 479system.cpu.itb_walker_cache.demand_misses::total 4415 # number of demand (read+write) misses 480system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4415 # number of overall misses 481system.cpu.itb_walker_cache.overall_misses::total 4415 # number of overall misses 482system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 53239000 # number of ReadReq miss cycles 483system.cpu.itb_walker_cache.ReadReq_miss_latency::total 53239000 # number of ReadReq miss cycles 484system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 53239000 # number of demand (read+write) miss cycles 485system.cpu.itb_walker_cache.demand_miss_latency::total 53239000 # number of demand (read+write) miss cycles 486system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 53239000 # number of overall miss cycles 487system.cpu.itb_walker_cache.overall_miss_latency::total 53239000 # number of overall miss cycles 488system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) 489system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) 490system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 491system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 492system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses 493system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses 494system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses 495system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses 496system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361175 # miss rate for ReadReq accesses 497system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361175 # miss rate for ReadReq accesses 498system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361116 # miss rate for demand accesses 499system.cpu.itb_walker_cache.demand_miss_rate::total 0.361116 # miss rate for demand accesses 500system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361116 # miss rate for overall accesses 501system.cpu.itb_walker_cache.overall_miss_rate::total 0.361116 # miss rate for overall accesses 502system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12058.663647 # average ReadReq miss latency 503system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12058.663647 # average ReadReq miss latency 504system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency 505system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12058.663647 # average overall miss latency 506system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency 507system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12058.663647 # average overall miss latency 508system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 509system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 510system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 511system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 512system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 513system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 514system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 515system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 516system.cpu.itb_walker_cache.writebacks::writebacks 830 # number of writebacks 517system.cpu.itb_walker_cache.writebacks::total 830 # number of writebacks 518system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4415 # number of ReadReq MSHR misses 519system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4415 # number of ReadReq MSHR misses 520system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4415 # number of demand (read+write) MSHR misses 521system.cpu.itb_walker_cache.demand_mshr_misses::total 4415 # number of demand (read+write) MSHR misses 522system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4415 # number of overall MSHR misses 523system.cpu.itb_walker_cache.overall_mshr_misses::total 4415 # number of overall MSHR misses 524system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39994000 # number of ReadReq MSHR miss cycles 525system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39994000 # number of ReadReq MSHR miss cycles 526system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39994000 # number of demand (read+write) MSHR miss cycles 527system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39994000 # number of demand (read+write) MSHR miss cycles 528system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39994000 # number of overall MSHR miss cycles 529system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39994000 # number of overall MSHR miss cycles 530system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361175 # mshr miss rate for ReadReq accesses 531system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361175 # mshr miss rate for ReadReq accesses 532system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for demand accesses 533system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361116 # mshr miss rate for demand accesses 534system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for overall accesses 535system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361116 # mshr miss rate for overall accesses 536system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average ReadReq mshr miss latency 537system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9058.663647 # average ReadReq mshr miss latency 538system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency 539system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency 540system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency 541system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency 542system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 543system.cpu.dtb_walker_cache.replacements 7810 # number of replacements 544system.cpu.dtb_walker_cache.tagsinuse 5.052392 # Cycle average of tags in use 545system.cpu.dtb_walker_cache.total_refs 12921 # Total number of references to valid blocks. 546system.cpu.dtb_walker_cache.sampled_refs 7826 # Sample count of references to valid blocks. 547system.cpu.dtb_walker_cache.avg_refs 1.651035 # Average number of references to valid blocks. 548system.cpu.dtb_walker_cache.warmup_cycle 5166488673000 # Cycle when the warmup percentage was hit. 549system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052392 # Average occupied blocks per requestor 550system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315774 # Average percentage of cache occupancy 551system.cpu.dtb_walker_cache.occ_percent::total 0.315774 # Average percentage of cache occupancy 552system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12921 # number of ReadReq hits 553system.cpu.dtb_walker_cache.ReadReq_hits::total 12921 # number of ReadReq hits 554system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12921 # number of demand (read+write) hits 555system.cpu.dtb_walker_cache.demand_hits::total 12921 # number of demand (read+write) hits 556system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12921 # number of overall hits 557system.cpu.dtb_walker_cache.overall_hits::total 12921 # number of overall hits 558system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9010 # number of ReadReq misses 559system.cpu.dtb_walker_cache.ReadReq_misses::total 9010 # number of ReadReq misses 560system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9010 # number of demand (read+write) misses 561system.cpu.dtb_walker_cache.demand_misses::total 9010 # number of demand (read+write) misses 562system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9010 # number of overall misses 563system.cpu.dtb_walker_cache.overall_misses::total 9010 # number of overall misses 564system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 118862500 # number of ReadReq miss cycles 565system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 118862500 # number of ReadReq miss cycles 566system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 118862500 # number of demand (read+write) miss cycles 567system.cpu.dtb_walker_cache.demand_miss_latency::total 118862500 # number of demand (read+write) miss cycles 568system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 118862500 # number of overall miss cycles 569system.cpu.dtb_walker_cache.overall_miss_latency::total 118862500 # number of overall miss cycles 570system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21931 # number of ReadReq accesses(hits+misses) 571system.cpu.dtb_walker_cache.ReadReq_accesses::total 21931 # number of ReadReq accesses(hits+misses) 572system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21931 # number of demand (read+write) accesses 573system.cpu.dtb_walker_cache.demand_accesses::total 21931 # number of demand (read+write) accesses 574system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21931 # number of overall (read+write) accesses 575system.cpu.dtb_walker_cache.overall_accesses::total 21931 # number of overall (read+write) accesses 576system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.410834 # miss rate for ReadReq accesses 577system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.410834 # miss rate for ReadReq accesses 578system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.410834 # miss rate for demand accesses 579system.cpu.dtb_walker_cache.demand_miss_rate::total 0.410834 # miss rate for demand accesses 580system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.410834 # miss rate for overall accesses 581system.cpu.dtb_walker_cache.overall_miss_rate::total 0.410834 # miss rate for overall accesses 582system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13192.286349 # average ReadReq miss latency 583system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13192.286349 # average ReadReq miss latency 584system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency 585system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13192.286349 # average overall miss latency 586system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency 587system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13192.286349 # average overall miss latency 588system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 589system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 590system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 591system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 592system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 593system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 594system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 595system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 596system.cpu.dtb_walker_cache.writebacks::writebacks 3142 # number of writebacks 597system.cpu.dtb_walker_cache.writebacks::total 3142 # number of writebacks 598system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9010 # number of ReadReq MSHR misses 599system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9010 # number of ReadReq MSHR misses 600system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9010 # number of demand (read+write) MSHR misses 601system.cpu.dtb_walker_cache.demand_mshr_misses::total 9010 # number of demand (read+write) MSHR misses 602system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9010 # number of overall MSHR misses 603system.cpu.dtb_walker_cache.overall_mshr_misses::total 9010 # number of overall MSHR misses 604system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 91832000 # number of ReadReq MSHR miss cycles 605system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 91832000 # number of ReadReq MSHR miss cycles 606system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 91832000 # number of demand (read+write) MSHR miss cycles 607system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 91832000 # number of demand (read+write) MSHR miss cycles 608system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 91832000 # number of overall MSHR miss cycles 609system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 91832000 # number of overall MSHR miss cycles 610system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for ReadReq accesses 611system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.410834 # mshr miss rate for ReadReq accesses 612system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for demand accesses 613system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.410834 # mshr miss rate for demand accesses 614system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for overall accesses 615system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.410834 # mshr miss rate for overall accesses 616system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average ReadReq mshr miss latency 617system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10192.230855 # average ReadReq mshr miss latency 618system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency 619system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency 620system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency 621system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency 622system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 623system.cpu.dcache.replacements 1622132 # number of replacements 624system.cpu.dcache.tagsinuse 511.997396 # Cycle average of tags in use 625system.cpu.dcache.total_refs 20004026 # Total number of references to valid blocks. 626system.cpu.dcache.sampled_refs 1622644 # Sample count of references to valid blocks. 627system.cpu.dcache.avg_refs 12.328044 # Average number of references to valid blocks. 628system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit. 629system.cpu.dcache.occ_blocks::cpu.data 511.997396 # Average occupied blocks per requestor 630system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy 631system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy 632system.cpu.dcache.ReadReq_hits::cpu.data 11972131 # number of ReadReq hits 633system.cpu.dcache.ReadReq_hits::total 11972131 # number of ReadReq hits 634system.cpu.dcache.WriteReq_hits::cpu.data 8029723 # number of WriteReq hits 635system.cpu.dcache.WriteReq_hits::total 8029723 # number of WriteReq hits 636system.cpu.dcache.demand_hits::cpu.data 20001854 # number of demand (read+write) hits 637system.cpu.dcache.demand_hits::total 20001854 # number of demand (read+write) hits 638system.cpu.dcache.overall_hits::cpu.data 20001854 # number of overall hits 639system.cpu.dcache.overall_hits::total 20001854 # number of overall hits 640system.cpu.dcache.ReadReq_misses::cpu.data 1309489 # number of ReadReq misses 641system.cpu.dcache.ReadReq_misses::total 1309489 # number of ReadReq misses 642system.cpu.dcache.WriteReq_misses::cpu.data 315369 # number of WriteReq misses 643system.cpu.dcache.WriteReq_misses::total 315369 # number of WriteReq misses 644system.cpu.dcache.demand_misses::cpu.data 1624858 # number of demand (read+write) misses 645system.cpu.dcache.demand_misses::total 1624858 # number of demand (read+write) misses 646system.cpu.dcache.overall_misses::cpu.data 1624858 # number of overall misses 647system.cpu.dcache.overall_misses::total 1624858 # number of overall misses 648system.cpu.dcache.ReadReq_miss_latency::cpu.data 19885711500 # number of ReadReq miss cycles 649system.cpu.dcache.ReadReq_miss_latency::total 19885711500 # number of ReadReq miss cycles 650system.cpu.dcache.WriteReq_miss_latency::cpu.data 9346101000 # number of WriteReq miss cycles 651system.cpu.dcache.WriteReq_miss_latency::total 9346101000 # number of WriteReq miss cycles 652system.cpu.dcache.demand_miss_latency::cpu.data 29231812500 # number of demand (read+write) miss cycles 653system.cpu.dcache.demand_miss_latency::total 29231812500 # number of demand (read+write) miss cycles 654system.cpu.dcache.overall_miss_latency::cpu.data 29231812500 # number of overall miss cycles 655system.cpu.dcache.overall_miss_latency::total 29231812500 # number of overall miss cycles 656system.cpu.dcache.ReadReq_accesses::cpu.data 13281620 # number of ReadReq accesses(hits+misses) 657system.cpu.dcache.ReadReq_accesses::total 13281620 # number of ReadReq accesses(hits+misses) 658system.cpu.dcache.WriteReq_accesses::cpu.data 8345092 # number of WriteReq accesses(hits+misses) 659system.cpu.dcache.WriteReq_accesses::total 8345092 # number of WriteReq accesses(hits+misses) 660system.cpu.dcache.demand_accesses::cpu.data 21626712 # number of demand (read+write) accesses 661system.cpu.dcache.demand_accesses::total 21626712 # number of demand (read+write) accesses 662system.cpu.dcache.overall_accesses::cpu.data 21626712 # number of overall (read+write) accesses 663system.cpu.dcache.overall_accesses::total 21626712 # number of overall (read+write) accesses 664system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098594 # miss rate for ReadReq accesses 665system.cpu.dcache.ReadReq_miss_rate::total 0.098594 # miss rate for ReadReq accesses 666system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037791 # miss rate for WriteReq accesses 667system.cpu.dcache.WriteReq_miss_rate::total 0.037791 # miss rate for WriteReq accesses 668system.cpu.dcache.demand_miss_rate::cpu.data 0.075132 # miss rate for demand accesses 669system.cpu.dcache.demand_miss_rate::total 0.075132 # miss rate for demand accesses 670system.cpu.dcache.overall_miss_rate::cpu.data 0.075132 # miss rate for overall accesses 671system.cpu.dcache.overall_miss_rate::total 0.075132 # miss rate for overall accesses 672system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15185.856086 # average ReadReq miss latency 673system.cpu.dcache.ReadReq_avg_miss_latency::total 15185.856086 # average ReadReq miss latency 674system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29635.446096 # average WriteReq miss latency 675system.cpu.dcache.WriteReq_avg_miss_latency::total 29635.446096 # average WriteReq miss latency 676system.cpu.dcache.demand_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency 677system.cpu.dcache.demand_avg_miss_latency::total 17990.379775 # average overall miss latency 678system.cpu.dcache.overall_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency 679system.cpu.dcache.overall_avg_miss_latency::total 17990.379775 # average overall miss latency 680system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 681system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 682system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 683system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 684system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 685system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 686system.cpu.dcache.fast_writes 0 # number of fast writes performed 687system.cpu.dcache.cache_copies 0 # number of cache copies performed 688system.cpu.dcache.writebacks::writebacks 1539490 # number of writebacks 689system.cpu.dcache.writebacks::total 1539490 # number of writebacks 690system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309489 # number of ReadReq MSHR misses 691system.cpu.dcache.ReadReq_mshr_misses::total 1309489 # number of ReadReq MSHR misses 692system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315369 # number of WriteReq MSHR misses 693system.cpu.dcache.WriteReq_mshr_misses::total 315369 # number of WriteReq MSHR misses 694system.cpu.dcache.demand_mshr_misses::cpu.data 1624858 # number of demand (read+write) MSHR misses 695system.cpu.dcache.demand_mshr_misses::total 1624858 # number of demand (read+write) MSHR misses 696system.cpu.dcache.overall_mshr_misses::cpu.data 1624858 # number of overall MSHR misses 697system.cpu.dcache.overall_mshr_misses::total 1624858 # number of overall MSHR misses 698system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15957199501 # number of ReadReq MSHR miss cycles 699system.cpu.dcache.ReadReq_mshr_miss_latency::total 15957199501 # number of ReadReq MSHR miss cycles 700system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8399992000 # number of WriteReq MSHR miss cycles 701system.cpu.dcache.WriteReq_mshr_miss_latency::total 8399992000 # number of WriteReq MSHR miss cycles 702system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24357191501 # number of demand (read+write) MSHR miss cycles 703system.cpu.dcache.demand_mshr_miss_latency::total 24357191501 # number of demand (read+write) MSHR miss cycles 704system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24357191501 # number of overall MSHR miss cycles 705system.cpu.dcache.overall_mshr_miss_latency::total 24357191501 # number of overall MSHR miss cycles 706system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 93628676500 # number of ReadReq MSHR uncacheable cycles 707system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 93628676500 # number of ReadReq MSHR uncacheable cycles 708system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467841500 # number of WriteReq MSHR uncacheable cycles 709system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467841500 # number of WriteReq MSHR uncacheable cycles 710system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96096518000 # number of overall MSHR uncacheable cycles 711system.cpu.dcache.overall_mshr_uncacheable_latency::total 96096518000 # number of overall MSHR uncacheable cycles 712system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098594 # mshr miss rate for ReadReq accesses 713system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098594 # mshr miss rate for ReadReq accesses 714system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037791 # mshr miss rate for WriteReq accesses 715system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037791 # mshr miss rate for WriteReq accesses 716system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075132 # mshr miss rate for demand accesses 717system.cpu.dcache.demand_mshr_miss_rate::total 0.075132 # mshr miss rate for demand accesses 718system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075132 # mshr miss rate for overall accesses 719system.cpu.dcache.overall_mshr_miss_rate::total 0.075132 # mshr miss rate for overall accesses 720system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12185.821722 # average ReadReq mshr miss latency 721system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12185.821722 # average ReadReq mshr miss latency 722system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26635.439755 # average WriteReq mshr miss latency 723system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26635.439755 # average WriteReq mshr miss latency 724system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14990.350850 # average overall mshr miss latency 725system.cpu.dcache.demand_avg_mshr_miss_latency::total 14990.350850 # average overall mshr miss latency 726system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14990.350850 # average overall mshr miss latency 727system.cpu.dcache.overall_avg_mshr_miss_latency::total 14990.350850 # average overall mshr miss latency 728system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 729system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 730system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 731system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 732system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 733system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 734system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 735 736---------- End Simulation Statistics ---------- 737