stats.txt revision 11138
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.783867 # Number of seconds simulated 4sim_ticks 2783867052000 # Number of ticks simulated 5final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1171566 # Simulator instruction rate (inst/s) 8host_op_rate 1426194 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 22843865684 # Simulator tick rate (ticks/s) 10host_mem_usage 624228 # Number of bytes of host memory used 11host_seconds 121.87 # Real time elapsed on the host 12sim_insts 142772879 # Number of instructions simulated 13sim_ops 173803124 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10324836 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 161845 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 189182 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 433574 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3708811 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 4142936 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 433574 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3175761 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 3182056 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 3175761 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 433574 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3715106 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 7324992 # Total bandwidth to/from this memory (bytes/s) 54system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 55system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 56system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 57system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 58system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 59system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 60system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 63system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 64system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 65system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 66system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 67system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 68system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 69system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 70system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 71system.cf0.dma_write_txs 631 # Number of DMA write transactions. 72system.cpu_clk_domain.clock 500 # Clock period in ticks 73system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 74system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 76system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 79system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 81system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 82system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 83system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 84system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 85system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 86system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 87system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 88system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 89system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 90system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 91system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 92system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 93system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 94system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 95system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 96system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 97system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 98system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 99system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 100system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 101system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 102system.cpu.dtb.walker.walks 10029 # Table walker walks requested 103system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors 104system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency 105system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency 106system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency 107system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 108system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 109system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 110system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated 111system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated 112system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated 113system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst 114system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 115system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst 116system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst 117system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 118system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst 119system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst 120system.cpu.dtb.inst_hits 0 # ITB inst hits 121system.cpu.dtb.inst_misses 0 # ITB inst misses 122system.cpu.dtb.read_hits 31526223 # DTB read hits 123system.cpu.dtb.read_misses 8581 # DTB read misses 124system.cpu.dtb.write_hits 23124452 # DTB write hits 125system.cpu.dtb.write_misses 1448 # DTB write misses 126system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 127system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 128system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 129system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 130system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB 131system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 132system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 133system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 134system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 135system.cpu.dtb.read_accesses 31534804 # DTB read accesses 136system.cpu.dtb.write_accesses 23125900 # DTB write accesses 137system.cpu.dtb.inst_accesses 0 # ITB inst accesses 138system.cpu.dtb.hits 54650675 # DTB hits 139system.cpu.dtb.misses 10029 # DTB misses 140system.cpu.dtb.accesses 54660704 # DTB accesses 141system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 142system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 143system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 144system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 145system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 146system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 147system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 148system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 149system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 150system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 151system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 152system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 153system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 154system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 155system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 156system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 157system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 158system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 159system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 160system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 161system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 162system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 163system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 164system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 165system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 166system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 167system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 168system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 169system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 170system.cpu.itb.walker.walks 4762 # Table walker walks requested 171system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 172system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 173system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 174system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 175system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 176system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 177system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 178system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated 179system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated 180system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated 181system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 182system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst 183system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst 184system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 185system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst 186system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst 187system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst 188system.cpu.itb.inst_hits 147039346 # ITB inst hits 189system.cpu.itb.inst_misses 4762 # ITB inst misses 190system.cpu.itb.read_hits 0 # DTB read hits 191system.cpu.itb.read_misses 0 # DTB read misses 192system.cpu.itb.write_hits 0 # DTB write hits 193system.cpu.itb.write_misses 0 # DTB write misses 194system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 195system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 196system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 197system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 198system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 199system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 200system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 201system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 202system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 203system.cpu.itb.read_accesses 0 # DTB read accesses 204system.cpu.itb.write_accesses 0 # DTB write accesses 205system.cpu.itb.inst_accesses 147044108 # ITB inst accesses 206system.cpu.itb.hits 147039346 # DTB hits 207system.cpu.itb.misses 4762 # DTB misses 208system.cpu.itb.accesses 147044108 # DTB accesses 209system.cpu.numCycles 5567737188 # number of cpu cycles simulated 210system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 211system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 212system.cpu.committedInsts 142772879 # Number of instructions committed 213system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed 214system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses 215system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 216system.cpu.num_func_calls 16873899 # number of times a function call or return occured 217system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls 218system.cpu.num_int_insts 153162683 # number of integer instructions 219system.cpu.num_fp_insts 11484 # number of float instructions 220system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read 221system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written 222system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 223system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 224system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read 225system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written 226system.cpu.num_mem_refs 55939276 # number of memory refs 227system.cpu.num_load_insts 31855884 # Number of load instructions 228system.cpu.num_store_insts 24083392 # Number of store instructions 229system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles 230system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles 231system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles 232system.cpu.idle_fraction 0.968015 # Percentage of idle cycles 233system.cpu.Branches 36396981 # Number of branches fetched 234system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 235system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction 236system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction 237system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction 238system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction 239system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction 240system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction 241system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction 242system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction 243system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction 244system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction 245system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction 246system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction 247system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction 248system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction 249system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction 250system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction 251system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction 252system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction 253system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction 254system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction 255system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction 256system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction 257system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction 258system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction 259system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction 260system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction 261system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction 262system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction 263system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 264system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction 265system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction 266system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 267system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 268system.cpu.op_class::total 177219912 # Class of executed instruction 269system.cpu.kern.inst.arm 0 # number of arm instructions executed 270system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed 271system.cpu.dcache.tags.replacements 819402 # number of replacements 272system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use 273system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. 274system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. 275system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks. 276system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 277system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 278system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 279system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 280system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 281system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 282system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 283system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 284system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 285system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses 286system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses 287system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits 288system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits 289system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits 290system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits 291system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits 292system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits 293system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits 294system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits 295system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits 296system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits 297system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits 298system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits 299system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits 300system.cpu.dcache.overall_hits::total 52864242 # number of overall hits 301system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses 302system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses 303system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses 304system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses 305system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses 306system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses 307system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses 308system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses 309system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 310system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 311system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses 312system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses 313system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses 314system.cpu.dcache.overall_misses::total 814074 # number of overall misses 315system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses) 316system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) 317system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses) 318system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) 319system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) 320system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) 321system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) 322system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) 323system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) 324system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) 325system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses 326system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses 327system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses 328system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses 329system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses 330system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses 331system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses 332system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses 333system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses 334system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses 335system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses 336system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses 337system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 338system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 339system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses 340system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses 341system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses 342system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses 343system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 344system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 345system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 346system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 347system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 348system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 349system.cpu.dcache.fast_writes 0 # number of fast writes performed 350system.cpu.dcache.cache_copies 0 # number of cache copies performed 351system.cpu.dcache.writebacks::writebacks 682040 # number of writebacks 352system.cpu.dcache.writebacks::total 682040 # number of writebacks 353system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 354system.cpu.icache.tags.replacements 1699214 # number of replacements 355system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use 356system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks. 357system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. 358system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. 359system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. 360system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor 361system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy 362system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy 363system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 368system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 369system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses 370system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses 371system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits 372system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits 373system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits 374system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits 375system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits 376system.cpu.icache.overall_hits::total 145342721 # number of overall hits 377system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses 378system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses 379system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses 380system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses 381system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses 382system.cpu.icache.overall_misses::total 1699732 # number of overall misses 383system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses) 384system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) 385system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses 386system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses 387system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses 388system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses 389system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses 390system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses 391system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses 392system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses 393system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses 394system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses 395system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 396system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 397system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 398system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 399system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 401system.cpu.icache.fast_writes 0 # number of fast writes performed 402system.cpu.icache.cache_copies 0 # number of cache copies performed 403system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 404system.cpu.l2cache.tags.replacements 109913 # number of replacements 405system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use 406system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks. 407system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. 408system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks. 409system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 410system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor 411system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor 412system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor 413system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.708883 # Average occupied blocks per requestor 414system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.628332 # Average occupied blocks per requestor 415system.cpu.l2cache.tags.occ_percent::writebacks 0.744080 # Average percentage of cache occupancy 416system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 417system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 418system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy 419system.cpu.l2cache.tags.occ_percent::cpu.data 0.110163 # Average percentage of cache occupancy 420system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy 421system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 422system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id 423system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 424system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 425system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id 426system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id 427system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id 428system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id 429system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 430system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id 431system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses 432system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses 433system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits 434system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits 435system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits 436system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits 437system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits 438system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 439system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits 440system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits 441system.cpu.l2cache.ReadExReq_hits::total 151146 # number of ReadExReq hits 442system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681416 # number of ReadCleanReq hits 443system.cpu.l2cache.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits 444system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits 445system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits 446system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits 447system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits 448system.cpu.l2cache.demand_hits::cpu.inst 1681416 # number of demand (read+write) hits 449system.cpu.l2cache.demand_hits::cpu.data 656586 # number of demand (read+write) hits 450system.cpu.l2cache.demand_hits::total 2349224 # number of demand (read+write) hits 451system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits 452system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits 453system.cpu.l2cache.overall_hits::cpu.inst 1681416 # number of overall hits 454system.cpu.l2cache.overall_hits::cpu.data 656586 # number of overall hits 455system.cpu.l2cache.overall_hits::total 2349224 # number of overall hits 456system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 457system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 458system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses 459system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses 460system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses 461system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 462system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 463system.cpu.l2cache.ReadExReq_misses::cpu.data 147776 # number of ReadExReq misses 464system.cpu.l2cache.ReadExReq_misses::total 147776 # number of ReadExReq misses 465system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses 466system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses 467system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses 468system.cpu.l2cache.ReadSharedReq_misses::total 15568 # number of ReadSharedReq misses 469system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 470system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 471system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses 472system.cpu.l2cache.demand_misses::cpu.data 163344 # number of demand (read+write) misses 473system.cpu.l2cache.demand_misses::total 181651 # number of demand (read+write) misses 474system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 475system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 476system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses 477system.cpu.l2cache.overall_misses::cpu.data 163344 # number of overall misses 478system.cpu.l2cache.overall_misses::total 181651 # number of overall misses 479system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) 480system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) 481system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) 482system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses) 483system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses) 484system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) 485system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) 486system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 487system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 488system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) 489system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) 490system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699714 # number of ReadCleanReq accesses(hits+misses) 491system.cpu.l2cache.ReadCleanReq_accesses::total 1699714 # number of ReadCleanReq accesses(hits+misses) 492system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) 493system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) 494system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses 495system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses 496system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses 497system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses 498system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses 499system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses 500system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses 501system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses 502system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses 503system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses 504system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses 505system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses 506system.cpu.l2cache.ReadReq_miss_rate::total 0.000801 # miss rate for ReadReq accesses 507system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses 508system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses 509system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 510system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 511system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494363 # miss rate for ReadExReq accesses 512system.cpu.l2cache.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses 513system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010765 # miss rate for ReadCleanReq accesses 514system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses 515system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses 516system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses 517system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses 518system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses 519system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010765 # miss rate for demand accesses 520system.cpu.l2cache.demand_miss_rate::cpu.data 0.199217 # miss rate for demand accesses 521system.cpu.l2cache.demand_miss_rate::total 0.071774 # miss rate for demand accesses 522system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses 523system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses 524system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010765 # miss rate for overall accesses 525system.cpu.l2cache.overall_miss_rate::cpu.data 0.199217 # miss rate for overall accesses 526system.cpu.l2cache.overall_miss_rate::total 0.071774 # miss rate for overall accesses 527system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 528system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 529system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 530system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 531system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 532system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 533system.cpu.l2cache.fast_writes 0 # number of fast writes performed 534system.cpu.l2cache.cache_copies 0 # number of cache copies performed 535system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks 536system.cpu.l2cache.writebacks::total 101949 # number of writebacks 537system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 538system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter. 539system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data. 540system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 541system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. 542system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 543system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 544system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution 545system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution 546system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution 547system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution 548system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution 549system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution 550system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution 551system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 552system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution 553system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution 554system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution 555system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution 556system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution 557system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes) 558system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes) 559system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) 560system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) 561system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) 562system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) 563system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) 564system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) 565system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) 566system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) 567system.cpu.toL2Bus.snoops 182974 # Total snoops (count) 568system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram 569system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram 570system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram 571system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 572system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram 573system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram 574system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 575system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 576system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 577system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 578system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram 579system.iobus.trans_dist::ReadReq 30164 # Transaction distribution 580system.iobus.trans_dist::ReadResp 30164 # Transaction distribution 581system.iobus.trans_dist::WriteReq 59002 # Transaction distribution 582system.iobus.trans_dist::WriteResp 59002 # Transaction distribution 583system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) 584system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 585system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 586system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 587system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 588system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 589system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 590system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 591system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 592system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 593system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 594system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 595system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 596system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 597system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 598system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 599system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 600system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 601system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 602system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 603system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 604system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) 605system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) 606system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) 607system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) 608system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) 609system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 610system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 611system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 612system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 613system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 614system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 615system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 616system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 617system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 618system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 619system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 620system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 621system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 622system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 623system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 625system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 627system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 629system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) 630system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) 633system.iocache.tags.replacements 36430 # number of replacements 634system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use 635system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 636system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. 637system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 638system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. 639system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor 640system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy 641system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy 642system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 643system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 644system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 645system.iocache.tags.tag_accesses 328176 # Number of tag accesses 646system.iocache.tags.data_accesses 328176 # Number of data accesses 647system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses 648system.iocache.ReadReq_misses::total 240 # number of ReadReq misses 649system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 650system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 651system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses 652system.iocache.demand_misses::total 240 # number of demand (read+write) misses 653system.iocache.overall_misses::realview.ide 240 # number of overall misses 654system.iocache.overall_misses::total 240 # number of overall misses 655system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) 656system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) 657system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 658system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 659system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses 660system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses 661system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses 662system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses 663system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 664system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 665system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 666system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 667system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 668system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 669system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 670system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 671system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 672system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 673system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 674system.iocache.blocked::no_targets 0 # number of cycles access was blocked 675system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 676system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 677system.iocache.fast_writes 0 # number of fast writes performed 678system.iocache.cache_copies 0 # number of cache copies performed 679system.iocache.writebacks::writebacks 36190 # number of writebacks 680system.iocache.writebacks::total 36190 # number of writebacks 681system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 682system.membus.trans_dist::ReadReq 40087 # Transaction distribution 683system.membus.trans_dist::ReadResp 74202 # Transaction distribution 684system.membus.trans_dist::WriteReq 27546 # Transaction distribution 685system.membus.trans_dist::WriteResp 27546 # Transaction distribution 686system.membus.trans_dist::Writeback 138139 # Transaction distribution 687system.membus.trans_dist::CleanEvict 7977 # Transaction distribution 688system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution 689system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 690system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution 691system.membus.trans_dist::ReadExReq 145997 # Transaction distribution 692system.membus.trans_dist::ReadExResp 145997 # Transaction distribution 693system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution 694system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 695system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 696system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) 697system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 698system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) 699system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) 700system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) 701system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) 702system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) 703system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes) 704system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) 705system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 706system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) 707system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092412 # Cumulative packet size per connected master and slave (bytes) 708system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255385 # Cumulative packet size per connected master and slave (bytes) 709system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) 710system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) 711system.membus.pkt_size::total 20586905 # Cumulative packet size per connected master and slave (bytes) 712system.membus.snoops 0 # Total snoops (count) 713system.membus.snoop_fanout::samples 434821 # Request fanout histogram 714system.membus.snoop_fanout::mean 1 # Request fanout histogram 715system.membus.snoop_fanout::stdev 0 # Request fanout histogram 716system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 717system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 718system.membus.snoop_fanout::1 434821 100.00% 100.00% # Request fanout histogram 719system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 720system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 721system.membus.snoop_fanout::min_value 1 # Request fanout histogram 722system.membus.snoop_fanout::max_value 1 # Request fanout histogram 723system.membus.snoop_fanout::total 434821 # Request fanout histogram 724system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 725system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 726system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 727system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 728system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 729system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 730system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 731system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 732system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 733system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 734system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 735system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 736system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 737system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 738system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 739system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 740system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 741system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 742system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 743system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 744system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 745system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 746system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 747system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 748system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 749system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 750system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 751system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 752system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 753system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 754system.realview.ethernet.droppedPackets 0 # number of packets dropped 755system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 756system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 757system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 758system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 759system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 760system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 761system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 762system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 763system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 764system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 765 766---------- End Simulation Statistics ---------- 767