stats.txt revision 10585
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.783867 # Number of seconds simulated 4sim_ticks 2783867165000 # Number of ticks simulated 5final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1064003 # Simulator instruction rate (inst/s) 8host_op_rate 1295252 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20746494205 # Simulator tick rate (ticks/s) 10host_mem_usage 558936 # Number of bytes of host memory used 11host_seconds 134.19 # Real time elapsed on the host 12sim_insts 142773109 # Number of instructions simulated 13sim_ops 173803334 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s) 54system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 55system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 56system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 57system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 58system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 59system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 60system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 63system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 64system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 65system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 66system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 67system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 68system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 69system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 70system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 71system.cf0.dma_write_txs 631 # Number of DMA write transactions. 72system.cpu_clk_domain.clock 500 # Clock period in ticks 73system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 74system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 75system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 76system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 77system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 78system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 79system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 80system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 81system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 82system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 83system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 84system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 85system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 86system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 87system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 88system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 89system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 90system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 91system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 92system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 93system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 94system.cpu.dtb.inst_hits 0 # ITB inst hits 95system.cpu.dtb.inst_misses 0 # ITB inst misses 96system.cpu.dtb.read_hits 31526301 # DTB read hits 97system.cpu.dtb.read_misses 8581 # DTB read misses 98system.cpu.dtb.write_hits 23124463 # DTB write hits 99system.cpu.dtb.write_misses 1448 # DTB write misses 100system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 101system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 102system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 103system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 104system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB 105system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 106system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 107system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 108system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 109system.cpu.dtb.read_accesses 31534882 # DTB read accesses 110system.cpu.dtb.write_accesses 23125911 # DTB write accesses 111system.cpu.dtb.inst_accesses 0 # ITB inst accesses 112system.cpu.dtb.hits 54650764 # DTB hits 113system.cpu.dtb.misses 10029 # DTB misses 114system.cpu.dtb.accesses 54660793 # DTB accesses 115system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 116system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 117system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 118system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 119system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 120system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 121system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 122system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 123system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 124system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 125system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 126system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 127system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 128system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 129system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 130system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 131system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 132system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 133system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 134system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 135system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 136system.cpu.itb.inst_hits 147039592 # ITB inst hits 137system.cpu.itb.inst_misses 4762 # ITB inst misses 138system.cpu.itb.read_hits 0 # DTB read hits 139system.cpu.itb.read_misses 0 # DTB read misses 140system.cpu.itb.write_hits 0 # DTB write hits 141system.cpu.itb.write_misses 0 # DTB write misses 142system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 143system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 144system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 145system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 146system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 147system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 148system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 149system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 150system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 151system.cpu.itb.read_accesses 0 # DTB read accesses 152system.cpu.itb.write_accesses 0 # DTB write accesses 153system.cpu.itb.inst_accesses 147044354 # ITB inst accesses 154system.cpu.itb.hits 147039592 # DTB hits 155system.cpu.itb.misses 4762 # DTB misses 156system.cpu.itb.accesses 147044354 # DTB accesses 157system.cpu.numCycles 5567737414 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 142773109 # Number of instructions committed 161system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 164system.cpu.num_func_calls 16873879 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls 166system.cpu.num_int_insts 153162826 # number of integer instructions 167system.cpu.num_fp_insts 11484 # number of float instructions 168system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read 169system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written 170system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written 174system.cpu.num_mem_refs 55939365 # number of memory refs 175system.cpu.num_load_insts 31855962 # Number of load instructions 176system.cpu.num_store_insts 24083403 # Number of store instructions 177system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles 178system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles 179system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.968015 # Percentage of idle cycles 181system.cpu.Branches 36397028 # Number of branches fetched 182system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction 184system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction 187system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction 188system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction 189system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction 190system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction 191system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction 192system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction 193system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction 194system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction 195system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction 196system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction 197system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction 198system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction 199system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction 200system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction 201system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction 202system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction 203system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction 204system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction 205system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction 206system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction 207system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction 208system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction 209system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 212system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction 213system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 177220138 # Class of executed instruction 217system.cpu.kern.inst.arm 0 # number of arm instructions executed 218system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed 219system.cpu.dcache.tags.replacements 819403 # number of replacements 220system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use 221system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks. 222system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks. 223system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks. 224system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 225system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 226system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 227system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 228system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 233system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses 234system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses 235system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits 236system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits 237system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits 238system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits 239system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits 240system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits 241system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits 242system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits 243system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits 244system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits 245system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits 246system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits 247system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits 248system.cpu.dcache.overall_hits::total 52864309 # number of overall hits 249system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses 250system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses 251system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses 252system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses 253system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses 254system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses 255system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses 256system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses 257system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 258system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 259system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses 260system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses 261system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses 262system.cpu.dcache.overall_misses::total 814075 # number of overall misses 263system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses) 264system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses) 265system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses) 266system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses) 267system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) 268system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) 269system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) 270system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) 271system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) 272system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) 273system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses 274system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses 275system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses 276system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses 277system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses 278system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses 279system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses 280system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses 281system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses 282system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses 283system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses 284system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses 285system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 286system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 287system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses 288system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses 289system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses 290system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses 291system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 292system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 293system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 295system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 297system.cpu.dcache.fast_writes 0 # number of fast writes performed 298system.cpu.dcache.cache_copies 0 # number of cache copies performed 299system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks 300system.cpu.dcache.writebacks::total 682060 # number of writebacks 301system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 302system.cpu.icache.tags.replacements 1699220 # number of replacements 303system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use 304system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks. 305system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks. 306system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks. 307system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. 308system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor 309system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy 310system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy 311system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 312system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 313system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id 314system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 315system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 316system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 317system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses 318system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses 319system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits 320system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits 321system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits 322system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits 323system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits 324system.cpu.icache.overall_hits::total 145342961 # number of overall hits 325system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses 326system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses 327system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses 328system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses 329system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses 330system.cpu.icache.overall_misses::total 1699738 # number of overall misses 331system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses) 332system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses) 333system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses 334system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses 335system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses 336system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses 337system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses 338system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses 339system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses 340system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses 341system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses 342system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses 343system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 344system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 345system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 346system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 347system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 348system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 349system.cpu.icache.fast_writes 0 # number of fast writes performed 350system.cpu.icache.cache_copies 0 # number of cache copies performed 351system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 352system.cpu.l2cache.tags.replacements 110027 # number of replacements 353system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use 354system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks. 355system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. 356system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks. 357system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 358system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor 359system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor 360system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor 361system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor 362system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor 363system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy 364system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 365system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 366system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy 367system.cpu.l2cache.tags.occ_percent::cpu.data 0.109777 # Average percentage of cache occupancy 368system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy 369system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 370system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id 371system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 372system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 373system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id 374system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id 375system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id 376system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id 377system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 378system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id 379system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses 380system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses 381system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits 382system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits 383system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits 384system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits 385system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits 386system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits 387system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits 388system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 389system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits 390system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits 391system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits 392system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits 393system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits 394system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits 395system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits 396system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits 397system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits 398system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits 399system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits 400system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits 401system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits 402system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 403system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 404system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses 405system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses 406system.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses 407system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses 408system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses 409system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 410system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 411system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses 412system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses 413system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 414system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 415system.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses 416system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses 417system.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses 418system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 419system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 420system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses 421system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses 422system.cpu.l2cache.overall_misses::total 181765 # number of overall misses 423system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) 424system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) 425system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses) 426system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses) 427system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses) 428system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses) 429system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses) 430system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) 431system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) 432system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 433system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 434system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) 435system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) 436system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses 437system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses 438system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses 439system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses 440system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses 441system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses 442system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses 443system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses 444system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses 445system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses 446system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses 447system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses 448system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses 449system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses 450system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses 451system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses 452system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses 453system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 454system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 455system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses 456system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses 457system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses 458system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses 459system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses 460system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses 461system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses 462system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses 463system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses 464system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses 465system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses 466system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses 467system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 468system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 469system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 470system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 471system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 472system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 473system.cpu.l2cache.fast_writes 0 # number of fast writes performed 474system.cpu.l2cache.cache_copies 0 # number of cache copies performed 475system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks 476system.cpu.l2cache.writebacks::total 101898 # number of writebacks 477system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 478system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution 480system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution 481system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution 482system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution 483system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution 484system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 485system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution 486system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution 487system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution 488system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes) 489system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes) 490system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) 491system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) 492system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes) 493system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes) 494system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes) 495system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) 496system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) 497system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes) 498system.cpu.toL2Bus.snoops 36631 # Total snoops (count) 499system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram 500system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram 501system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram 502system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 503system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 504system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 505system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 506system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 507system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 508system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram 509system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram 510system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 511system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 512system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 513system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram 514system.iobus.trans_dist::ReadReq 30171 # Transaction distribution 515system.iobus.trans_dist::ReadResp 30171 # Transaction distribution 516system.iobus.trans_dist::WriteReq 59016 # Transaction distribution 517system.iobus.trans_dist::WriteResp 22792 # Transaction distribution 518system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 519system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) 520system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 521system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 522system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 523system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 524system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 525system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 526system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 527system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 528system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 529system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 530system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 531system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 532system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 533system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 534system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 535system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 536system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 537system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 538system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 539system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 540system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) 541system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) 542system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) 543system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) 544system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) 545system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 546system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 547system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 548system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 549system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 550system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 551system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 552system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 553system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 554system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 555system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 556system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 557system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 558system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 559system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 560system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 561system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 562system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 563system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 564system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 565system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) 566system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) 567system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) 568system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) 569system.iocache.tags.replacements 36430 # number of replacements 570system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use 571system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 572system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. 573system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 574system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. 575system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor 576system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy 577system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy 578system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 579system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 580system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 581system.iocache.tags.tag_accesses 328176 # Number of tag accesses 582system.iocache.tags.data_accesses 328176 # Number of data accesses 583system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses 584system.iocache.ReadReq_misses::total 240 # number of ReadReq misses 585system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 586system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 587system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses 588system.iocache.demand_misses::total 240 # number of demand (read+write) misses 589system.iocache.overall_misses::realview.ide 240 # number of overall misses 590system.iocache.overall_misses::total 240 # number of overall misses 591system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) 592system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) 593system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 594system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 595system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses 596system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses 597system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses 598system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses 599system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 600system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 601system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 602system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 603system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 604system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 605system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 606system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 607system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 608system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 609system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 610system.iocache.blocked::no_targets 0 # number of cycles access was blocked 611system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 612system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 613system.iocache.fast_writes 0 # number of fast writes performed 614system.iocache.cache_copies 0 # number of cache copies performed 615system.iocache.writebacks::writebacks 36190 # number of writebacks 616system.iocache.writebacks::total 36190 # number of writebacks 617system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 618system.membus.trans_dist::ReadReq 74235 # Transaction distribution 619system.membus.trans_dist::ReadResp 74235 # Transaction distribution 620system.membus.trans_dist::WriteReq 27560 # Transaction distribution 621system.membus.trans_dist::WriteResp 27560 # Transaction distribution 622system.membus.trans_dist::Writeback 138088 # Transaction distribution 623system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 624system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 625system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution 626system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 627system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution 628system.membus.trans_dist::ReadExReq 146085 # Transaction distribution 629system.membus.trans_dist::ReadExResp 146085 # Transaction distribution 630system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) 631system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 632system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) 633system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes) 634system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes) 635system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) 636system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) 637system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes) 638system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) 639system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 640system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) 641system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes) 642system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes) 643system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) 644system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) 645system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes) 646system.membus.snoops 0 # Total snoops (count) 647system.membus.snoop_fanout::samples 359047 # Request fanout histogram 648system.membus.snoop_fanout::mean 1 # Request fanout histogram 649system.membus.snoop_fanout::stdev 0 # Request fanout histogram 650system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 651system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 652system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram 653system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 654system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 655system.membus.snoop_fanout::min_value 1 # Request fanout histogram 656system.membus.snoop_fanout::max_value 1 # Request fanout histogram 657system.membus.snoop_fanout::total 359047 # Request fanout histogram 658system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 659system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 660system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 661system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 662system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 663system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 664system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 665system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 666system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 667system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 668system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 669system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 670system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 671system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 672system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 673system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 674system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 675system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 676system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 677system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 678system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 679system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 680system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 681system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 682system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 683system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 684system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 685system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 686system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 687system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 688system.realview.ethernet.droppedPackets 0 # number of packets dropped 689 690---------- End Simulation Statistics ---------- 691